TWI512826B - Dry etching method - Google Patents
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- TWI512826B TWI512826B TW100127420A TW100127420A TWI512826B TW I512826 B TWI512826 B TW I512826B TW 100127420 A TW100127420 A TW 100127420A TW 100127420 A TW100127420 A TW 100127420A TW I512826 B TWI512826 B TW I512826B
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- 238000000034 method Methods 0.000 title claims description 76
- 238000001312 dry etching Methods 0.000 title description 8
- 238000005530 etching Methods 0.000 claims description 52
- 230000008569 process Effects 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 238000001020 plasma etching Methods 0.000 claims description 16
- 238000005498 polishing Methods 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 238000003672 processing method Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 238000010169 landfilling Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000007789 gas Substances 0.000 description 48
- 239000011229 interlayer Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 238000012545 processing Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005429 filling process Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32192—Microwave generated discharge
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- General Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Description
本發明關於使用電漿之乾蝕刻方法。
近年來，伴隨半導體裝置之高性能化，組合高介電率之閘極絕緣膜以及雙金屬閘極之技術已經實用化，伴隨此而可以解決驅動電流之降低或漏電流之增大。作為彼等之製造方法有習知之閘極電極加工方法的先閘極方式(gate fast type)及後閘極方式(gate last type)之2種。
後閘極方式，係以多晶矽等之材料形成虛擬閘極，在源極/汲極形成後於該虛擬閘極間填埋層間氧化膜，除去虛擬閘極。在藉由虛擬閘極之除去而形成之溝部分填埋金屬材料，藉由CMP(Chemical Mechanical Polishing)研磨填埋之金屬材料而形成金屬閘極之方法(參照專利文獻1)。
上述後閘極方式，需要藉由乾蝕刻除去虛擬閘極而形成溝之工程。另外，形成該溝時，有可能需要實施該溝之上部之圓弧化處理(round)。亦即有可能需要在虛擬閘極之除去而形成之溝設置頂部圓弧(top round)。
於半導體基板表面實施上部角部之圓弧化而形成溝槽之方法被揭示於專利文獻2。
專利文獻1：特開2005-19892號公報
專利文獻2：特開2005-26662號公報
但是，上述習知技術為使用遮罩之溝槽形成方法，未考慮到不使用遮罩之溝之形成。另外，藉由虛擬閘極之除去而形成溝的方法乃屬於不使用遮罩之溝形成方法。
因此，欲於藉由虛擬閘極之除去而形成之溝或孔設置頂部環時，難以直接適用上述習知技術。另外，該問題乃在藉由虛擬材料之除去而形成之溝或孔設置頂部環的乾蝕刻方法所共通者。
本發明提供乾蝕刻方法，其可在藉由虛擬材料之除去而形成之溝或孔容易設置頂部圓弧。
本發明之乾蝕刻方法，係在層間氧化膜藉由除去包圍其周圍之虛擬材料而形成溝或孔者；其特徵為：蝕刻上述虛擬材料直至特定深度，於上述蝕刻後進行等向性蝕刻，等向性蝕刻後除去上述虛擬材料之殘部。
本發明之後閘極方式之金屬閘極製造方法，係在藉由虛擬閘極之除去而形成之溝填埋金屬膜，藉由研磨上述金屬膜而形成金屬閘極者；其特徵為具有：圓弧調整工程，用於蝕刻上述虛擬閘極直至特定深度；圓弧形成工程，係在上述圓弧調整工程後藉由等向性蝕刻而形成圓弧；主蝕刻工程，在上述圓弧形成工程後除去上述虛擬閘極之殘部；填理工程，係在上述主蝕刻工程後進行金屬膜之填埋；及研磨工程，用於研磨上述被填埋之金屬膜。
本發明之乾蝕刻方法，係在層間氧化膜藉由除去包圍其周圍之虛擬材料而形成溝或孔者；其特徵為：蝕刻上述虛擬材料直至特定深度，於上述蝕刻後進行等向性蝕刻，等向性蝕刻後除去上述虛擬材料之殘部。
以下參照圖面說明本發明之一實施形態。
本實施形態說明之本發明之適用例，為使用後閘極方式之High-k材料之閘極絕緣膜的金屬閘極形成方法。
首先，說明本實施形態使用之電漿蝕刻裝置。
圖1表示本實施形態使用之電漿蝕刻裝置之概略縱斷面圖。
在上部為開放之真空容器101上部，設置將蝕刻氣體導入真空容器101內之石英製之噴氣板104及石英製之介電窗105予以密封而形成處理室106。於噴氣板104被連接流入蝕刻氣體之氣體供給裝置107。另外，真空容器101之內部，係藉由通過真空排氣口108而連接之真空排氣裝置(未圖示)實施減壓排氣。
為使電漿產生用之電力傳送至處理室106，而於介電窗105上方設置電磁波傳送用之導波管109。傳送至導波管109之微波，係由磁控管103振盪產生。又，磁控管103振盪產生之微波頻率為2.45GHz。於處理室106外周部設置磁場產生用之磁場產生線圈110，藉由磁控管103振盪產生之微波，和磁場產生線圈110產生之磁場之相互作用，於處理室106內產生高密度電漿。另外，和噴氣板104呈對向，而於真空容器101下方設置試料台102用於載置晶圓111。試料台102，其表面被溶射膜(未圖示)覆蓋，係介由高頻濾波器114連接於直流電源115。另外，試料台102，係介由匹配電路112連接於高頻電源113。
藉由搬送手段(未圖示)被搬送至處理室106內，載置於試料台102的晶圓111，係藉由直流電源115所施加之直流電壓之靜電力被吸附於試料台102之表面，藉由氣體供給裝置107介由噴氣板104將蝕刻氣體供給至處理室106內，設定真空容器101內成為特定壓力，使通過導波管109及介電窗105導入處理室106內之微波，和磁場產生線圈110產生之磁場，產生相互作用而於處理室106內產生高密度電漿。另外，由高頻電源113將高頻電力施加於試料台102，由電漿將離子引入載置於試料台102之晶圓111，對晶圓111具有之被蝕刻膜進行離子輔助蝕刻(ion assist etching)，而可以實施異方性蝕刻。
說明本實施形態使用之晶圓111。如圖2(a)所示，晶圓111，係於矽基板201上有暫時之閘極之虛擬閘極202，於虛擬閘極202上有自然氧化膜205，於虛擬閘極202之側壁有薄的絕緣膜204，於絕緣膜204外側有層間氧化膜203被配置之構造。
針對具有此種構造之晶圓111使用上述電漿蝕刻，依據以下順序，使用後閘極方式之High-k材料之閘極絕緣膜進行金屬閘極之形成。
首先，如圖2(b)所示，使用Cl2
氣體，使用處理壓力設為0.2Pa，微波電力設為800W之電漿，進行施加80W之高頻電力而除去自然氧化膜205之貫穿(break through)工程。
於該貫穿工程，和填埋特性良好之層間氧化膜203比較，絕緣膜204具有強的耐腐蝕性而蝕刻速度較慢，因此絕緣膜204較難被蝕刻。絕緣膜204之上部被形成為較層間氧化膜203突出之形狀之突起形狀206。之後，如圖2(c)所示，使用Cl2
氣體與O2
氣體與HBr氣體與Ar氣體之混合氣體，使用處理壓力設為0.4Pa，微波電力設為800W之電漿，施加80W之高頻電力而進行至特定深度為止除去虛擬閘極202之圓弧調整工程。特定深度係指在欲圓弧處理絕緣膜204上部之量之範圍內，使絕緣膜204相接於虛擬閘極202之側壁成露出之深度。
因此，藉由調整特定深度，可以配合半導體裝置來調整圓弧形狀於深度方向之大小。
該圓弧調整工程之必要之蝕刻條件為，欲使最終形成之金屬閘極之高度維持於初期之虛擬閘極之高度，提高虛擬閘極202與層間氧化膜203間之蝕刻選擇性，而在除去虛擬閘極202全部時儘可能不削去層間氧化膜203之條件。
之後，如圖2(d)所示，使用O2
氣體與CHF3
氣體之混合氣體，使用處理壓力設為0.3Pa，微波電力設為700W之電漿，不施加高頻電力而進行於絕緣膜204上部形成圓弧之圓弧形成工程。
該圓弧形成工程係藉由等向性蝕刻進行突起形狀206之蝕刻工程使成為圓弧形狀。於該圓弧形成工程可以形成圓弧之理由如下。
於等向性蝕刻之蝕刻，蝕刻劑之衝撞機率較高之處會被選擇性蝕刻，因此，突起形狀206會被選擇性蝕刻除去，而使絕緣膜204上部成為圓弧形狀。
藉由調整該圓弧形成工程之蝕刻時間，可調整絕緣膜204上部之圓弧量。於該圓弧形成工程亦可控制圓弧形狀之大小。
通常，隨高頻電力增加射入之離子能量亦增加，異方性蝕刻變為容易。另外，隨著作用於蝕刻之射入離子能量之增加，蝕刻速度被加速。因此，於圓弧形成工程中，高頻電力較低為較好，較好是0W。此乃因為，射入高能量離子時，露出之層間氧化膜203之蝕刻會被加速，層間氧化膜203之削去量變多。另外，隨高頻電力之增加蝕刻速度亦增加，圓弧形狀控制用之蝕刻時間調整變為困難。
因此，藉由施加低的高頻電力之同時，進行等向性蝕刻，可抑制層間氧化膜203之削去量，於所要蝕刻時間有效形成圓弧形狀。因此，上述圓弧形成工程需要設為高頻電力為0W/cm2
以上0.042W/cm2
以下，離子射入能量需要設為0eV/cm2
以上0.24eV/cm2
以下。
又，於上述圓弧形成工程使用CHF3
氣體作為主蝕刻氣體，但亦可使用CF4
氣體、SF6
氣體、NF3
氣體、CH2
F2
氣體、CH3
F氣體、C4
F8
氣體等含氟氣體，於絕緣膜204上部形成圓弧。
絕緣膜204上部之圓弧形狀調整，除上述圓弧形成工程之蝕刻時間、高頻電力以外，亦可藉由含氟氣體與O2
氣體之混合比率之調整來控制。其理由如下。
主蝕刻氣體為CHF3
氣體時，藉由電漿之解離而產生碳、氫、氟之自由基或離子。蒸汽壓高的反應生成物會由真空容器101介由真空排氣口108排氣，但蒸汽壓低的反應生成物會附著於蝕刻之被蝕刻膜表面。該附著物發揮作為蝕刻之保護膜機能，而抑制蝕刻速度。附著物極端厚時，亦有可能不進行蝕刻。通常，在被蝕刻膜表面離子照射較少之處會附著較厚。
蝕刻氣體使用CHF3
氣體時，附著物較多者為含碳化合物，因此藉由添加O2
氣體，使附著物之碳與O2
氣體之氧反應物產生高揮發性之CX
OY
，可減少附著物。因此，藉由O2
氣體之添加量可調整絕緣膜204上部之蝕刻速度，可控制圓弧形狀之大小。
本實施形態之圓弧形成工程，藉由對CHF3
氣體流量添加約15%之O2
氣體可獲得最佳之圓弧形狀。該O2
氣體之添加量，需要依據使用之含氟氣體種類或欲形成之圓弧形狀之大小實施最佳化，但是超出30%之O2
氣體之添加時，氧與氧化膜中之矽之反應，會導致被蝕刻表面形成矽氧化膜，無法進行蝕刻。另外，SF6
氣體、NF3
氣體等在不添加O2
氣體之情況下蝕刻亦會被進行，因此較好是在0%~3%之間調整O2
氣體之添加量。
另外，等向性蝕刻雖有濕蝕刻，但於上述圓弧形成工程適用濕蝕刻時將增加其他工程，增加成本。因此，於本實施形態中，於上述圓弧形成工程適用乾蝕刻之等向性蝕刻，則可抑制半導體裝置之成本上升。
之後，如圖2(e)所示，使用Cl2
氣體與O2
氣體與HBr氣體與Ar氣體之混合氣體，使用處理壓力設為0.4Pa，微波電力設為800W之電漿，施加80W之高頻電力，而進行除去上述圓弧形成工程後殘留之虛擬閘極202之主蝕刻工程。
該主蝕刻工程，係和上述圓弧調整工程同樣，會影響最終之金屬閘極之高度，因此需要提高虛擬閘極202與層間氧化膜203之間之蝕刻選擇性，在虛擬閘極202之除去時儘可能不要削去層間氧化膜203。
該主蝕刻工程後，如圖2(e)所示，突起形狀206被消除，可於絕緣膜204上部形成具有圓弧形狀之溝。亦即，可形成具有頂部圓弧之溝。
之後，如圖2(f)所示，進行填理工程而將High-k材料之閘極絕緣膜(未圖示)與金屬膜207填埋於虛擬閘極202被除去後而形成之溝。
該填埋工程之後，藉由CMP(化學機械研磨)研磨被沈積於層間氧化膜203上之High-k材料之閘極絕緣膜(未圖示)與金屬膜207，而可以形成使用High-k材料之閘極絕緣膜的金屬閘極。
如上述說明，本實施形態中，溝之形成用之遮罩不存在之情況下，亦可於溝形成頂部圓弧。
以下參照圖面說明藉由在溝不形成頂部圓弧之後閘極方式，來形成使用High-k材料之閘極絕緣膜的金屬閘極之形成方法。
如圖3所示，依序進行如圖3(b)所示貫穿工程、如圖3(c)所示主蝕刻工程及如圖3(d)所示填埋工程。其中，圖3(b)所示貫穿工程、圖3(c)所示主蝕刻工程及圖3(d)所示填理工程，分別和上述說明之圖2(b)所示貫穿工程、圖2(e)所示主蝕刻工程及圖2(f)所示填理工程為同一處理，因此省略說明。
依據圖3之後閘極方式形成金屬閘極時，貫穿工程所形成之突起形狀206在虛擬閘極202之除去後亦殘留，導致填埋工程中之金屬膜207之填埋變為困難，產生空隙(孔洞208)。該孔洞208導致無法形成滿足半導體裝置之設計規格的金屬閘極。
該孔洞208之產生之原因出自於，依據圖3之後閘極方式形成金屬閘極之方法中，絕緣膜204上部無法形成為圓弧形狀。
相對於此，依據本發明圖2之後閘極方式形成金屬閘極之方法中，絕緣膜204上部可以形成為圓弧形狀，可以在不產生孔洞208之情況下，填埋金屬膜207。因此，本發明可以提升虛擬閘極除去後填埋金屬膜時之填埋特性，有助於半導體裝置之性能及良品率之提升。
以上本實施形態中雖說明藉由後閘極方式形成金屬閘極之方法，但不限定於此，本發明亦適用於以下之情況下，例如電極與電極之連接等之柱塞(plug)形成工程，或者配線與配線之連接等之貫穿孔(其他如接觸點(contact)、導孔(via)、貫穿導孔(hole))形成工程等之形成用於填埋金屬膜之孔。
例如亦適用於深溝(deep trench)工程、雙鑲嵌(dual damascene)工程、STI(淺溝絕緣(shallow trench isolation))工程等。
又，本實施形態中說明使用微波之ECR(Electron Cyclotron Resonance)電漿蝕刻裝置，但本發明可以適用任一電漿之產生方法。另外，本發明亦適用螺旋波(helicon wave)電漿蝕刻裝置、感應耦合型電漿蝕刻裝置、容量耦合型電漿蝕刻裝置等。
藉由本發明之構成，可在藉由虛擬材料之除去而形成之溝或孔容易設置頂部環。
101．．．真空容器
102．．．試料台
103．．．磁控管
104．．．噴氣板
105．．．介電窗
106．．．處理室
107．．．氣體供給裝置
108．．．真空排氣口
109．．．導波管
110．．．磁場產生線圈
111．．．晶圓
112．．．匹配電路
113．．．高頻電源
114．．．高頻濾波器
115．．．直流電源
201．．．矽基板
202．．．虛擬閘極
203．．．層間氧化膜
204．．．絕緣膜
205．．．自然氧化膜
206．．．突起形狀
207．．．金屬膜
208．．．孔洞
圖1表示本發明之一實施形態使用之電漿蝕刻裝置之概略縱斷面圖。
圖2表示適用本發明之金屬閘極形成方法之說明圖。
圖3表示不適用本發明之金屬閘極形成方法之說明圖。
201．．．矽基板
202．．．虛擬閘極
203．．．層間氧化膜
204．．．絕緣膜
205．．．自然氧化膜
206．．．突起形狀
207．．．金屬膜
Claims (4)
- 一種電漿處理方法，係在藉由虛擬閘極之除去而形成之溝填埋金屬膜，藉由研磨上述金屬膜而形成後閘極方式之金屬閘極者，其特徵為具有：圓弧調整工程，係藉由電漿蝕刻除去上述虛擬閘極之一部分，而使配置於上述虛擬閘極之側壁的絕緣膜露出；圓弧形成工程，係在上述圓弧調整工程後，於上述露出的絕緣膜之上部藉由等向性電漿蝕刻而形成圓弧；及主蝕刻工程，係藉由電漿蝕刻除去在上述圓弧形成工程後殘留的虛擬閘極。
- 如申請專利範圍第1項之電漿處理方法，其中上述圓弧形成工程，係藉由使用含氟氣體與O2 氣體之混合氣體的電漿，進行等向性電漿蝕刻。
- 如申請專利範圍第2項之電漿處理方法，其中上述圓弧形成工程之電漿蝕刻，係在對形成有上述後閘極方式之金屬閘極的晶圓不供給高頻電力之狀態下進行。
- 一種後閘極方式之金屬閘極之製造方法，係在藉由虛擬閘極之除去而形成之溝填埋金屬膜，藉由研磨上述金屬膜而形成金屬閘極者，其特徵為具有：圓弧調整工程，係藉由電漿蝕刻除去上述虛擬閘極之一部分，而使配置於上述虛擬閘極之側壁的絕緣膜露出；圓弧形成工程，係在上述圓弧調整工程後，於上述露出的絕緣膜之上部藉由等向性電漿蝕刻而形成圓弧； 主蝕刻工程，係藉由電漿蝕刻除去在上述圓弧形成工程後殘留的虛擬閘極；填埋工程，係在上述主蝕刻工程後在所形成之溝填埋上述金屬膜；及研磨工程，係對在上述主蝕刻工程後形成之溝之上部藉由上述填埋工程而被沉積的金屬膜進行研磨。
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| US6713380B2 (en) * | 2001-05-16 | 2004-03-30 | Seiko Epson Corporation | Methods for dry etching at low substrate temperatures using gas chemistry including a fluorocarbon gas and a gas including oxygen |
| US6784110B2 (en) * | 2002-10-01 | 2004-08-31 | Jianping Wen | Method of etching shaped features on a substrate |
| US6875680B1 (en) * | 2003-12-30 | 2005-04-05 | Dongbu Electronics Co. Ltd. | Methods of manufacturing transistors using dummy gate patterns |
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| JP4237332B2 (ja) * | 1999-04-30 | 2009-03-11 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2005019892A (ja) | 2003-06-27 | 2005-01-20 | Semiconductor Leading Edge Technologies Inc | 半導体装置及びその製造方法 |
| KR100513799B1 (ko) | 2003-06-30 | 2005-09-13 | 주식회사 하이닉스반도체 | 트렌치형 소자분리막을 구비한 반도체 소자의 제조 방법 |
| JP4442194B2 (ja) * | 2003-11-05 | 2010-03-31 | 富士電機システムズ株式会社 | 半導体装置の製造方法 |
| JP4579611B2 (ja) * | 2004-07-26 | 2010-11-10 | 株式会社日立ハイテクノロジーズ | ドライエッチング方法 |
| JP4967313B2 (ja) * | 2005-11-09 | 2012-07-04 | ソニー株式会社 | 半導体装置の製造方法 |
| KR100905999B1 (ko) * | 2007-06-12 | 2009-07-06 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
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| US6624065B2 (en) * | 2000-10-13 | 2003-09-23 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device using a damascene metal gate |
| US6713380B2 (en) * | 2001-05-16 | 2004-03-30 | Seiko Epson Corporation | Methods for dry etching at low substrate temperatures using gas chemistry including a fluorocarbon gas and a gas including oxygen |
| US6784110B2 (en) * | 2002-10-01 | 2004-08-31 | Jianping Wen | Method of etching shaped features on a substrate |
| US6875680B1 (en) * | 2003-12-30 | 2005-04-05 | Dongbu Electronics Co. Ltd. | Methods of manufacturing transistors using dummy gate patterns |
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