TWI509711B - 超淺接面的製造方法 - Google Patents
超淺接面的製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000002019 doping agent Substances 0.000 claims description 100
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 44
- 239000002356 single layer Substances 0.000 claims description 43
- 239000010410 layer Substances 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000007943 implant Substances 0.000 claims description 30
- 229910052757 nitrogen Inorganic materials 0.000 claims description 30
- 238000002513 implantation Methods 0.000 claims description 29
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 28
- 229910052698 phosphorus Inorganic materials 0.000 claims description 26
- 239000011574 phosphorus Substances 0.000 claims description 26
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 22
- 238000005280 amorphization Methods 0.000 claims description 22
- 229910052787 antimony Inorganic materials 0.000 claims description 22
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 22
- 229910052799 carbon Inorganic materials 0.000 claims description 22
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 22
- 229910052732 germanium Inorganic materials 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052785 arsenic Inorganic materials 0.000 claims description 15
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 229910052738 indium Inorganic materials 0.000 claims description 15
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 13
- 229910052801 chlorine Inorganic materials 0.000 claims description 13
- 239000000460 chlorine Substances 0.000 claims description 13
- 230000003213 activating effect Effects 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 description 24
- 238000005468 ion implantation Methods 0.000 description 7
- 238000005224 laser annealing Methods 0.000 description 7
- 238000004151 rapid thermal annealing Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
- 229910052714 tellurium Inorganic materials 0.000 description 5
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000002086 nanomaterial Substances 0.000 description 3
- 238000002679 ablation Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005755 formation reaction Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Description
本揭露係有關一種半導體製造方法,且特別有關一種超淺接面的製造方法。
具有多數個半導體元件(包括場效電晶體(field effect transistors,FETs))在內的積體電路為近代微電子系統之基石。傳統上,場效電晶體的不同區域(舉例來說,源極/汲極與源極/汲極延伸區(source/drain and source/drain extensions))係藉由如離子佈植(ion implantation)等方法將摻雜原子引入半導體基板而形成。在引入摻雜物後,半導體基板會遭受一或多道的退火製程,例如低溫熱退火、快速熱退火、尖峰退火(spike annealing),瞬間退火(flash annealing)或雷射退火,以電性活化摻雜物。
然而,摻雜物在退火時具有往原來輪廓(profile)外圍橫向及縱向擴散或擴張的傾向,因此增加了不同元件區域之尺寸。特別是當半導體元件尺寸微縮(scaled down)時,不希望引起摻雜物的擴散。微縮元件尺寸至分子範圍時,對於製造原子組成受控制的明確定義之結構帶來基礎與技術上的挑戰。
用以完成精確控制之結構組成的一提案為自限性(self-limiting)與自組合(self-assembly)製程的整合,其所需之
奈米結構的合成與製造係由表面與化學現象操控。現需尋求一技術,使其可用以在矽結構中實現可靠的奈米尺度摻雜,例如在源極與汲極延伸區域中形成定義明確且均勻摻雜的超淺接面。傳統上依靠帶有能量之離子轟擊半導體的離子佈植製程面臨佈植範圍與陡峭性分佈(abruptness)無法降至奈米範圍、佈植離子隨機的空間分佈、與奈米結構材料無法相容,及晶體損傷的問題。固態源(sloid-source)擴散製程缺少所需的均勻性及缺少對用於微形元件製造之摻雜物區域劑量(areal dose)的掌控。然而,單層摻雜可以原子級的精確度達成受控制的半導體材料摻雜。一般來說,單層摻雜利用半導體的結晶性以形成高均勻度、可自組合,及含有共價鍵之單層,並在後續的退火步驟結合及擴散摻雜物。
例示性的單層形成反應為自限性且使得摻雜原子在半導體表面上形成確定性的覆蓋。單層摻雜與傳統摻雜技術不同處在於控制摻雜劑量的方法。舉例來說,與離子佈植相比,單層摻雜不涉及將高能量摻雜物引入半導體晶格而引起晶體損傷。然而,為了避免摻雜物損耗,傳統的單層摻雜需要一氧化物蓋層(cap layer)以在後續熱製程中保護各自摻雜物。因此,需要尋求一製造方法來提供或製造超淺接面且無需沉積及/或移除此氧化物蓋層。
本發明之實施例係揭示一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域;藉由實施一單層摻雜步驟,於非晶區域內
佈植一摻雜物;以及對半導體基板進行熱處理以活化非晶區域內之佈植摻雜物,進而於半導體基板內形成一超淺接面。
本發明之另一實施例係揭示一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域;藉由實施一第一單層摻雜步驟,於非晶區域內佈植一第一摻雜物;藉由實施一第二單層摻雜步驟,於非晶區域內佈植一第二摻雜物;以及對半導體基板進行熱處理以活化非晶區域內之此些佈植摻雜物,進而於半導體基板內形成一超淺接面。
本發明之又一實施例係揭示一種超淺接面的製造方法,包括:於一半導體基板內形成一非晶區域;藉由實施一單層摻雜步驟,於非晶區域內佈植一第一摻雜物;以及活化第一摻雜物,其中活化過程包括非晶區域的再結晶(recrystallizing),其中活化第一摻雜物步驟係於上方無任何氧化物蓋層的非晶佈植區域實施。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
100、200、300‧‧‧方法
110、120、130、140、220、230、320、330、340‧‧‧步驟
112、222‧‧‧單層之摻雜物
122‧‧‧氧化物蓋層
132、204、304‧‧‧矽基板
202、302‧‧‧磊晶鍺層
203、205、303‧‧‧非晶區域
210、310‧‧‧先行非晶化佈植
321‧‧‧氮佈植層
322‧‧‧氮佈植
331‧‧‧磷佈植層
332‧‧‧磷佈植
410‧‧‧磷佈植於具有碳共佈植的鍺基板
420‧‧‧磷佈植於具有氯共佈植的鍺基板
430‧‧‧磷佈植於具有氮共佈植的鍺基板
440‧‧‧單獨磷佈植
第1圖為使用單層摻雜來製造超淺接面的一技術示意圖。
第2A及2B圖為根據本揭露一些實施例之使用單層摻雜來製造超淺接面的額外技術示意圖。
第3圖為根據本揭露一些實施例之製造超淺接面的例示性
技術示意圖。
第4圖為根據本揭露一些實施例之共佈植(co-implantation)方法圖解說明。
要瞭解的是本揭露提供許多不同的實施例或範例,以實施本揭露的不同特徵。而本揭露是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本揭露。本揭露的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述外觀結構之間的關係。
本文所使用的用語係用來描述特定的實施例,而非用來限定所附之請求項。舉例來說,除非特別限定,否則單數形式的用語”一”或”該”亦可代表複數形式。如”第一”及”第二”等用語係用來描述不同的元件、區域及層等,儘管這些用語係僅用來區別一元件、一區域或一層與另一元件、另一區域或另一層。因此,在不脫離請求項主體內容之精神內,第一區域可被視為是第二區域,其他項目亦可由此類推。再者,空間相關的用語,例如「在...下」、「在...上」、「上方」、「下方」等,係用於描述在圖式中之一元件或一特徵物與另一元件或另一特徵物之間的關係。要了解的是這些空間相關的用語意圖包括元件除圖式所示的方位之外的方位。舉例來說,若圖式中元件被上下翻轉,則被敘述成在其他元件或特徵物下或下方的元件將變成在上方。因此,所用來作為範例的用詞「下方」可包括
「上方」及「下方」兩方位。
第1圖為使用單層摻雜(MLD)來製造超淺接面的一技術示意圖。參照第1圖,其繪示出使用單層摻雜來製造超淺接面的例示性技術100,在步驟110中,當矽基板132暴露於含有摻雜物的前驅物(precursor)中時,單層之摻雜物112會組合於矽結構表面上。儘管未繪示於圖中,但一般會在基板與含有摻雜物的前驅物反應前藉由氫氟酸(HF)去除原生之氧化矽層。典型的摻雜物包含但不限於:硼、鋁、鎵、銦、鉈、氮、磷、砷、銻及鉍等所列舉之例。在步驟120中,包括二氧化矽(SiO2
)、氮氧化矽(SiON)或其他阻障材料的氧化物蓋層(oxide cap)122係沉積於上述單層上以避免在後續熱處理過程中的摻雜物損耗,舉例來說,如退火過程中摻雜物的外洩(outgassing)。此氧化物蓋層122可藉由化學氣相沉積、電子束蒸鍍或其他合適的沉積技術來沉積並在之後進行選擇性蝕刻。在步驟130中,此結構經歷熱處理以破壞摻雜物分子,並使摻雜物原子112藉熱擴散進入矽基板132以形成超淺接面。例示性的熱處理包括但不限於:低溫熱退火、快速熱退火、尖峰退火(spike annealing),瞬間退火(flash annea1ing)或雷射退火。在步驟140中,氧化物蓋層係藉由如氫氟酸蝕刻等傳統方法來去除。
第2A及2B圖為根據本揭露一些實施例之使用單層摻雜來製造超淺接面的額外技術示意圖。參照第2A圖,其繪示出使用單層摻雜來製造超淺接面的例示性技術200,其中先行非晶化佈植(PAI)步驟210實施於位於矽基板204上之磊晶鍺層202上。在第2B圖中,先行非晶化佈植步驟210實施於矽基板204
上。先行非晶化佈植步驟可以任何所需的摻雜物、劑量且/或能量來實施。劑量及能量可依據欲形成之結構的需求,特別是依據所需的非晶層深度來選擇。可用於先行非晶化佈植之摻雜物的不侷限範例為:鍺、氮、銦、砷、硼、碳、氙、銻及氬等所列舉之例。此外,摻雜物的選擇可取決於各自基板所用的半導體材料。因此,例示性的先行非晶化佈植步驟210有助於活化後續引入之摻雜物,原因在於其結構表面的非晶性及對後續摻雜製程其各自的親合力。舉例來說,先行非晶化佈植可用以形成佈植區域,其為位於各自結構上表面之下的非晶矽。就第2A圖所繪之例而言,非晶區域203係形成於磊晶鍺層202內。就第2B圖所繪之例而言,非晶區域205係形成於矽基板204內。此非晶區域或非晶層的深度取決於上述之劑量與能量並可介於結構之上表面下方10至15奈米處。在一些實施例中,此非晶區域或非晶層之深度需深於活化摻雜物之尖峰濃度(peak concentration),以確保所有活化摻雜物均包含在先行非晶化佈植區域內。
在步驟220中,採用一例示性的單層摻雜技術,當各自結構的表面暴露於含有摻雜物的前驅物時,其單層之摻雜物222會組合於其上。典型的單層摻雜技術可應用於”由下至上”(“bottom-up”)或”由上至下”(“top-down”)方法所製作的各種奈米結構材料的p型或n型摻雜,使其可多方面適用於各種應用。單層摻雜技術的一重要特徵為其使用自限性反應以在結晶鍺或矽表面上形成高均勻度的單層,使其可以分子級精確度形成以化學吸附含有摻雜物之分子之定義明確的表層。此對於在
後續熱處理製程中形成高度受控且均勻的奈米尺度摻雜輪廓是十分重要的。區域摻雜劑量亦可藉由各自前驅物的分子印記(molecular footprint)來調整,較小的分子可配合較高的劑量。熱處理製程的時間及溫度亦可用來調節精確的接面深度。因此,後續熱處理製程條件與前驅物之分子設計的結合可提供廣大的摻雜輪廓範圍以符合所需應用或所致結構的特定需求。例示性的摻雜物包括但不限於:硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍等所列舉之例。就第2A圖所繪之例而言,由於實施前述先行非晶化佈植步驟之故,與第1圖所繪之方法相比,可於磊晶鍺層202內的非晶區域203捕捉更多的摻雜物。就第2B圖所繪之例而言,由於實施前述先行非晶化佈植步驟之故,與第1圖所繪之方法相比,可於矽基板204內的非晶區域205捕捉更多的摻雜物。儘管單層摻雜係繪示於第2A圖及第2B圖中,但並非用以限制所附之請求項,所有例示性的離子佈植步驟均可用於本發明之實施例。此外,單一單層摻雜步驟的圖式並非用以限制所附請求項之範圍,多重單層摻雜程序或步驟亦可展望為用以提供額外的摻雜物佈植於例示性結構中。在步驟230中,各自的結構經歷熱處理以破壞摻雜物分子,並使摻雜物原子藉熱擴散進入結構以形成超淺接面。例示性的熱處理包括但不限於:低溫熱退火、快速熱退火、尖峰退火,瞬間退火或雷射退火。在熱處理步驟230中,固態磊晶層中非晶區域的再成長可能如圖式般發生。
第3圖為根據本揭露一些實施例之製造超淺接面的例示性技術示意圖。參照第3圖,其所繪示出例示性的超淺
接面製造技術300,其先行非晶化佈植步驟310實施於位於矽基板304上之磊晶鍺層302上,以於磊晶鍺層302中形成非晶區域303。儘管所繪為磊晶鍺層,先行非晶化佈植步驟310可實施於任何包含矽基板(未繪示)的裝置或層中。先行非晶化佈植步驟可以任何所需的摻雜物、劑量且/或能量來實施。劑量及能量可依據欲形成之結構的需求,特別是依據其深度來選擇。可用於先行非晶化佈植之摻雜物的不侷限範例為:鍺、硼、碳、氮、銦、砷、氙、銻及氬等所列舉之例。此外,摻雜物的選擇可取決於各自基板所用的半導體材料。例示性的先行非晶化佈植步驟310有助於活化後續引入之摻雜物。舉例來說,先行非晶化佈植可用以形成佈植區域,其為位於各自結構上表面之下的非晶矽。此非晶化的深度取決於上述之劑量與能量並可介於結構之上表面下方10至15奈米處。在一些實施例中,此非晶區域或非晶層之深度需深於活化摻雜物之尖峰濃度,以確保所有活化摻雜物均包含在先行非晶化佈植區域內。
在步驟320中,一例示性的離子佈植技術係用以在結構表面上方組合摻雜物層。在所繪示之範例中,氮佈植步驟322可以6KeV的佈植能量來實施,以形成深度約125埃(Å)的氮佈植層321。這些數值僅為範例而非用以限定所附請求項之範圍,任何合適的佈植能量皆可用以形成各自摻雜物所需的佈植深度。在一些實施例中,採用一例示性的單層摻雜技術,當各自結構的表面暴露於含有摻雜物的前導物時,其單層的摻雜物會組合於其上。例示性的摻雜物包括但不限於:硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍等所列舉之例。在另外
的實施例中,傳統的離子佈植方法可用以取代單層摻雜。在步驟330中,一第二離子佈植技術用以於結構表面上方組合第二摻雜物層。在所繪示之範例中,磷佈植步驟332以2KeV的佈植能量來實施,以形成深度淺於氮佈植層321的磷佈植層331。當然,此能量數值僅為範例而非用以限定所附請求項之範圍,任何合適的佈植能量皆可用以形成各自摻雜物所需的佈植深度。需要注意的是由於實施前述先行非晶化佈植步驟310之故,可於磊晶鍺層302內的非晶區域303捕捉更多的摻雜物(無論是單一或多重摻雜物)。一般而言,磷會於鍺基板中擴散。因此,在本發明的一些實施例中,為了抑制磷在基板內的擴散,可引進氮共佈植(co-implant)技術以形成高活化的磷源極/汲極延伸區(source/drain extension,SDE)接面。當然,亦可採用其他共佈植物來抑制磷的擴散,包括但不限於:碳共佈植、氯共佈植及其類似共佈植物。在步驟340中,各自的結構經歷熱處理以破壞摻雜物分子,並使摻雜物原子藉熱擴散進入結構以形成超淺接面。例示性的熱處理包括但不限於:低溫熱退火、快速熱退火、尖峰退火,瞬間退火或雷射退火。在熱處理步驟340中,固態磊晶層中非晶區域的再成長可能會發生。
第4圖為根據本揭露一些實施例之共佈植方法圖解說明。參照第4圖,四條描記線(trace)係代表磷濃度對深度關係,分別為:磷佈植於具有碳共佈植的鍺基板410,其片電阻為639ohm/sq;磷佈植於具有氯共佈植的鍺基板420,其片電阻為233ohm/sq;磷佈植於具有氮共佈植的鍺基板430,其片電阻為341ohm/sq;以及單獨磷佈植440,其片電阻為209
ohm/sq。如第4圖所示,碳與氯共佈值的磷濃度在深度內的維持度優於單獨磷佈植,而與碳與氯共佈植相比,氮共佈植之磷濃度於深度內的維持度更佳。
因此,參照前述之圖式,本揭露之不同實施例可提供一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域;藉由實施一單層摻雜步驟,於非晶區域內佈植一摻雜物;以及對半導體基板進行熱處理以活化非晶區域內之佈植摻雜物,進而於半導體基板內形成一超淺接面。用於先行非晶化佈植步驟的摻雜物包含但不限於:鍺、硼、氮、銦、砷、碳、氙、銻及氬。用於單層摻雜步驟之佈植摻雜物包含但不限於:硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍。例示性的熱處理包括低溫熱退火、快速熱退火、尖峰退火,瞬間退火或雷射退火。在本發明的一些實施例中,熱處理步驟係於上方無任何氧化物蓋層的非晶佈植區域實施。
本揭露額外的實施例提供一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域;藉由實施一第一單層摻雜步驟,於非晶區域內佈植一第一摻雜物;藉由實施一第二單層摻雜步驟,於非晶區域內佈植一第二摻雜物;以及對半導體基板進行熱處理以活化非晶區域內之此些佈植摻雜物,進而於半導體基板內形成一超淺接面。用於先行非晶化佈植步驟的摻雜物包含但不限於:鍺、硼、氮、銦、砷、碳、氙、銻及氬。用於第一單層摻雜步驟之佈植摻雜物包含但不限於:硼、鋁、鎵、銦、鉈、氮、
碳、氯、磷、砷、銻及鉍。例示性的熱處理包括低溫熱退火、快速熱退火、尖峰退火,瞬間退火或雷射退火。在一些實施例中,第二摻雜物為磷且第一摻雜物為氮、氯或碳。在本發明的其他實施例中,熱處理步驟係於上方無任何氧化物蓋層的非晶佈植區域實施。
本揭露的又一實施例提供一種具有複數個活化摻雜物的超淺接面的製造方法,包括:於一半導體基板內形成一非晶區域;藉由實施一單層摻雜步驟,於非晶區域內佈植一第一摻雜物;以及活化第一摻雜物,其中活化過程包括非晶區域的再結晶,且此步驟係於上方無任何氧化物蓋層的非晶佈植區域實施。在一些實施例中,形成一非晶區域步驟包括實施一先行非晶化佈植步驟。用於先行非晶化佈植步驟的摻雜物包含但不限於:鍺、硼、氮、銦、砷、碳、氙、銻及氬。所佈植的第一摻雜物包含但不限於:硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍。例示性的熱處理包括低溫熱退火、快速熱退火、尖峰退火,瞬間退火或雷射退火。在其他的實施例中,此方法包括藉由實施一第二單層摻雜步驟,於非晶區域內佈植一第二摻雜物,此第二摻雜物深度較第一摻雜物為淺,其中活化步驟更包括活化第一摻雜物及第二摻雜物。在不同的實施例中,第二摻雜物為磷且第一摻雜物可為氮、氯或碳。
需強調的是上述之實施例,特別是任何”較佳”之實施例,係僅為可能實施之範例,及僅用以使本揭露之原理可清楚理解。上述之本揭露實施例可在不脫離本揭露之精神和原則內作出許多更動及潤飾。所有潤飾及更動均包含於本揭露範圍
且於下述之請求項保護之。
再者,以上敘述許多實施例的特徵,使所屬技術領域中具有通常知識者能夠清楚理解以下的說明。所屬技術領域中具有通常知識者能夠理解其可利用本揭露作為基礎,以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本揭露之精神和範圍的等效構造可在不脫離本揭露之精神和範圍內作任意之更動、替代與潤飾。
同樣地,儘管操作步驟係以特定的順序繪於圖中,這不應理解為需以所示之特定順序或串聯順序來實施,或需實施所有繪示出之操作步驟才能達成所需之結果。在某些情況中,多重處理及平行處理亦是有助益的。
如第1至4圖所示之不同結構與實施例,各種製造超淺接面的方法係敘述於此。
儘管本發明主體內容之較佳實施例係敘述於上,應了解的是此些實施例僅作為說明之用,當符合完全等同範圍時發明之範圍係單獨由後附之請求項來定義,且所屬技術領域中具有通常知識者得從其相關閱讀中自然作出許多更動及潤飾。
300‧‧‧方法
302‧‧‧磊晶鍺層
303‧‧‧非晶區域
304‧‧‧矽基板
310‧‧‧先行非晶化佈植
320、330、340‧‧‧步驟
321‧‧‧氮佈植層
322‧‧‧氮佈植
331‧‧‧磷佈植層
332‧‧‧磷佈植
Claims (7)
- 一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域,其中該半導體基板包括鍺;藉由實施一第一單層摻雜步驟,於該非晶區域內佈植一第一摻雜物;藉由實施一第二單層摻雜步驟,於該非晶區域內佈植一第二摻雜物,其中該第二單層摻雜步驟包括磷與氮共佈植;以及對該半導體基板進行熱處理以活化該非晶區域內之該些佈植摻雜物,進而於該半導體基板內形成一超淺接面。
- 如申請專利範圍第1項所述之超淺接面的製造方法,其中用於該先行非晶化佈植步驟之一摻雜物係選自於由鍺、硼、氮、銦、砷、碳、氙、銻及氬所組成之群組。
- 如申請專利範圍第1項所述之超淺接面的製造方法,其中該第一摻雜物係選自於由硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍所組成之群組。
- 如申請專利範圍第1項所述之超淺接面的製造方法,其中該熱處理步驟係於上方無任何氧化物蓋層的該非晶佈植區域實施。
- 一種超淺接面的製造方法,包括:藉由實施一先行非晶化佈植步驟,於一半導體基板內形成一非晶區域,其中該半導體基板包括鍺; 藉由實施一單層摻雜步驟,於該非晶區域內佈植一第一摻雜物;藉由實施一第二單層摻雜步驟,於該非晶區域內佈植一第二摻雜物,其中該第二摻雜物深度較該第一摻雜物為淺,且該第二單層摻雜步驟包括磷與氮共佈植;以及活化該第一摻雜物及該第二摻雜物,其中該活化過程包括該非晶區域的再結晶;其中活化該第一摻雜物及該第二摻雜物步驟係於上方無任何氧化物蓋層的該非晶佈植區域實施。
- 如申請專利範圍第5項所述之超淺接面的製造方法,其中用於該先行非晶化佈植步驟之一摻雜物係選自於由鍺、硼、氮、銦、砷、碳、氙、銻及氬所組成之群組。
- 如申請專利範圍第5項所述之超淺接面的製造方法,其中該第一摻雜物係選自於由硼、鋁、鎵、銦、鉈、氮、碳、氯、磷、砷、銻及鉍所組成之群組。
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