CN110473781A - 镍硅化物的制造方法 - Google Patents

镍硅化物的制造方法 Download PDF

Info

Publication number
CN110473781A
CN110473781A CN201910742951.9A CN201910742951A CN110473781A CN 110473781 A CN110473781 A CN 110473781A CN 201910742951 A CN201910742951 A CN 201910742951A CN 110473781 A CN110473781 A CN 110473781A
Authority
CN
China
Prior art keywords
nickel silicide
manufacturing
mosfet
nickel
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910742951.9A
Other languages
English (en)
Inventor
李中华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN201910742951.9A priority Critical patent/CN110473781A/zh
Publication of CN110473781A publication Critical patent/CN110473781A/zh
Priority to US16/704,153 priority patent/US11069532B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

本发明公开了一种镍硅化物的制造方法，包括：步骤一、提供半导体衬底，在半导体衬底上具有暴露的硅表面，暴露的硅表面为镍硅化物的形成区域；步骤二、进行预非晶化离子注入并在镍硅化物的形成区域中形成非晶化层，预非晶化离子注入的注入源采用氙；步骤三、在镍硅化物的形成区域自对准形成镍硅化物。本发明利用氙是质量最大的非放射性惰性气体的特点能使非晶化层和硅之间的界面层具有最好的均匀性，从而能提高镍硅化物的欧姆接触电阻均匀性。

Description

镍硅化物的制造方法
技术领域
本发明涉及一种半导体集成电路制造方法，特别是涉及一种镍硅化物的制造方法。
背景技术
在半导体集成电路制造中，通常采用金属硅化物来降低接触电阻，如CMOS器件如NMOS管或PMOS管的源区和漏区以及多晶硅栅和顶部的接触插销的接触通常需要金属硅化物。金属硅化物的形成通常是采用自对准工艺形成，也即首先采用光刻工艺将需要形成金属硅化物的区域打开即将硅暴露出来，其他地方用介质层如氮化层形成的阻挡层覆盖，之后形成金属或金属合金，之后进行退火是形成的金属或金属合金和接触的硅反应并自对准的在金属硅化物的形成区域形成金属硅化物。随着工艺的发展，器件的关键尺寸不断等比例缩小，特别是在65nm以下工艺节点中，普遍采用镍硅化物。
镍硅化物形成通常是先形成镍铂合金，之后再对镍铂合金进行退火，退火过程中，和硅接触的镍铂合金会形成镍硅化物。退火工艺通常采用两步退火，第一次退火使镍铂合金和硅反应形成Ni2Si；第二次退火使Ni2Si转化为NiSi。
超浅结工艺普遍会在镍硅化物生长前进行预非晶化离子注入，预非晶化离子注入会在硅表面形成非晶化层以及在非晶化层和硅之间形成界面层。现有常用的预非晶化离子注入工艺是常温硅或锗离子注入，或者采用低温的硅离子注入。预非晶化离子注入之后会使同一半导体衬底上各区域的硅表面生长的镍硅化物的厚度一致较好即不同区域的厚度较为均匀，如在单晶硅表面、多晶硅表面或锗硅外延层表面生长的镍硅化物的厚度一致性较好。相反，如果不进行预非晶化离子注入，锗硅外延层上生长的镍硅化物的厚度会比单晶硅表面或多晶硅表面生长的镍硅化物薄。
但是随着技术的进步，特别是达到28nm工艺节点以下时，对不同区域的硅表面形成的镍硅化物的均匀性要求越来越高，并希望从而实现镍硅化物形成的欧姆接触电阻的均匀性提高。
发明内容
本发明所要解决的技术问题是提供一种镍硅化物的制造方法，能提高镍硅化物的欧姆接触电阻均匀性。
为解决上述技术问题，本发明提供的镍硅化物的制造方法包括：
步骤一、提供半导体衬底，在所述半导体衬底上具有暴露的硅表面，暴露的硅表面为镍硅化物的形成区域。
步骤二、进行预非晶化离子注入并在所述镍硅化物的形成区域中形成非晶化层，所述预非晶化离子注入的注入源采用氙，利用氙是质量最大的非放射性惰性气体的特点使所述非晶化层和硅之间的界面层具有最好的均匀性。
步骤三、在所述镍硅化物的形成区域自对准形成所述镍硅化物。
进一步的改进是，所述半导体衬底包括硅衬底或SOI衬底。
进一步的改进是，步骤一所提供的所述半导体衬底上形成有MOSFET的源区和漏区，所述镍硅化物的形成区域包括所述MOSFET的源区和漏区。
进一步的改进是，在所述MOSFET的源区或漏区中形成有嵌入式外延层，所述嵌入式外延层为所述MOSFET的沟道区提供有利于增加载流子迁移率的应力。
进一步的改进是，所述MOSFET为PMOS或NMOS。
进一步的改进是，所述MOSFET为PMOS时，所述嵌入式外延层的材料为SiGe。
进一步的改进是，所述MOSFET为NMOS时，所述嵌入式外延层的材料为SiP。
进一步的改进是，所述MOSFET还包括栅极结构，所述栅极结构包括栅介质层和栅极导电材料层。
进一步的改进是，所述栅介质层的材料包括氧化硅、氮氧化硅或高介电常数材料；所述高介电常数材料包括二氧化铪。
进一步的改进是，所述栅极导电材料层为多晶硅栅，步骤一所提供的所述半导体衬底上形成有所述栅极结构，所述镍硅化物的形成区域包括所述多晶硅栅表面。
进一步的改进是，所述栅极导电材料层为金属栅，在步骤一中，在所述栅极结构的形成区域中形成有伪栅极结构，所述伪栅极结构包括依次叠加的所述栅介质层和多晶硅伪栅。
进一步的改进是，所述MOSFET的类型包括平面晶体管和鳍式晶体管。
进一步的改进是，所述预非晶化离子注入的氙源为气体，注入能量为0.5KeV～10KeV，注入剂量为1×1013cm-2～1×1014cm-2，温度为-100℃～25℃，入射角度为0度～30度。
进一步的改进是，步骤三中形成所述镍硅化物的步骤包括：先形成镍铂合金，再对所述镍铂合金进行退火。
在步骤三完成之后，还包括制作层间膜、钨通孔和铜互连的步骤。
进一步的改进是，铜互连工艺完成之后还包括进行所述镍硅化物的欧姆接触电阻进行测试的步骤。
本发明利用形成镍硅化物之前的预非晶化离子注入工艺做了特别的设置，预非晶化离子注入的注入源采用氙，利用氙是质量最大的非放射性惰性气体的特点使非晶化层和硅之间的界面层具有最好的均匀性，也即相对于现有技术中预非晶化离子注入的注入源采用硅或锗的技术方案，本发明中突破了常规思维而第一次采用氙作为预非晶化离子注入的注入源，从而使非晶化层和硅之间的界面层具有最好的均匀性，从而能使形成镍硅化物的均匀性如厚度均匀性也达到最好，这里的均匀性即包括同一掺杂区域如源区、漏区或多晶硅栅中的一个区域镍硅化物的均匀性，也包括不同掺杂区域如源区、漏区或多晶硅栅之前各区域的镍硅化物的均匀性，从而能使镍硅化物的欧姆接触电阻均匀性提高。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明实施例镍硅化物的制造方法的流程图；
图2A-图2C是本发明实施例镍硅化物的制造方法各步骤中的器件结构图。
具体实施方式
如图1所示，是本发明实施例镍硅化物107的制造方法的流程图；如图2A至图2C所示，是本发明实施例镍硅化物107的制造方法各步骤中的器件结构图；本发明实施例镍硅化物107的制造方法包括：
步骤一、如图2A所示，提供半导体衬底101，在所述半导体衬底101上具有暴露的硅表面，暴露的硅表面为镍硅化物107的形成区域。
本发明实施例方法中，所述半导体衬底101为硅衬底。在其他实施例方法中也能为：所述半导体衬底101为SOI衬底。
所提供的所述半导体衬底101上形成有MOSFET的源区和漏区，所述镍硅化物107的形成区域包括所述MOSFET的源区和漏区，从后面描述可知，所述镍硅化物107的形成区域还包括所述多晶硅栅表面。
在所述MOSFET的源区或漏区中形成有嵌入式外延层103，所述嵌入式外延层103为所述MOSFET的沟道区提供有利于增加载流子迁移率的应力。
所述MOSFET为PMOS或NMOS。所述MOSFET为PMOS时，所述嵌入式外延层103的材料为SiGe。所述MOSFET为NMOS时，所述嵌入式外延层103的材料为SiP；也能为：所述MOSFET为NMOS时不采用嵌入式外延层。
所述MOSFET还包括栅极结构，所述栅极结构包括栅介质层和栅极导电材料层。所述栅介质层的材料包括氧化硅、氮氧化硅或高介电常数材料；所述高介电常数材料包括二氧化铪。
所述栅极导电材料层为多晶硅栅。步骤一所提供的所述半导体衬底101上形成有所述栅极结构，所述镍硅化物107的形成区域包括所述多晶硅栅表面。在所述栅极结构的侧面还形成有侧墙105。所述侧墙105通常包括两道侧墙，第一道侧墙形成之后形成轻掺杂漏(LDD)注入；当PMOS和NMOS管集成在一起制造时，能包括步骤：在第一道侧墙形成之后，进行PMOS管的P型LDD即PLDD的注入，之后形成嵌入式SiGe外延层，之后再进行NMOS管的N型LDD即NLDD注入，当NMOS管采用嵌入式外延层时则形成NMOS管的嵌入式外延层，之后再形成第二道侧墙；当NMOS管不采用嵌入式外延层时则在NLDD之后形成第二道侧墙。第二道侧墙形成之后，分别进行PMOS的源漏注入和NMOS的源漏注入。
在其他实施例中，也能为：所述栅极导电材料层为金属栅，在步骤一中，在所述栅极结构的形成区域中形成有伪栅极结构，所述伪栅极结构包括依次叠加的所述栅介质层和多晶硅伪栅。所述多晶硅伪栅会在后续第零层层间膜形成之后去除，并在所述多晶硅伪栅的去除区域形成所述金属栅。
通常，采用形成金属硅化物阻挡层并对所述金属硅化物阻挡层进行图形化的方法将所述镍硅化物107的形成区域打开从而将对应的硅表面暴露。
本发明实施例方法中，所述MOSFET为平面晶体管，即沟道区的沟道仅在一个面上。在其他实施例中也能为：所述MOSFET的类型包括平面晶体管和鳍式晶体管。
步骤二、如图2B所示，进行如标记106所示的预非晶化离子注入并在所述镍硅化物107的形成区域中形成非晶化层，所述预非晶化离子注入的注入源采用氙，利用氙是质量最大的非放射性惰性气体的特点使所述非晶化层和硅之间的界面层具有最好的均匀性，也即本发明实施例采用氙注入源能比现有镍硅化物的制造方法中所采用的任何注入源形成的所述非晶化层和硅之间的界面层的均匀性都好。
所述预非晶化离子注入的氙源为气体，注入能量为0.5KeV～10KeV，注入剂量为1×1013cm-2～1×1014cm-2，温度为-100℃～25℃，入射角度为0度～30度。和常温相比，所述预非晶化离子注入的温度比常温低的低温，通过降低所述预非晶化离子注入的温度，能进一步提高所述非晶化层和硅之间的界面层的均匀性。
步骤三、如图2C所示，在所述镍硅化物107的形成区域自对准形成所述镍硅化物107。
形成所述镍硅化物107的步骤包括：先形成镍铂合金，再对所述镍铂合金进行退火，通常包括两步退火。第一次退火使镍铂合金和硅反应形成Ni2Si；第二次退火使Ni2Si转化为NiSi。
在步骤三完成之后，还包括制作层间膜、钨通孔和铜互连的步骤。
铜互连工艺完成之后还包括进行所述镍硅化物107的欧姆接触电阻进行测试的步骤。
本发明实施例利用形成镍硅化物107之前的预非晶化离子注入工艺做了特别的设置，预非晶化离子注入的注入源采用氙，利用氙是质量最大的非放射性惰性气体的特点使非晶化层和硅之间的界面层具有最好的均匀性，也即相对于现有技术中预非晶化离子注入的注入源采用硅或锗的技术方案，本发明实施例中突破了常规思维而第一次采用氙作为预非晶化离子注入的注入源，从而使非晶化层和硅之间的界面层具有最好的均匀性，从而能使形成镍硅化物107的均匀性如厚度均匀性也达到最好，这里的均匀性即包括同一掺杂区域如源区、漏区或多晶硅栅中的一个区域镍硅化物107的均匀性，也包括不同掺杂区域如源区、漏区或多晶硅栅之前各区域的镍硅化物107的均匀性，从而能使镍硅化物107的欧姆接触电阻均匀性提高。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (15)

1.一种镍硅化物的制造方法，其特征在于，包括：
步骤一、提供半导体衬底，在所述半导体衬底上具有暴露的硅表面，暴露的硅表面为镍硅化物的形成区域；
步骤二、进行预非晶化离子注入并在所述镍硅化物的形成区域中形成非晶化层，所述预非晶化离子注入的注入源采用氙，利用氙是质量最大的非放射性惰性气体的特点使所述非晶化层和硅之间的界面层具有最好的均匀性；
步骤三、在所述镍硅化物的形成区域自对准形成所述镍硅化物。
2.如权利要求1所述的镍硅化物的制造方法，其特征在于：所述半导体衬底包括硅衬底或SOI衬底。
3.如权利要求2所述的镍硅化物的制造方法，其特征在于：步骤一所提供的所述半导体衬底上形成有MOSFET的源区和漏区，所述镍硅化物的形成区域包括所述MOSFET的源区和漏区。
4.如权利要求3所述的镍硅化物的制造方法，其特征在于：在所述MOSFET的源区或漏区中形成有嵌入式外延层，所述嵌入式外延层为所述MOSFET的沟道区提供有利于增加载流子迁移率的应力。
5.如权利要求4所述的镍硅化物的制造方法，其特征在于：所述MOSFET为PMOS或NMOS。
6.如权利要求5所述的镍硅化物的制造方法，其特征在于：所述MOSFET为PMOS时，所述嵌入式外延层的材料为SiGe。
7.如权利要求5所述的镍硅化物的制造方法，其特征在于：所述MOSFET为NMOS时，所述嵌入式外延层的材料为SiP。
8.如权利要求3所述的镍硅化物的制造方法，其特征在于：所述MOSFET还包括栅极结构，所述栅极结构包括栅介质层和栅极导电材料层。
9.如权利要求8所述的镍硅化物的制造方法，其特征在于：所述栅介质层的材料包括氧化硅、氮氧化硅或高介电常数材料；所述高介电常数材料包括二氧化铪。
10.如权利要求8所述的镍硅化物的制造方法，其特征在于：所述栅极导电材料层为多晶硅栅，步骤一所提供的所述半导体衬底上形成有所述栅极结构，所述镍硅化物的形成区域包括所述多晶硅栅表面。
11.如权利要求8所述的镍硅化物的制造方法，其特征在于：所述栅极导电材料层为金属栅，在步骤一中，在所述栅极结构的形成区域中形成有伪栅极结构，所述伪栅极结构包括依次叠加的所述栅介质层和多晶硅伪栅。
12.如权利要求3所述的镍硅化物的制造方法，其特征在于：所述MOSFET的类型包括平面晶体管和鳍式晶体管。
13.如权利要求1所述的镍硅化物的制造方法，其特征在于：所述预非晶化离子注入的氙源为气体，注入能量为0.5KeV～10KeV，注入剂量为1×1013cm-2～1×1014cm-2，温度为-100℃～25℃，入射角度为0度～30度。
14.如权利要求1所述的镍硅化物的制造方法，其特征在于：步骤三中形成所述镍硅化物的步骤包括：先形成镍铂合金，再对所述镍铂合金进行退火；
在步骤三完成之后，还包括制作层间膜、钨通孔和铜互连的步骤。
15.如权利要求14所述的镍硅化物的制造方法，其特征在于：铜互连工艺完成之后还包括进行所述镍硅化物的欧姆接触电阻进行测试的步骤。
CN201910742951.9A 2019-08-13 2019-08-13 镍硅化物的制造方法 Pending CN110473781A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910742951.9A CN110473781A (zh) 2019-08-13 2019-08-13 镍硅化物的制造方法
US16/704,153 US11069532B2 (en) 2019-08-13 2019-12-05 Method for manufacturing nickel silicide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910742951.9A CN110473781A (zh) 2019-08-13 2019-08-13 镍硅化物的制造方法

Publications (1)

Publication Number Publication Date
CN110473781A true CN110473781A (zh) 2019-11-19

Family

ID=68510643

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910742951.9A Pending CN110473781A (zh) 2019-08-13 2019-08-13 镍硅化物的制造方法

Country Status (2)

Country Link
US (1) US11069532B2 (zh)
CN (1) CN110473781A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2734095C1 (ru) * 2020-05-02 2020-10-12 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления силицида никеля
CN113838747A (zh) * 2020-06-23 2021-12-24 上海先进半导体制造有限公司 带外延层的半导体器件及其制作方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689687B1 (en) * 2001-02-02 2004-02-10 Advanced Micro Devices, Inc. Two-step process for nickel deposition
US20040087121A1 (en) * 2002-10-30 2004-05-06 Thorsten Kammler Method of forming a nickel silicide region in a doped silicon-containing semiconductor area
US20050090067A1 (en) * 2003-10-27 2005-04-28 Dharmesh Jawarani Silicide formation for a semiconductor device
CN1649112A (zh) * 2003-11-17 2005-08-03 三星电子株式会社 镍－自对准硅化物工艺和利用该工艺制造半导体器件的方法
CN101150070A (zh) * 2006-09-19 2008-03-26 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN101996872A (zh) * 2009-08-14 2011-03-30 台湾积体电路制造股份有限公司 集成电路的形成方法
CN102468172A (zh) * 2010-11-12 2012-05-23 中芯国际集成电路制造(上海)有限公司 半导体器件制造方法
CN102714159A (zh) * 2010-01-08 2012-10-03 国际商业机器公司 具有不同铂成分的硅化镍的形成方法
CN103972060A (zh) * 2013-01-28 2014-08-06 台湾积体电路制造股份有限公司 超浅结的制造
CN103972102A (zh) * 2014-04-22 2014-08-06 上海华力微电子有限公司 超浅结的形成方法及半导体器件的形成方法
US20140227843A1 (en) * 2013-02-12 2014-08-14 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US20180301559A1 (en) * 2017-04-18 2018-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080057685A1 (en) * 2006-07-31 2008-03-06 Interuniversitair Microelektronica Centrum (Imec) Vzw Method for forming doped metal-semiconductor compound regions
US7820492B2 (en) * 2007-05-25 2010-10-26 Kabushiki Kaisha Toshiba Electrical fuse with metal silicide pipe under gate electrode
US9881872B2 (en) * 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a local interconnect in a semiconductor device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689687B1 (en) * 2001-02-02 2004-02-10 Advanced Micro Devices, Inc. Two-step process for nickel deposition
US20040087121A1 (en) * 2002-10-30 2004-05-06 Thorsten Kammler Method of forming a nickel silicide region in a doped silicon-containing semiconductor area
US20050090067A1 (en) * 2003-10-27 2005-04-28 Dharmesh Jawarani Silicide formation for a semiconductor device
CN1649112A (zh) * 2003-11-17 2005-08-03 三星电子株式会社 镍－自对准硅化物工艺和利用该工艺制造半导体器件的方法
CN101150070A (zh) * 2006-09-19 2008-03-26 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN101996872A (zh) * 2009-08-14 2011-03-30 台湾积体电路制造股份有限公司 集成电路的形成方法
CN102714159A (zh) * 2010-01-08 2012-10-03 国际商业机器公司 具有不同铂成分的硅化镍的形成方法
CN102468172A (zh) * 2010-11-12 2012-05-23 中芯国际集成电路制造(上海)有限公司 半导体器件制造方法
CN103972060A (zh) * 2013-01-28 2014-08-06 台湾积体电路制造股份有限公司 超浅结的制造
US20140227843A1 (en) * 2013-02-12 2014-08-14 Renesas Electronics Corporation Method of manufacturing a semiconductor device
CN103972102A (zh) * 2014-04-22 2014-08-06 上海华力微电子有限公司 超浅结的形成方法及半导体器件的形成方法
US20180301559A1 (en) * 2017-04-18 2018-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2734095C1 (ru) * 2020-05-02 2020-10-12 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления силицида никеля
CN113838747A (zh) * 2020-06-23 2021-12-24 上海先进半导体制造有限公司 带外延层的半导体器件及其制作方法

Also Published As

Publication number Publication date
US11069532B2 (en) 2021-07-20
US20210050217A1 (en) 2021-02-18

Similar Documents

Publication Publication Date Title
JP4493536B2 (ja) 半導体装置及びその製造方法
CN1307709C (zh) 具有硅锗栅极的半导体器件及其制作方法
US7511350B2 (en) Nickel alloy silicide including indium and a method of manufacture therefor
US5432129A (en) Method of forming low resistance contacts at the junction between regions having different conductivity types
US20090203177A1 (en) Thin-film semiconductor device and method for manufacturing the same
US20120112292A1 (en) Intermixed silicide for reduction of external resistance in integrated circuit devices
CN110473781A (zh) 镍硅化物的制造方法
US20090079010A1 (en) Nickel silicide formation for semiconductor components
US9231079B1 (en) Stress memorization techniques for transistor devices
KR100574172B1 (ko) 반도체 소자의 제조방법
US8470703B2 (en) Semiconductor device and method of fabricating the same
JP2006508548A (ja) ドープされたｈｉｇｈ−ｋサイドウォールスペーサを有す電界効果トランジスタのドレイン／ソース拡張構造
CN101393931A (zh) 半导体器件及其制造方法
US9741853B2 (en) Stress memorization techniques for transistor devices
US20050112830A1 (en) Ultra shallow junction formation
US20040115889A1 (en) Ultra shallow junction formation
KR100835424B1 (ko) 모스 트랜지스터 제조 방법
KR100678318B1 (ko) 풀리실리사이드 게이트 형성 방법
JP3744895B2 (ja) Ｃｍｏｓ型半導体装置の製造方法
US20080057685A1 (en) Method for forming doped metal-semiconductor compound regions
US20030124807A1 (en) Versatile system for forming uniform wafer surfaces
US20150004767A1 (en) Method of forming nickel salicide on a silicon-germanium layer
KR0172250B1 (ko) 반도체 소자의 트랜지스터 제조방법
KR100204015B1 (ko) 모스트랜지스터 제조방법
JPH1116855A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20191119