TWI503885B - Etching method and etching treatment device - Google Patents
Etching method and etching treatment device Download PDFInfo
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- TWI503885B TWI503885B TW099145407A TW99145407A TWI503885B TW I503885 B TWI503885 B TW I503885B TW 099145407 A TW099145407 A TW 099145407A TW 99145407 A TW99145407 A TW 99145407A TW I503885 B TWI503885 B TW I503885B
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- 238000005530 etching Methods 0.000 title claims description 116
- 238000000034 method Methods 0.000 title claims description 51
- 239000007789 gas Substances 0.000 claims description 194
- 238000012545 processing Methods 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 230000001629 suppression Effects 0.000 claims 3
- QGJOPFRUJISHPQ-UHFFFAOYSA-N Carbon disulfide Chemical compound S=C=S QGJOPFRUJISHPQ-UHFFFAOYSA-N 0.000 description 66
- 230000008021 deposition Effects 0.000 description 11
- 239000010410 layer Substances 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005764 inhibitory process Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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Description
本發明係關於一種蝕刻方法以及蝕刻處理裝置。尤其係關於一種以阻膜(resist film)圖案作為罩體來進行蝕刻之技術。
半導體製程中之形成所需圖案之罩體製程,係對蝕刻對象膜上塗佈感光膜之後,藉由曝光以及顯影來進行圖案化。此時,為了防止曝光中之反射,係於蝕刻對象膜之上、感光膜之下形成有抗反射膜ARC(Anti Reflection Coating Layer)。抗反射膜包括有機抗反射膜、無機抗反射膜。例如於專利文獻1、2當中揭示了一種方法,一邊以有機抗反射膜來抑制反射,並利用所需蝕刻氣體而於抗反射膜形成圖案。
但是,終究有機抗反射膜與無機抗反射膜在膜質上不同。因此,適當的蝕刻氣體也不同。因而,即使將上述專利文獻1、2所揭示之有機抗反射膜的蝕刻氣體轉用於無機抗反射膜之蝕刻上也難以實現良好的蝕刻。
習知技術文獻
專利文獻1 日本特開2009-152586號公報
專利文獻2 國際公開WO98/32162號小冊
於無機抗反射膜當中,尤其是含矽無機抗反射膜(以下,也稱為Si-ARC膜),以往,係以ArF阻膜為罩體,以四氟甲烷(CF4
)氣體與氧(O2
)氣體之混合氣體作為蝕刻氣體來蝕刻Si-ARC膜。但是,此混合氣體所進行之蝕刻所存在的問題在於:ArF阻膜與Si-ARC膜之選擇比並非良好,ArF阻膜之減少量高,對後續製程產生障礙。此外,尚發生於圖案之線寬發生差異、圖案變形之LWR(Line Width Roughness),或是圖案之邊緣變形之LER(Line Edge Roughness)的問題。
針對上述課題,本發明之目的在於提供一種蝕刻方法以及蝕刻處理裝置,其適合於以阻膜為罩體之抗反射膜的蝕刻上。
為了解決上述課題,依據本發明之某觀點,係提供一種蝕刻方法,包含下述製程:於被蝕刻層上形成抗反射膜之製程;於該抗反射膜上形成經圖案化阻膜之製程;以及,以該阻膜為罩體,將含有CF4
氣體與COS氣體與O2
氣體之蝕刻氣體導入處理室內,使用所導入之蝕刻氣體來蝕刻該抗反射膜,藉以於該抗反射膜形成所需圖案之製程。
藉此,抗反射膜係以阻膜為罩體,使用含有CF4
氣體與COS氣體與O2
氣體之蝕刻氣體進行蝕刻。於CF4
氣體與COS氣體與O2
氣體之混合氣體當中,CF4氣體主要係使用於抗反射膜之蝕刻上,COS氣體主要係使用於該蝕刻面之包覆(沉積)上,O2
氣體主要係使用於COS氣體之包覆(沉積)之降低上。依據以上構成,一邊以CF4
氣體與COS氣體與O2
氣體當中之CF4
氣體來蝕刻抗反射膜,一邊在COS氣體所致包覆與O2
氣體所致前述包覆之抑制間取得平衡,可謀求阻膜以及抗反射膜間之選擇比的提高、以及抗反射膜之LWR之改善。
前述阻膜亦可為ArF阻膜。
前述抗反射膜亦可含有矽。
前述蝕刻氣體所含COS氣體之流量上限可為50sccm。
前述蝕刻氣體所含CF4
氣體之流量可在50~300sccm之範圍內。
前述蝕刻氣體所含O2
氣體之流量上限可為100sccm。
前述蝕刻氣體所含COS氣體之流量以及O2
氣體之流量亦可成正比控制。
前述處理室內之壓力可在30~100mT之範圍內。
再者,前述處理室內之壓力上限以75mT為更佳。
此外,為了解決上述課題,依據本發明之另一觀點,係提供一種蝕刻處理裝置,具備有:氣體供給源,係將含有CF4
氣體與COS氣體與O2
氣體之蝕刻氣體供給至處理室;以及高頻電源,係對該處理室供給所需高頻電力;另外,使用高頻電力而由該蝕刻氣體生成電漿,藉由該電漿對於形成有抗反射膜以及經圖案化阻膜之被處理體施行蝕刻處理,以於該抗反射膜形成所需圖案。
如以上說明般,依據本發明,能以適合於以阻膜為罩體之抗反射膜之蝕刻上的蝕刻方法,來謀求阻膜以及抗反射膜間之選擇比的提高以及抗反射膜之LWR的改善。
以下參照所附圖式,針對本發明之實施形態做詳細說明。此外,於本說明書以及圖式中,針對實質上具有同一機能構成之構成要素係賦予同一符號而省略重複說明。
本發明之一實施形態之蝕刻方法係適合於以ArF阻膜為罩體之Si-ARC膜的蝕刻上。圖1係用以說明本實施形態之Si-ARC膜之蝕刻方法的積層膜截面圖。
如圖1之上側圖所示般,於作為被蝕刻層之有機膜10上形成有Si-ARC膜(含矽無機反射膜)。Si-ARC膜12乃感光膜之曝光製程時用以防止反射之物。有機膜10為被蝕刻層之一例,被蝕刻層不限於此,亦可為例如絕緣膜或是導電膜。被蝕刻層亦可為矽基板。
於Si-ARC膜12上形成有ArF阻膜14。ArF阻膜14係於Si-ARC膜12上使用ArF光微影而形成者。具體而言,於Si-ARC膜12上塗佈感光劑,通過刻印有欲印刷圖案之被稱為罩體的遮光材,照射波長193nm之ArF雷射光線進行曝光。於曝光後,對感光部分進行化學性腐蝕(蝕刻),於ArF阻膜14形成所需圖案。以此方式,使用以ArF雷射作為曝光光源之ArF光微影來朝向短波長化,達成電路之微細化。
此外,ArF阻膜14係用以於Si-ARC膜形成圖案之阻膜的一例,阻膜不侷限於此。阻膜亦可使用g線(436nm)、i線(365nm)、KrF(248nm)來形成。
圖1之下側圖係顯示蝕刻製程。本製程係以由四氟甲烷(CF4
)氣體、硫化碳醯(COS)氣體與氧(O2
)氣體所構成之混合氣體作為蝕刻氣體來蝕刻Si-ARC膜12。ArF阻膜14發揮罩體之功用。蝕刻的結果,於Si-ARC膜12形成所需圖案。
(LWR/選擇比)
發明者以實驗證明了使用由CF4
氣體、COS氣體以及O2
氣體所構成之混合氣體,可提高Si-ARC膜12之LWR(Line Width Roughness)以及ArF阻膜14與Si-ARC膜12之間的選擇比。
此時,在蝕刻處理裝置方面係使用圖2所示平行平板型電漿處理裝置。關於該裝置構成簡單說明之。
蝕刻處理裝置100具有處理室105。處理室105係由例如鋁等金屬所形成並接地。於處理室105內部,有上部電極110與下部電極115對向配置著,藉此構成一對的平行平板電極。於上部電極110貫通有複數氣體孔Op而同時發揮淋灑板之作用。亦即,從氣體供給源120所供給之CF4
氣體與COS氣體與O2
氣體在處理室內之氣體擴散空間S擴散之後,從複數氣體孔Op導入處理室內。
下部電極115係受到支持台125所支持著。於下部電極115之載置台表面係載置著晶圓W。於下部電極115(載置台)內部埋設有加熱器115a以及未圖示之冷卻管,可將晶圓W調整至既定溫度。下部電極115係經由未圖示之整合器而與高頻電源130連接著。被導入處理室內之CF4
氣體與COS氣體與O2
氣體之混合氣體係被高頻電源130所輸出之高頻電場能量所激發,藉此在上部電極110與下部電極115之間的電漿空間生成放電型電漿。利用以此方式所生成之電漿而在晶圓W上施行圖1之蝕刻處理。
於處理室105底面設有排氣口135,藉由驅動連接於排氣口135之排氣裝置140,將處理室105內部保持在所需真空狀態。
於相關構成之蝕刻處理裝置100中來蝕刻含矽之Si-ARC膜12。可作為程序條件使用之範圍表示於圖3。具體而言,處理室105之壓力落於30~100mT之範圍內,建議值為50mT。
關於從氣體供給源120所供給之各氣體流量,COS氣體在50sccm以下之範圍內,建議值為30sccm。CF4
氣體在50~300sccm之範圍內,建議值為250sccm。O2
氣體在100sccm以下之範圍內,建議值為5sccm。
從高頻電源130所輸出之電力在200~600W之範圍內,建議值為400W。載置台內部之加熱器115a在10~60℃之範圍內,建議值為30℃。
以下,一開始先考察COS氣體之流量為可變時進行蝕刻處理後之實驗結果與該時之蝕刻狀態,其次考察COS氣體之流量與壓力兩者為可變時進行蝕刻處理後之實驗結果與該時之蝕刻狀態。
<COS氣體之流量控制>
首先,針對COS氣體之流量控制與蝕刻狀態的關係,參照圖4以及圖5來說明。針對此時之程序條件描述。蝕刻對象為Si-ARC膜,以ArF阻膜發揮罩體之作用。處理室內之壓力為50mT,高頻電力為400W,CF4氣體、COS氣體、O2
氣體之流量分別為250sccm、0~35sccm(可變)、5sccm。蝕刻時間為過度蝕刻時間之30%的時間,實際乃圖4所示蝕刻時間。此外,當COS氣體為40sccm以上,由於COS氣體所造成之堆積物變得過多,故並未測量。
對上部電極110並未施加直流電壓DCS。於下部電極115所設之未圖示冷卻管內的壓力在中心側以及邊緣側皆為30T。處理室105之溫度在上部電極110以及處理室側面皆為60℃,晶圓W之載置下部為30℃。
經以上程序條件實驗之結果表示於圖4以及圖5。圖4最左上端之圖像係與圖1之上側圖為相同截面狀態,從上而下表示經圖案化之ArF阻膜14、初期狀態之未經蝕刻之Si-ARC膜12、底膜。圖4最左下端之圖像係從上方觀看上部截面圖之圖,顯示著初期狀態之阻劑圖案之線寬(CD:Critical Dimension)。
於此實驗中,係將COS氣體之流量以0、10、30、35sccm來變化。實驗結果,如圖4以及圖5(a)所示般,可知COS氣體之流量愈多則蝕刻速率E/R(ArF阻膜之蝕刻速率(PR E/R)、Si-ARC膜之蝕刻速率(Si-ARC E/R))愈為降低。
此外,如圖4以及圖5(b)所示般,COS氣體之流量愈多則選擇比愈為提高。尤其,當COS氣體之流量從30sccm變化為35sccm之際,選擇比顯著地提高了。
此外,如圖4以及圖5(c)所示般,COS氣體之流量愈多則LWR(Line Width Roughness)愈為降低,不易於線寬出現差異,圖案形狀少有變形發生。一般認為此乃由於COS氣體所致包覆(coating)之故。
此外,如圖4以及圖5(d)所示般,COS氣體之流量愈多則圖案線寬(CD)變得愈粗。此被認為乃由於COS氣體所致沉積之故。
由以上結果可知,由CF4
氣體與COS氣體與O2
氣體所構成之混合氣體當中之CF4
氣體主要被使用於Si-ARC膜12之蝕刻上。
此外,由於COS氣體之流量愈多則蝕刻速率(E/R:阻膜之蝕刻速率(PR E/R)與Si-ARC膜之蝕刻速率(Si-ARC E/R))變得愈差,故一般認為COS氣體主要係使用於該蝕刻面之包覆(沉積)上。是以,被認為當COS氣體之流量愈多則ArF阻膜之減少量變少,可得到ArF阻膜與Si-ARC膜之選擇比良好之結果。
再者,O2
氣體被認為主要係使用於COS氣體之包覆(沉積)的降低上。
從以上實驗結果,證明了藉由以ArF阻膜14為罩體,並使用由CF4
氣體與COS氣體與O2
氣體所構成之蝕刻氣體來蝕刻Si-ARC膜12,可謀求ArF阻膜14與Si-ARC膜12之間的選擇比之提高以及Si-ARC膜12之LWR的改善。
<COS氣體之流量控制以及壓力控制>
其次,針對COS氣體之流量控制以及壓力控制與蝕刻狀態之關係,參照圖6以及圖7來說明。若針對此時之程序條件來說明,則於處理製程,處理室內之壓力為100mT,高頻電力為200W,對處理室內導入H2
氣體以及N2
氣體,其流量皆為450sccm,處理時間為120秒,並未對上部電極110施加直流電壓DCS。
在處理製程後之蝕刻製程,蝕刻對象為Si-ARC膜,ArF阻膜作為罩體來作用。在此實驗中,係將COS氣體之流量以0、10、30sccm來變化,並使得處理室內之壓力以30、50、75mT來變化。
高頻電力為400W,CF4
氣體、COS氣體、O2
氣體之流量分別為250sccm、0~35sccm、5sccm。蝕刻時間為過度蝕刻時間之30%的時間。於下部電極115所設之未圖示之冷卻管內部的壓力在中心側以及邊緣側皆為30T。處理室105之溫度在上部電極110以及處理室側面皆為60℃,晶圓W之載置下部為30℃。
以以上程序條件實驗之結果係表示於圖6以及圖7。圖6之大致左半邊的圖像係表示當COS氣體之流量為10sccm之情況下之蝕刻狀態,圖6之大致右半邊的圖像係表示當COS氣體之流量為30sccm之情況下之蝕刻狀態。
依據此實驗,如圖6所示般,可知COS之流量不論在何種情況下,壓力愈低則蝕刻速率(E/R)愈為上昇。若壓力高則堆積物變多,在圖6之結果,一旦處理室內之壓力成為75mT則COS之堆積物變得過多而無法進行蝕刻製程。
此外,如圖6以及圖7(a)所示般,當COS氣體之流量高於0之情況(COS氣體為10sccm或是30sccm之情況),則處理室內之壓力愈高,選擇比愈為提高。
此外,如圖6以及圖7(b)所示般,尤其當COS氣體為30sccm、壓力為50mT之時,LWR成為最佳狀態。
此外,如圖6以及圖7(c)所示般,COS氣體之流量愈多則圖案線寬(CD)變得愈粗。一般認為此乃由於COS氣體所致沉積之故。
從以上的結果,一般認為由CF4
氣體與COS氣體與O2
氣體所構成之混合氣體當中之CF4
氣體主要被使用於Si-ARC膜12之蝕刻,COS氣體主要被使用於圖案之蝕刻面的包覆,O2
氣體主要被使用於COS氣體所致沉積的抑制。此時,可知尤其處理室內之壓力愈低則蝕刻速率(E/R)愈高,處理室內之壓力愈高則COS氣體所致沉積愈多。
此外,可知當COS氣體之流量愈多、壓力愈低則蝕刻速率E/R(阻膜之蝕刻速率(PR E/R)、Si-ARC膜之蝕刻速率(Si-ARC E/R))愈為良好。
由以上實驗結果,可知在選擇比之提高以及LWR之改善上,雖可使用含有CF4
氣體與COS氣體與O2
氣體之蝕刻氣體,惟一旦COS氣體達到既定流量以上,會因為附著性高之COS的沉積而造成蝕刻停止(etch stop)。是以,基於防止沉積而實現良好的蝕刻製程之觀點,參照圖6之結果,處理室內之壓力以75mT為上限。
此外,基於前述般COS氣體主要係使用於圖案之蝕刻面的包覆,而O2
氣體主要係使用於COS氣體所致沉積之抑制的性質上,以COS氣體之流量與O2
氣體之流量的流量比成為大致一定的方式進行控制為佳。
以上,參照所附圖式對本發明之較佳實施形態作了詳細說明,惟本發明不限定於相關之例。只要是本發明所屬技術領域具有通常知識者,顯然地可於申請專利範圍所記載之技術思想的範疇內思及各種變更例或是修正例,這些當然也屬於本發明之技術範圍。
例如,本發明之阻膜不限於ArF阻膜,亦可為其他阻膜。此外,本發明之抗反射膜不限於Si-ARC膜,亦可為不含矽之無機抗反射膜,或是亦可為有機抗反射膜。無機抗反射膜主要係由F系氣體所蝕刻,而有機抗反射膜主要係由氧系氣體所蝕刻。
本發明之蝕刻氣體可僅為CF4
氣體與COS氣體與O2
氣體之混合氣體,亦可為於CF4
氣體與COS氣體與O2
氣體之混合氣體中加入惰性氣體而成之混合氣體。
本發明之蝕刻處理裝置只要是電漿處理裝置則不限於平行平板型電漿處理裝置,亦可為ICP(Inductively Coupled Plasma)電漿處理裝置等電漿處理裝置。
10...有機膜
12...Si-ARC
14...ArF阻膜
100...蝕刻處理裝置
105...處理室
110...上部電極
115...下部電極
120...氣體供給源
130...高頻電源
圖1係本發明之一實施形態之Si-ARC膜的蝕刻製程圖。
圖2係實行同實施形態之蝕刻製程的電漿處理裝置截面圖。
圖3係表示同實施形態之蝕刻製程中之程序條件表。
圖4係表示同實施形態之蝕刻製程中,當控制了COS流量之情況下罩體之殘存狀態圖。
圖5(a)~(d)係表示同實施形態之蝕刻製程中COS流量控制與蝕刻速率、選擇比等之關係圖。
圖6係表示於同實施形態之蝕刻製程中,當控制了COS流量以及壓力之情況下之罩體殘存狀態之圖。
圖7(a)~(c)係表示同實施形態之蝕刻製程中,COS流量控制以及壓力控制與選擇比、LWR等之關係圖。
10...有機膜
12...Si-ARC
14...ArF阻膜
Claims (16)
- 一種蝕刻方法,包含下述製程:於被蝕刻層上形成抗反射膜之製程;於該抗反射膜上形成經圖案化阻膜之製程;以及以該阻膜為罩體,將含有CF4 氣體與COS氣體與O2 氣體之蝕刻氣體導入處理室內,使用所導入之蝕刻氣體來蝕刻該抗反射膜,藉以於該抗反射膜形成所需圖案之製程;該COS氣體係使用於該抗反射膜的蝕刻面之包覆上,該O2 氣體係使用於該COS氣體之該包覆的抑制上。
- 如申請專利範圍第1項之蝕刻方法,其中該阻膜為ArF阻膜。
- 如申請專利範圍第1項之蝕刻方法,其中該抗反射膜含有矽。
- 如申請專利範圍第1至3項中任一項之蝕刻方法,其中該蝕刻氣體所含COS氣體之流量上限為50sccm。
- 如申請專利範圍第1至3項中任一項之蝕刻方法,其中該蝕刻氣體所含CF4 氣體之流量在50~300sccm之範圍內。
- 如申請專利範圍第1至3項中任一項之蝕刻方法,其中該蝕刻氣體所含O2 氣體之流量上限為100sccm。
- 如申請專利範圍第1至3項中任一項之蝕刻方法,其中該蝕刻氣體所含COS氣體之流量以及O2 氣體之流 量係以正比方式控制。
- 如申請專利範圍第1至3項中任一項之蝕刻方法,其中該處理室內之壓力在30~100mT之範圍內。
- 如申請專利範圍第8項之蝕刻方法,其中該處理室內之壓力上限為75mT。
- 一種蝕刻處理裝置,具備有:氣體供給源,係將含有CF4 氣體與COS氣體與O2 氣體之蝕刻氣體供給至處理室;以及高頻電源,係對該處理室供給所需高頻電力;使用高頻電力而由該蝕刻氣體生成電漿,藉由該電漿對於形成有抗反射膜以及經圖案化阻膜之被處理體施行蝕刻處理,以於該抗反射膜形成所需圖案;該COS氣體係使用於該抗反射膜的蝕刻面之包覆上,該O2 氣體係使用於該COS氣體之該包覆的抑制上。
- 一種蝕刻方法,係依序形成有抗反射膜、經圖案化阻膜,而在處理室內將該阻膜作為罩體來蝕刻該抗反射膜;具備有:將CF4 氣體與COS氣體與O2 氣體之蝕刻氣體導入處理室內之製程;生成該CF4 氣體與該COS氣體與該O2 氣體之蝕刻氣體電漿之製程;藉由該CF4 氣體與該COS氣體與該O2 氣體之蝕刻氣體電漿,並以該阻膜為罩體來蝕刻該抗反射膜,藉以於該抗反射膜形成所需圖案之製程。
- 如申請專利範圍第11項之蝕刻方法,其中該蝕刻氣體包含有非活性氣體。
- 如申請專利範圍第12項之蝕刻方法,其中該COS氣體之流量係10~35sccm。
- 如申請專利範圍第13項之蝕刻方法,其中該處理室內之壓力係30~100mT的範圍內。
- 如申請專利範圍第11或12項之蝕刻方法,其中該COS氣體之流量與該O2 氣體之流量的流量比係控制為幾乎成定值。
- 如申請專利範圍第11之蝕刻方法,其中該COS氣體係使用於該抗反射膜的蝕刻面之包覆上,該O2 氣體係使用於該COS氣體之該包覆的抑制上。
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US8394722B2 (en) * | 2008-11-03 | 2013-03-12 | Lam Research Corporation | Bi-layer, tri-layer mask CD control |
US8986561B2 (en) * | 2008-12-26 | 2015-03-24 | Tokyo Electron Limited | Substrate processing method and storage medium |
US20110079918A1 (en) * | 2009-10-01 | 2011-04-07 | Applied Materials, Inc. | Plasma-based organic mask removal with silicon fluoride |
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2009
- 2009-12-24 JP JP2009293094A patent/JP5606060B2/ja not_active Expired - Fee Related
-
2010
- 2010-12-21 KR KR1020100131305A patent/KR101810970B1/ko active IP Right Grant
- 2010-12-23 TW TW099145407A patent/TWI503885B/zh active
- 2010-12-23 US US12/977,266 patent/US8283254B2/en active Active
- 2010-12-24 CN CN2010106218007A patent/CN102129983B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090087996A1 (en) * | 2007-09-27 | 2009-04-02 | Lam Research Corporation | Line width roughness control with arc layer open |
US20090212010A1 (en) * | 2008-02-21 | 2009-08-27 | Judy Wang | Plasma etching carbonaceous layers with sulfur-based etchants |
Also Published As
Publication number | Publication date |
---|---|
TW201137971A (en) | 2011-11-01 |
KR101810970B1 (ko) | 2017-12-20 |
US20110159697A1 (en) | 2011-06-30 |
CN102129983A (zh) | 2011-07-20 |
KR20110074455A (ko) | 2011-06-30 |
JP2011134896A (ja) | 2011-07-07 |
CN102129983B (zh) | 2012-11-21 |
US8283254B2 (en) | 2012-10-09 |
JP5606060B2 (ja) | 2014-10-15 |
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