TWI501393B - 半導體元件 - Google Patents

半導體元件 Download PDF

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TWI501393B
TWI501393B TW103116948A TW103116948A TWI501393B TW I501393 B TWI501393 B TW I501393B TW 103116948 A TW103116948 A TW 103116948A TW 103116948 A TW103116948 A TW 103116948A TW I501393 B TWI501393 B TW I501393B
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semiconductor
electrode
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Yoshio Takahara
Takeshi Miura
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Mitsubishi Electric Corp
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors

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Description

半導體元件
本發明係關於半導體元件。
習知的高頻電力放大器中使用的異質接面型雙極電晶體(以下為HBT),一般構成如第5圖。第5圖,係顯示具有用以說明本發明課題的典型的HBT構造之半導體元件圖。第5圖所示的HBT,包括N型半導體形成的射極層111、射極電極112、基極電極113、高濃度P型半導體形成的基極層114、N型半導體形成的集極層115、高濃度N型半導體形成的歐姆集極層116以及集極電極117。
此HBT中,P型基極層114與N型集極層115之間,形成基極集極接面部118。為了降低接面電容(Cbc)的電容,提高高頻特性(最大振盪頻率fmax等),最好此基極集極接面部118儘可能小。因此,可以極力降低位於基極電極113的外側的PN接面端部119。
考慮以溼蝕刻或乾蝕刻進行基極層的蝕刻。利用溼蝕刻的情況下,考慮使用酒石酸過氧化氫或磷酸過氧化氫,進行此基極層加工時,必須注意基極電極一定要避開被蝕刻區域。因此,某程度離開基極電極的位置上必須形成蝕刻端,具體而言,根據蝕刻時使用的光阻的尺寸控制性及與基極電極的 配合精確課題,必須進行設置0.5μm(微米)以上的間隔的設計。因此,PN接面端部119在基極電極113正下方設置蝕刻端,事實上不可能。
又,利用乾蝕刻的情況下,也有基極電極作為光罩以自我對準(Self-Aligned)乾蝕刻加工基極層,得到最小面積的基極集極接面面積的方法。不過,基極電極材料一般使用Au(金),此時在光罩中蝕刻Au。於是,因為產生乾蝕刻裝置的Au污染問題,或是蝕刻時裝置本身受Au污染等的問題,乾蝕刻不是可以大量生產的製程,大量生產現場以上述溼蝕刻為主流。
又,第5圖所示的HBT構造中,如同端部1110地,基極集極接面露出加工基極層的端部表面。因此,表面準位不穩定,基極集極間的漏電流有不穩定的問題。
關於這點,例如日本專利昭和60年第164358號公開公報所揭示,具有進行非活化的技術,係在基極電極外側形成的基極集極半導體層中,以基極電極作為光罩執行離子注入。
[先行技術文件] [專利文件]
[專利文件1]日本專利昭和60年第164358號公開公報
不過,上述習知技術中,在基極電極的外側形成 的基極集極半導體層中,藉由注入氫離子(H+)、氧離子(O+)、硼離子(B+),達成高電阻化產生的非活化。例如,基極層中殘留的H+受到基極層不純物的影響,成為HBT的電流增益β變動主因。又,O+及B+成為不純物,有絕緣性問題。於是,上述習知的非活化技術,藉由穩定半導體層的側面,根據確保半導體元件可靠性的觀點,還留下改善點。
因為本發明係用以解決上述的問題而形成,目的為提供可以降低接面電容的同時穩定半導體層的側面之半導體元件。
根據本發明的半導體元件,包括第1半導體層,包括第1側面,具有第1導電型;第2半導體層,層壓在上述第1半導體上,包括上面與第2側面,具有與上述第1導電型相反的第2導電型;第3半導體層,層壓在上述上面的一部分中,具有上述第1導電型;第1電極,電性連接上述第1半導體層;第2電極,圍繞上述第3半導體層,設置在上述上面的另一部分中;以及第3電極,設置在上述第3半導體層中;其中,以平面所視,在比上述上面中的上述第2電極的外側端部更外側,從氦及氬的構成群中選擇1元素,離子注入至上述第1、2半導體層,藉此設置從上述上面延伸至上述第1、2半導體層的接面部更下方之非活性部。
根據本發明,降低第1、2半導體層的接面部的面積,可以降低接面電容的同時,可以穩定第1、2半導體層的 側面。
10‧‧‧半導體元件
11‧‧‧射極層
12‧‧‧射極電極
13‧‧‧基極電極
14‧‧‧基極層
14a‧‧‧上面
15‧‧‧集極層
16‧‧‧集極接觸層
17‧‧‧集極電極
18‧‧‧基極集極層接面部
19‧‧‧非活性部
19a‧‧‧基極非活性部
19b‧‧‧集極非活性部
29‧‧‧非活性部
29a‧‧‧基極非活性部
29b‧‧‧集極非活性部
39‧‧‧非活性部
39a‧‧‧基極非活性部
39b‧‧‧集極非活性部
39c‧‧‧集極接觸非活性部
111‧‧‧射極層
112‧‧‧射極電極
113‧‧‧基極電極
114‧‧‧基極層
115‧‧‧集極層
116‧‧‧歐姆集極層
117‧‧‧集極電極
118‧‧‧接面部
119‧‧‧接面端部
1110‧‧‧端部
[第1圖]係顯示根據本發明實施例的半導體元件圖; [第2圖]係顯示根據本發明實施例的半導體元件圖; [第3圖]係顯示根據本發明實施例的半導體元件圖; [第4圖]係顯示根據本發明實施例的半導體元件圖;以及 [第5圖]係顯示具有用以說明本發明課題的典型的HBT構造之半導體元件圖。
第1圖,係顯示根據本發明實施例的半導體元件10的剖面圖。第2圖,係顯示根據本發明實施例的半導體元件10的平面圖。第1圖,係沿著第2圖的A-A’線,切斷半導體元件10。
半導體元件10,係高頻電力放大器使用的GaAs(砷化鎵)基的異質接面型雙極電晶體(HBT)。半導體元件10,包括以高濃度N型半導體層形成的集極接觸層16。集極接觸層16上,層壓N型的集極層15;高濃度P型半導體層的基極層14,層壓在集極層15上,包括上面14a;以及N型射極層11,層壓在上面14a的一部分中。基極層14與集極層15的接合面中,形成基極集極接面部18。
集極接觸層16上,夾入集極層15,設置2個集極電極17。射極層11上,設置射極電極12。圍繞射極層11,在上面14a的另外一部分設置基極電極13。
非活性部19,以平面所視,係設置在比上面14a中的基極電極13的外側端部更外側。非活性部19,係由不活化基極層14的基極非活性部19a、及不活化集極層15的集極非活性部19b構成。非活性部19,係從氦及氬的構成群中選擇1元素,離子注入至集極層15及基極層14而形成。非活性部19,從上面14a延伸至基極集極層接面部18更下方。
特別在第一實施例中,根據第1圖的剖面圖可了解,剖面圖中基極層14的側面上端到集極層15的側面中途,設置非活性部19。因此,非活性部19的端部在集極層15的的中央部附近結束。
又,根據第2圖的剖面圖可了解,非活性部19,以平面所視,係連續圍繞基極電極13的周圍。
根據本實施例,對於基極電極的外側設置的半導體接面部的基極接觸層接面部,設置從氦及氬的構成群中選擇1元素離子注入的非活性部。因此,基極接觸層接面部的面積降低,可以降減接面電容(Cbc)的同時,可以穩定基極集極層接面部的側面。
因為非活性部19為絕緣狀態,基極集極層接面部18的外圍端部不存在PN接面。因此,可以降低基極集極層接面部18的面積,可以實效縮小PN接面面積。又,半導體層表面,非活性前露出PN接面部。因此,基極集極接面施加電場時,半導體界面部中由於製程的偏離容易有電場依存性。這點,根據本實施例,藉由執行絕緣注入,可以穩定電場產生的影響。
本實施例中,藉由非活性離子的氦(He+)或氬(Ar+)的絕緣注入,設置非活性部19。藉由使用這些非活性化元素的離子注入,可以形成可靠性也不降低的穩定非活性部19。
本實施例中,形成非活性部19的離子注入之際,非活性部19不到達高濃度N型半導體層的集極接觸層16。這以從集極層15中絕緣基極層14的注入加速能量及注入量形成即可。藉此,可以抑制HBT的電氣特性下降。
說明關於抑制HBT的電氣特性下降時,首先HBT的一般動作,射極為GND電位,施加電流至基極電極,並施加集極電壓。在此情況下,集極電流的流動係流過集極電極17、高濃度N型半導體的集極接觸層16、N型半導體構成的集極層15→P型半導體構成的基極層14→N型半導體構成的射極層11→射極電極12的路徑。
在此,如果施加到達高濃度N型半導體的集極接觸層16之絕緣注入時,低電阻為目的的高濃度化的集極接觸層16成為高電阻。於是,HBT的集極射極間的電阻變高。特別是導通電阻上升,電晶體特性下降。本實施例中,因為非活性部19儘量不到達集極接觸層16,可以抑制HBT的電氣特性下降。
高頻特性的指標的最大振盪頻率fmax以次式表示。
藉由縮小PN接面面積S,可以減少基極集極層接面部18的接面電容(Cbc)。因為不影響其他HBT活性區域,預料HBT 單體的主要特性原封不動,高速化、低消費電力化等的高頻特性提高。又,藉由穩定不穩定的半導體界面準位,可以穩定基極集極間的表面不穩定引起的漏電流
第3圖係顯示根據本發明實施例的半導體元件圖。第3圖所示的變形例中,非活性部29設置到集極接觸層16與集極層15的邊界為止。即,集極層15的側面全部不活化。非活性部29,係由不活化基極層14的基極非活性部29a、及完全不活化集極層15側面的集極非活性部29b構成。又,平面所視的形狀與第2圖相同。
第4圖係顯示根據本發明實施例的半導體元件圖。第4圖所示的變形例中,非活性部39,設置到集極接觸層16的內部為止。即,基極層14的側面、集極層15的側面及集極接觸層16的上面的一部分不活化。非活性部39,係由不活化基極層14的基極非活性部39a、不活化集極層15的集極非活性部39b、以及不活化集極接觸層16的集極接觸非活性部39c構成。又,平面所視的形狀與第2圖相同。
10‧‧‧半導體元件
11‧‧‧射極層
12‧‧‧射極電極
13‧‧‧基極電極
14‧‧‧基極層
14a‧‧‧上面
15‧‧‧集極層
16‧‧‧集極接觸層
17‧‧‧集極電極
18‧‧‧基極集極層接面部
19‧‧‧非活性部
19a‧‧‧基極非活性部
19b‧‧‧集極非活性部

Claims (6)

  1. 一種半導體元件,包括:第1半導體層,包括第1側面,具有第1導電型;第2半導體層,層壓在上述第1半導體上,包括上面與第2側面,具有與上述第1導電型相反的第2導電型;第3半導體層,層壓在上述上面的一部分中,具有上述第1導電型;第1電極,電性連接上述第1半導體層;第2電極,圍繞上述第3半導體層,設置在上述上面的另一部分中;以及第3電極,設置在上述第3半導體層中;其特徵在於:以平面所視,在比上述上面中的上述第2電極的外側端部更外側,從氦及氬的構成群中選擇1元素,離子注入至上述第1、2半導體層,藉此設置從上述上面延伸至上述第1、2半導體層的接面部更下方之非活性部。
  2. 如申請專利範圍第1項所述的半導體元件,其中,以剖面所視,上述第2側面上端到上述第1側面中途,設置上述非活性部。
  3. 如申請專利範圍第1或2項所述的半導體元件,其中,以平面所視,上述非活性部連續圍繞上述第2電極的周圍。
  4. 如申請專利範圍第1或2項所述的半導體元件,其中,上述第1半導體層是集極層,上述第2半導體層是基極層,上述第3半導體層是射極層,上述第1電極是集極電極, 上述第2電極是基極電極,以上述第3電極是射極電極之異質接面型雙極電晶體。
  5. 如申請專利範圍第1項所述的半導體元件,更包括:接觸層;其中,上述接觸層上層壓上述第1半導體層;以及上述非活性部,設置到上述接觸層與上述第1半導體層的邊界為止。
  6. 如申請專利範圍第1項所述的半導體元件,更包括:接觸層;其中,上述接觸層上層壓上述第1半導體層;以及上述非活性部,設置到上述接觸層的內部為止。
TW103116948A 2013-10-02 2014-05-14 半導體元件 TWI501393B (zh)

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US20040262634A1 (en) * 2003-06-30 2004-12-30 Keiichi Murayama Hetero-junction bipolar transistor and manufacturing method thereof
US20060131608A1 (en) * 2004-11-30 2006-06-22 Kabushiki Kaisha Toshiba Semiconductor device
TW200629363A (en) * 2003-09-02 2006-08-16 Epitactix Pty Ltd Method and structure for a high performance heterojunction bipolar transistor

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JPS60164358A (ja) 1984-02-06 1985-08-27 Fujitsu Ltd 半導体装置の製造方法
EP0300803B1 (en) * 1987-07-24 1994-06-22 Matsushita Electric Industrial Co., Ltd. High-frequency bipolar transistor and its fabrication method
JP5386764B2 (ja) * 2008-10-10 2014-01-15 独立行政法人産業技術総合研究所 光検出素子

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US20040262634A1 (en) * 2003-06-30 2004-12-30 Keiichi Murayama Hetero-junction bipolar transistor and manufacturing method thereof
TW200629363A (en) * 2003-09-02 2006-08-16 Epitactix Pty Ltd Method and structure for a high performance heterojunction bipolar transistor
US20060131608A1 (en) * 2004-11-30 2006-06-22 Kabushiki Kaisha Toshiba Semiconductor device

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