TWI492336B - 用於影像感測器之階式封裝體及其製造方法 - Google Patents

用於影像感測器之階式封裝體及其製造方法 Download PDF

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Publication number
TWI492336B
TWI492336B TW101124616A TW101124616A TWI492336B TW I492336 B TWI492336 B TW I492336B TW 101124616 A TW101124616 A TW 101124616A TW 101124616 A TW101124616 A TW 101124616A TW I492336 B TWI492336 B TW I492336B
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Taiwan
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chamber
holes
wafer
processor
image sensor
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TW101124616A
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TW201312707A (zh
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Vage Oganesian
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Optiz Inc
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Description

用於影像感測器之階式封裝體及其製造方法 發明領域
本發明係有關於微電子元件之封裝，更特定言之係有關於光學半導體元件之封裝。
 發明背景
半導體元件之趨勢在於較小的積體電路(IC)元件(亦視為晶片)，封裝在較小的封裝體中(保護該晶片同時提供晶片外信號連接)。其中一實例係為影像感測器，其係為IC元件包括光探測器將入射光轉換成電信號(精確地表現具有良好空間解析度的入射光之強度與色彩資訊)。
目前，晶片直接安裝(COB-其中將裸晶片直接地安裝在一印刷電路板上)及Shellcase晶圓級晶片尺寸封裝(CSP)(其中該晶圓係層合在二玻璃片之間)係為用以建構影像感測器模組(例如，用於行動裝置相機、光學滑鼠等)的最具支配性的封裝與裝配製程。然而，當使用越高像素影像感測器時，COB及Shellcase晶圓級晶片尺寸封裝(WLCSP)由於裝配限制、尺寸限制(該需求係針對較小外形裝置)、以及針對8與12吋影像感測器晶圓封裝的產量問題及資本投資而變得越來越困難。例如，該Shellcase WLCSP技術包含在該晶圓切單成個別封裝晶片之前將該等影像感測器封裝在該晶圓上，意謂著源自於每一晶圓的該等具缺陷的晶片係仍在其進行測試之前接受封裝(使成本上升)。
具有對於針對已經切單及測試的諸如影像感測器晶片的該等晶片的一改良。式封裝體及封裝技術的需求，以及提供一低外形封裝解決方案其係具成本效益且確實可靠(亦即，提供該必要的機械方面支援及電氣連接性)。
 發明概要
本發明之一觀點係為一影像感測器封裝體包括一結晶處理器，其具有相對的第一及第二表面，該處理器包括一腔室構成於該第一表面中以及至少一階梯部分其係自該腔室之一側壁延伸，其中該腔室係於該第二表面處之一孔口中終止，一蓋其係安裝至該第二表面並延伸超越及覆蓋該孔口，其中該蓋係對至少一光波長範圍為可透光的，以及一感測器晶片其係配置在該腔室中並安裝至該至少一階梯部分。該感測器晶片包括具有前與背相對表面之一基板，構成位在前表面處之複數之光探測器，以及構成位在前表面處之複數之接點墊，其係電耦合至該等光探測器。
於本發明之另一觀點中，一影像感測器封裝體包括一處理器具有相對的第一及第二表面以及一感測器晶片。該處理器係對至少一光波長範圍為可透光的，包括一腔室其係構成於該第一表面中未抵達該第二表面，其中該腔室包括至少一階梯部分其係自該腔室之一側壁延伸。該感測器晶片其係配置在該腔室中並係安裝至該至少一階梯部分。該感測器晶片包括一基板具有前與背相對表面，複數之光探測器係構成位在前表面，以及複數之接點墊係構成位在 前表面其係電耦合至該等光探測器。
於本發明之又一觀點中，構成一影像感測器封裝體的一方法包括提供一結晶處理器具有相對的第一及第二表面，構成一腔室於該第一表面中具有至少一階梯部分其係自該腔室之一側壁延伸，其中該腔室係於該第二表面處之一孔口中終止，安裝一蓋至該第二表面，該蓋係延伸超越及覆蓋該孔口，其中該蓋係對至少一光波長範圍為可透光的，以及安裝一感測器晶片於該腔室中並安裝至該至少一階梯部分。該感測器晶片包括一基板具有前與背相對表面，複數之光探測器係構成位在前表面，以及複數之接點墊係構成位在前表面其係電耦合至該等光探測器。
於本發明之再一觀點中，構成一影像感測器封裝體的一方法包括提供一處理器具有相對的第一及第二表面，構成一腔室於該第一表面中且未抵達該第二表面，其中該腔室包括至少一階梯部分其係自該腔室的一側壁延伸，以及其中該處理器係對至少一光波長範圍為可透光的，以及安裝一感測器晶片於該腔室中並安裝至該至少一階梯部分。該感測器晶片包括一基板具有前與背相對表面，構成位在前表面之複數之光探測器，以及構成位在前表面之複數之接點墊，其係電耦合至該等光探測器。
本發明之其他目的及特性藉由檢閱說明書、申請專利範圍及附加的圖式將為顯而易見的。
 發明之詳細說明
本發明係為一晶圓級、低應力封裝體解決方案，對於影像感測器係為非常適合的。以下說明該低應力封裝體解決方案之構成。
該構成製程係以一結晶處理器6作為開始，其各別地包括頂部及底部表面8與10。一腔室12係構成於該處理器6之該底部表面10中，如於第1A圖中顯示。腔室12係可藉由使用雷射，電漿蝕刻製程，噴沙製程，一機械球磨製程，或是任何其他相似方法而構成。較佳地，腔室12係藉由光微影電漿蝕刻所構成，包括在該處理器6上構成一光阻劑層，將該光阻劑層圖案化以暴露處理器6之一選定部分，並接著執行一電漿蝕刻製程(例如，使用一SF6電漿)以去除該處理器6之該暴露部分用以構成該腔室12。較佳地，該腔室12延伸不超過該結晶基板厚度的3/4，或至少在約50微米之該腔室的該最大深度部分處留有一最小的厚度。該電漿蝕刻可為各向異性的、錐形的、等向的或是其等之結合方式。如所顯示，該電漿蝕刻係經錐形化，其中該腔室側壁14與該垂直方向具有一約為5度的角度(亦即，該等側壁14係於深度方向向內地延伸)。接著藉由以上所列針對構成腔室12的任何技術構成一孔口16通過該結晶處理器6之該薄化部分(由腔室12通過頂部表面8)。孔口16之該橫向尺寸(亦即，直徑)係較腔室12之該等尺寸為小，導致一階梯式側壁14(亦即，讓階梯部分18朝著孔口16之該中心向外延伸，其中階梯部分18包括一大體上橫向延伸的表面，於一大體上垂直延伸的表面處終止)。較佳地，階梯部分18係為連續地環繞 腔室12之周圍(亦即，階梯部分18係為界定孔口16的一環狀肩部分之形式)。然而，構成複數之各別的階梯部分18其係於各別位置處向內地朝向該孔口16之中心延伸。為確保正確地經由孔口16成像，孔口16之該等尺寸較佳地係稍微大於該感測器晶片之該成像區域(例如，至少50微米)(以下加以說明)。該最終結構係於第1A圖中顯示。
接著在該底部表面10及腔室側壁14與階梯部分18上構成一隔離(介電)層20。層20可為氧化矽、氮化矽、環氧基、聚醯亞胺樹脂、FR4或是任何適合的介電材料。較佳地，層20之厚度至少係為0.1微米，並且係使用任何傳統式介電層沉積技術(於業界係為廣為熟知的)構成。接著一傳導性層22係構成位在層20上。傳導性層22可為銅、銅/鎳/金、銅/金、鈦/銅/金、鋁/鎳/銅或是另外的廣為熟知之傳導性材料。接著執行一光微影蝕刻步驟以去除緊鄰底部表面10之外邊緣，階梯部分18之內邊緣(與孔口16相鄰)以及以上部分之選擇性部分的層22之該等部分，用以構成複數之各別跡線23其分別地自階梯部分18延伸至底部表面10。該最終結構係於第1B圖中顯示。
一介電層24係經構成覆蓋傳導性層22(以及隔離層22之該等暴露部分)。層24可為氧化矽、氮化矽、環氧基、聚醯亞胺樹脂、FR4或是任何適合的介電材料。較佳地，層24之厚度至少係為0.1微米，並且係使用任何適合的介電層沉積技術(於業界係為廣為熟知的)構成，諸如電化學沉積、層合、噴塗或旋轉塗佈等。接著執行一光微影蝕刻步驟以去 除位在階梯部分18上以及底部表面10的層24之選擇性部分，用以暴露傳導性層22之選擇性部分(亦即，每一跡線23之該等端部部分)。傳導性層22之該等選擇性地暴露部分分別地構成接點墊26/28。該最終結構係於第1C圖中顯示。
表面安裝(SMT)互連裝置30係接著經構成位在接點墊28上。SMT互連裝置可為球柵陣列封裝(BGA)型，並使用一焊料合金之絲網印刷製程，或是藉由一植球製程，或藉由一電鍍製程而構成。球柵陣列封裝(BGA)互連裝置係為磨圓的導體用於與對應的導體作實體及電接觸，通常藉由將金屬球焊接或部分地熔融位在接點墊上而構成。可交替地，SMT互連裝置可為傳導性金屬桿(例如，銅)。一蓋32係固定至處理器6之該頂部表面8，較佳地利用一黏著劑34。蓋32延伸橫越且較佳地密封孔口16，並係對至少一範圍之光波長(例如，用於相機應用的可見光)為透光的。於一較佳的具體實施例中，蓋32係由玻璃或聚合物構成，具有至少25微米之厚度。該蓋32包括抗反射及/或紅外光塗層。該最終結構係於第1D圖中顯示。
一感測器晶片36係插入於腔室12中並安裝至階梯部分18。該感測器晶片36包括一基板38，複數之光探測器40(以及支援電路)連同接點墊42係構成位在該基板上，該等光探測器40(以及支援電路)及接點墊42係構成位在基板38之該面向上(前)表面處，如第1E圖中所示。該等接點墊42係電連接至該等光探測器40(及/或其之支援電路)以提供晶片外信號。每一光探測器40將光能轉換成一電壓信號。晶片上 可包括附加的電路以放大該電壓，及/或將其轉換成數位數據。濾色器44及微透鏡46係經安裝覆蓋該等光探測器40。此型式之影像感測器於業界係廣為熟知的，於此不再進一步說明。該感測器晶片36係以機械方式並經由覆晶連接器48電連接至該處理器6，將每一接點墊42(位在感測器晶片36)與其中之一接點墊26(位在階梯部分18上)電連接。連接器48之實例包括BGA、柱形金凸塊以及導電膏。一可任擇的囊封(介電)材料可用以填注腔室12，並從而將感測器晶片36囊封於其中。在現在這種情況下，第1E圖之該封裝感測器晶片總成提供複數優點。首先，配置具有一階梯式腔室(亦即，該感測器晶片36安裝至的一側向延伸的階梯部分18)一結晶處理器6，提供優越的機械及電氣穩定性，以及一可靠的技術用於將該感測器晶片36安裝並電連接至該處理器6。第二，藉由構成在處理器6上的傳導性層22可靠地提供晶片外連接性。第三，藉由提供與該完成的感測器晶片36分開的一封裝結構，感測器晶片36能夠在安裝之前完全地加以測試，從而節省封裝結果是為缺陷的感測器晶片之成本。第四，構成腔室12之壁具有一傾斜，潛在地降低在該結晶處理器上由於90度角落所導致誘發應力所造成的損害。第五，腔室12之該等傾斜側壁亦意指無負角區域，其會造成構成於其上的該等材料層中之間隙。第六，首先藉由構成隔離層20，並接著於其上構成金屬化層22，避免金屬擴散進入該結晶處理器6中。第七，藉由以蓋32密封孔口16，保護微透鏡46不受污染同時容許光線通過蓋32並抵達 感測器晶片36。第七，感測器晶片36能夠囊封於處理器6中以達較佳的裝置保護與可靠性。第八，該封裝體結構能夠用於複數組件之並列整合，諸如背側照明影像感測器與支援處理器及記憶體晶片整合於一SMT相容封裝體中，而未增加該封裝體之該總高度。
第2A-2G圖圖示一第一可交替具體實施例之構成，其中該蓋32係在該處理器6經處理以構成腔室12、孔口16及階梯部分18(使用如以上相關於第1A圖說明的該等相同處理步驟)之前安裝至該結晶處理器6(如於第2A圖中所示)。該最終結構係於第2B圖中顯示。
該感測器晶片36接著插入於腔室12中，並經由一介電安裝材料60(例如，環氧化物、膠帶等)安裝至階梯部分18，如第2C圖中所示。在現在這種情況下，能夠藉由矽蝕刻而降低該處理器6之高度，其去除處理器6之底部部分因此其之底部表面10係與該感測器晶片背面齊平的。接著一介電材料62被構成覆蓋底部表面10及位於腔室12中，將感測器晶片36囊封在腔室12中。該最終結構係於第2D圖中顯示。
孔64接著被構成穿過該介電材料62並進入該感測器晶片基板38，以暴露接點墊42。針對較大尺寸孔64藉由使用CO2 雷射(例如，約為70奈米的光點大小)，或是針對較小尺寸孔64(例如，直徑小於50微米)藉由使用UV雷射(例如，在355奈米的一波長下約為20奈米的光點大小)而構成孔64。可使用在小於140奈秒的一脈衝長度下，介於10與50kHz之間的雷射脈衝頻率。該等孔64之外形係為錐形化的，在孔 64所構成穿過的該表面處具有一較大的尺寸。較佳地，該最小與最大孔直徑分別約為5至250微米，以及相對於與該等孔64所構成穿過的該表面垂直的一方向，該等壁之角度係介於0度與45度之間(亦即，以致該等孔64在該等接點墊42處具有較小的橫截面尺寸)。一絕緣層66係藉由薄膜塗佈(例如，噴霧、旋轉及/或電化學沉積)以及光微影製程構成位在孔64之側壁上。該最終結構係於第2E圖中顯示。
接著將一傳導性材料層68沉積覆蓋介電材料層62，亦以該傳導性材料填注孔64。傳導性材料層68較佳地係為一金屬材料，諸如銅、鎢、鋁、鋁銅合金等。接著執行一光微影製程以選擇性地去除部分之傳導性層68，留有扇入/扇出(fan-in/fan-out)互連裝置70其分別與其中之一接點墊42電連接。該最終結構係於第2F圖中顯示。
一介電(絕緣)材料層72係構成覆蓋層62及互連裝置70。接著執行一光微影製程以選擇性地去除覆蓋互連裝置70的介電層72之該等部分，因而暴露互連裝置70。該等SMT互連裝置30接著係構成位在互連裝置70上，較佳地係為BGA型式互連裝置之形式。該最終結構係於第2G圖中顯示。
就第2G圖之該具體實施例而言，晶片外傳導性之路線為由該感測器晶片接點墊42，經由傳導性材料67通過該感測器晶片基板38並至SMT互連裝置30。除以上所列優點外，該結構能夠達到較高位準的路線安排與較短的互連裝置，有助於改良電氣性能及降低功率消耗。
相關於第2G圖之該具體實施例，應注意的是於構成傳 導性層68當中，不需填注孔64，而是能夠沿著孔64之側壁構成一傳導性層，如於第3圖中所示。同時於第3圖中所示係為未與孔64對準的互連裝置30(亦即，所顯示如同扇出互連裝置)，以及蓋32具有一較處理器6為小的橫向尺寸。
第4圖圖示一第二可交替具體實施例，其中蓋32係一體成型為一透光的處理器6的一部分。取代將孔口16構成為自腔室12延伸至處理器6之頂部表面8，腔室12延伸超越階梯部分18相當足以容納濾色器44及微透鏡46。於此具體實施例中，該處理器6較佳地係以一非晶質(非結晶)玻璃。處理器6之單體(單一材料)結構藉由保護該感測器晶片36不致受到濕氣及不良的有機材料影響，而能夠有一較高位準的密封性控制作業環境。濕氣穿透對於浸沒於液體或高濕度環境的封裝體係為一常見的失效模式。封裝體內部的濕氣會造成在該元件之活性區域上凝結，導致結構腐蝕及/或性能降低。此外，該結構亦消除對於密封腔室的需求，並因而較使用高溫陽極、熔化、焊接等黏合製程的結構具有一較高的容限及可靠性。
第5圖圖示一第三可交替具體實施例，其包括一用於該感測器晶片36的整合式處理器。一第二腔室82係構成位於該處理器6中與腔室12橫向相鄰(以用以構成腔室12相同的方式)。接著將一第二晶片(例如，一處理器IC晶片)84插入第二腔室82中。該IC晶片84包括一處理器積體電路86用於處理源自於該感測器晶片36的信號。該IC晶片82包括傳導性接點墊88係暴露位在其之前表面上，用於通訊晶片上及 晶片外信號。該IC晶片84係藉由介電材料62囊封在第二腔室82中。暴露接點墊88的孔90可以構成孔64的相同方式構成通過介電材料62。孔90可以傳導性材料68填注，以及SMT互連裝置30構成於其上，如於以上說明並於第5圖中圖示。
第5圖之具體實施例的優點在於其提供將感測器晶片36與處理器晶片84共同封裝。該處理器晶片84包含硬體處理器與軟體運算法之一結合，一起地組成影像感測器用於由個別的光探測器40收集亮度及色差資訊，並加以使用以針對每一像素計算/內插正確的色彩與亮度值。該影像處理器評估一已知像素的色彩及亮度數據，將其與源自於鄰近像素的數據比較並接著使用一色彩插補運算法從一不完全色彩樣本重建一完整色彩影像，並針對該像素產生一適合的亮度值。該影像處理器亦評估該整個相片並修正銳度及減小影像之雜訊。
影像感測器之進展導致影像感測器中像素數目越來越高，以及附加的相機功能性，諸如自動對焦、變焦、消除紅眼、臉部追蹤等，需要能夠在較高速度下操作之更為強有力的影像感測器處理器。攝影師不希望在完成拍攝之前等候該相機處理器完成其之工作-其甚至不希望被通知該相機內部正在進行一些處理作業。因此，影像處理器必需經最佳化以在相同或甚至更短時段內妥善地處理更多的數據。
以上所說明並於第1-5圖中圖示的該感測器晶片36係為一前面照射(FSI)型式感測器，其中該等光探測器40、支 援電路及接點墊42、濾色器及微透鏡係構成位在該晶片的前表面上，以及該等光探測器40係經定向以捕捉/測量衝射該晶片之該前表面的光線。然而，後面照射(BSI)型式感測器亦係為熟知的，其中該等探測器係經組配以捕捉/測量進入通過該晶片之背表面的光線，藉此該光線通過該矽基板並至該等光探測器。該等濾色器44及微透鏡46係安裝至該晶片之該背表面。BSI感測器之優點在於所配置的電路通常係較該等光探測器接近該晶片之該前表面，當光線由該背表面進入時可避免該電路。上述的封裝技術可使用BSI型式感測器晶片而加以應用，如於第6圖中所示，其中該背表面(取代該前表面)係安裝至該(等)階梯部分(18)，以及孔64僅延伸通過介電材料62以暴露接點墊42(不需針對孔以延伸進入該基板)。
應瞭解的是本發明並不限定在以上說明及於此圖示的該(等)具體實施例，但包含涵蓋於該等附加的申請專利範圍之範疇內的任何及所有的變化形式。例如，於此本發明之參考資料並不意欲限定任一申請專利範圍或是申請專利範圍項之範疇，而僅是替代地參考由一或更多申請專利範圍所涵蓋的一或更多特性。以上說明的材料、製程及數值實例係僅為示範性的，並且不應視為限定該等申請專利範圍。再者，如同由該等申請專利範圍及說明書為顯而易見的，並非所有的方法步驟需以圖示或是主張的準確順序執行，而是個別地或是同時地以任意順序執行，容許正確地形成本發明之BSI影像感測器封裝作業。可構成單一材料層 作為複數之該等或是相似材料層，反之亦然。
應注意的是，如於此所使用，該用語“覆蓋(over)”及“位在..上(on)”二者包含地包括“直接地位在..上(directly on)”(無中間材料，元件或是空間配置於其間)以及“間接地位在..上(indirectly on)”(中間材料，元件或是空間配置於其間)。同樣地，該用語“相鄰(adjacent)”包括“直接地相鄰(directly adjacent)”(無中間材料，元件或是空間配置於其間)以及“間接地相鄰(indirectly adjacent)”(中間材料，元件或是空間配置於其間)，“安裝至(mounted to)”包括“直接地安裝至(directly mounted)”(無中間材料，元件或是空間配置於其間)以及“間接地安裝至(indirectly mounted to)”(中間材料，元件或是空間配置於其間)，以及“電耦合(electrically coupled)”包括“直接地電耦合至(directly electrically coupled to)”(於其間無中間材料、元件，將該等元件電連接在一起)以及“間接地電耦合至(indirectly electrically coupled to)”(於其間中間材料、元件，將該等元件電連接在一起)。例如，構成一元件“覆蓋一基板”可包括直接地構成該元件位在該基板上而於其間無中間的材料/元件，以及於其間具有一或更多中間的材料/元件而間接地將該元件構成位在該基板上。
6‧‧‧結晶處理器
8‧‧‧頂部表面
10‧‧‧底部表面
12‧‧‧腔室
14‧‧‧腔室側壁
16‧‧‧孔口
18‧‧‧階梯部分
20‧‧‧隔離(介電)層
22‧‧‧傳導性層/金屬化層
23‧‧‧跡線
24‧‧‧介電層
26,28‧‧‧接點墊
30‧‧‧表面安裝(SMT)互連裝置
32‧‧‧蓋
34‧‧‧黏著劑
36‧‧‧感測器晶片
38‧‧‧基板
40‧‧‧光探測器
42‧‧‧接點墊
44‧‧‧濾色器
46‧‧‧微透鏡
48‧‧‧覆晶連接器
60‧‧‧介電安裝材料
62‧‧‧介電材料
64‧‧‧孔
66‧‧‧絕緣層
67‧‧‧傳導性材料
68‧‧‧傳導性材料層
70‧‧‧扇入/扇出互連裝置
72‧‧‧介電(絕緣)材料層
82‧‧‧第二腔室
84‧‧‧第二晶片
86‧‧‧處理器積體電路
88‧‧‧傳導性接點墊
90‧‧‧孔
第1A-1E圖係為一半導體封裝結構的側橫截面視圖，按順序地顯示用於一影像感應器的該封裝結構之製程中該等步驟。
第2A-2G圖係為該半導體封裝結構的一可交替具體實施例之側橫截面視圖，按順序地顯示用於一影像感應器的該封裝結構之製程中該等步驟。
第3圖係為第2G圖之該具體實施例的一側橫截面視圖，但針對該等半導體孔中的該傳導性材料、該蓋及該等互連裝置具有修改的構態。
第4圖係為該半導體封裝結構之一第二可交替具體實施例的一側橫截面視圖。
第5圖係為該半導體封裝結構之一第三可交替具體實施例的一側橫截面視圖。
第6圖係為第2G圖之該具體實施例的一側橫截面視圖，但具有一BSI型感測器。
6‧‧‧結晶處理器
8‧‧‧頂部表面
10‧‧‧底部表面
18‧‧‧階梯部分
20‧‧‧隔離(介電)層
22‧‧‧傳導性層/金屬化層
23‧‧‧跡線
24‧‧‧介電層
26‧‧‧接點墊
30‧‧‧表面安裝(SMT)互連裝置
32‧‧‧蓋
34‧‧‧黏著劑
36‧‧‧感測器晶片
38‧‧‧基板
40‧‧‧光探測器
42‧‧‧接點墊
44‧‧‧濾色器
46‧‧‧微透鏡
48‧‧‧覆晶連接器

Claims (12)

  1. 一種影像感測器封裝體，其包含：一結晶處理器(crystalline handler)，其具有相對的第一及第二表面，該處理器包括一腔室及至少一階梯部分，該腔室係構成於該第一表面中，而該至少一階梯部分係自該腔室之一側壁延伸，其中該腔室係於該第二表面處之一孔口中終止；一蓋，其係安裝至該第二表面並延伸超越及覆蓋該孔口，其中該蓋係對至少一光波長範圍為可透光的；一感測器晶片，其係配置在該腔室中，其中該感測器晶片包括：一基板，其具有相對的前與背表面，構成位在該前表面處之複數之光探測器，以及構成位在該前表面處之複數之接點墊，該等接點墊係電耦合至該等光探測器，其中該感測器晶片之該前表面係安裝至該至少一階梯部分；複數之導電跡線，每一導電跡線係構成位在該至少一階梯部分的一表面、該腔室之該側壁的一表面、以及該第一表面上，並與該至少一階梯部分的表面、該腔室之該側壁的表面、以及該第一表面相隔離(insulated)；以及複數之電連接器，其係配置在該基板之該前表面與該至少一階梯部分之間，其中每一電連接器係於該等跡 線中之一跡線、與該等接點墊中之一接點墊之間電連接。
  2. 如申請專利範圍第1項之影像感測器封裝體，其進一步包含：介電材料，其配置在該腔室中並將該感測器晶片囊封在該腔室中。
  3. 如申請專利範圍第1項之影像感測器封裝體，其中該感測器晶片係藉由配置在該至少一階梯部分與該前表面之間的介電材料，而安裝至該至少一階梯部分。
  4. 如申請專利範圍第1項之影像感測器封裝體，其進一步包含：位在該基板中之複數個孔，每一孔係自該背表面延伸至該等接點墊中之一接點墊；位於每一孔中的傳導性材料，其係自該一接點墊延伸至該背表面；以及複數之表面安裝互連裝置，每一者係配置覆蓋該第一表面或是該背表面，以及每一者係電連接至位於該複數個孔中之一孔中的該傳導性材料。
  5. 如申請專利範圍第4項之影像感測器封裝體，其進一步包含：一介電材料，其延伸覆蓋該第一及背表面並將該感測器晶片囊封在該腔室中，其中該複數個孔中之每一孔延伸通過該介電材料。
  6. 如申請專利範圍第1項之影像感測器封裝體，其進一步 包含：位在該基板中之複數個孔，每一孔係自該背表面延伸至該等接點墊中之一接點墊，其中每一孔包括一傳導性材料層，該傳導性材料層係與該一接點墊電接觸，並沿著該孔之一側壁延伸且與該孔之側壁相隔離；以及複數之表面安裝互連裝置，每一者係配置覆蓋該第一表面或是該背表面，以及每一者係電連接至該等傳導性材料層中之一傳導性材料層。
  7. 如申請專利範圍第1項之影像感測器封裝體，其進一步包含：一第二腔室，其係構成位在該處理器之該第一表面中；一處理器晶片，其係配置位在該第二腔室中，該處理器晶片包含：一第二基板，構成位在該第二基板上之處理電路，以及構成位在該第二基板上之複數個第二接點墊，該等第二接點墊係電耦合至該處理電路。
  8. 如申請專利範圍第7項之影像感測器封裝體，其進一步包含：一介電材料，其延伸覆蓋該處理器之該第一表面、該感測器晶片及該處理器晶片，該介電材料將該感測器晶片囊封在該腔室中，以及將該處理器晶片囊封在該第二腔室中。
  9. 如申請專利範圍第8項之影像感測器封裝體，其進一步包含：複數之第一孔，每一第一孔係自該感測器晶片的該等接點墊中的一接點墊延伸、通過該感測器晶片之該基板、以及通過該介電材料；位在每一第一孔中的傳導性材料，該傳導性材料係自該感測器晶片之該一接點墊延伸、通過該感測器晶片之該基板、以及通過該介電材料；複數之第二孔，每一第二孔係自該處理器晶片的該等接點墊中之一接點墊延伸並通過該介電材料；以及位在每一第二孔中的傳導性材料，該傳導性材料係自該處理器晶片之該一接點墊延伸以及通過該介電材料。
  10. 如申請專利範圍第9項之影像感測器封裝體，其進一步包含：第一複數之表面安裝互連裝置，每一者係配置覆蓋該第一表面或感測器晶片，且每一者係電連接至位於該等第一孔中的一者內的該傳導性材料；以及第二複數之表面安裝互連裝置，每一者係配置覆蓋該第一表面或該處理器晶片，且每一者係電連接至位於該等第二孔中的一者內的該傳導性材料。
  11. 如申請專利範圍第1項之影像感測器封裝體，其中該感測器晶片係藉由配置在該至少一階梯部分與該背表面之間的介電材料，而安裝至該至少一階梯部分。
  12. 如申請專利範圍第1項之影像感測器封裝體，其進一步包含：延伸覆蓋該等第一及前表面之一介電材料，該介電材料將該感測器晶片囊封在該腔室中；複數之孔，每一孔係延伸通過該介電材料至該等接點墊中的一接點墊；位於每一孔中的傳導性材料，該傳導性材料自該一接點墊延伸；以及複數之表面安裝互連裝置，每一者係配置覆蓋該第一表面或是該前表面，且每一者係電連接至位於該等孔中之一者中的該傳導性材料。
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