TWI491015B - 用於無窗之導線接合總成之短線最小化 - Google Patents

用於無窗之導線接合總成之短線最小化 Download PDF

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Publication number
TWI491015B
TWI491015B TW101136588A TW101136588A TWI491015B TW I491015 B TWI491015 B TW I491015B TW 101136588 A TW101136588 A TW 101136588A TW 101136588 A TW101136588 A TW 101136588A TW I491015 B TWI491015 B TW I491015B
Authority
TW
Taiwan
Prior art keywords
microelectronic
package
terminals
substrate
contacts
Prior art date
Application number
TW101136588A
Other languages
English (en)
Chinese (zh)
Other versions
TW201324734A (zh
Inventor
理查 狄威特 柯斯伯
華爾 柔伊
畢哥辛 哈芭
法蘭克 藍布里奇
Original Assignee
英帆薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/440,290 external-priority patent/US8659142B2/en
Application filed by 英帆薩斯公司 filed Critical 英帆薩斯公司
Publication of TW201324734A publication Critical patent/TW201324734A/zh
Application granted granted Critical
Publication of TWI491015B publication Critical patent/TWI491015B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H10W40/10—
    • H10W90/00—
    • H10W90/701—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H10W70/63—
    • H10W70/635—
    • H10W70/65—
    • H10W70/654—
    • H10W70/655—
    • H10W70/68—
    • H10W72/00—
    • H10W72/241—
    • H10W72/252—
    • H10W72/29—
    • H10W72/536—
    • H10W72/5363—
    • H10W72/5445—
    • H10W72/5473—
    • H10W72/59—
    • H10W72/834—
    • H10W72/859—
    • H10W72/865—
    • H10W72/877—
    • H10W72/884—
    • H10W72/932—
    • H10W72/942—
    • H10W72/944—
    • H10W72/9445—
    • H10W72/967—
    • H10W74/00—
    • H10W74/117—
    • H10W74/142—
    • H10W74/15—
    • H10W90/20—
    • H10W90/22—
    • H10W90/231—
    • H10W90/24—
    • H10W90/26—
    • H10W90/271—
    • H10W90/28—
    • H10W90/288—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W90/734—
    • H10W90/752—
    • H10W90/754—

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)
TW101136588A 2011-10-03 2012-10-03 用於無窗之導線接合總成之短線最小化 TWI491015B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161542488P 2011-10-03 2011-10-03
US201161542553P 2011-10-03 2011-10-03
US201261600271P 2012-02-17 2012-02-17
US13/440,290 US8659142B2 (en) 2011-10-03 2012-04-05 Stub minimization for wirebond assemblies without windows

Publications (2)

Publication Number Publication Date
TW201324734A TW201324734A (zh) 2013-06-16
TWI491015B true TWI491015B (zh) 2015-07-01

Family

ID=47146660

Family Applications (3)

Application Number Title Priority Date Filing Date
TW101136588A TWI491015B (zh) 2011-10-03 2012-10-03 用於無窗之導線接合總成之短線最小化
TW101136592A TWI459537B (zh) 2011-10-03 2012-10-03 用於無窗之導線結合總成之短線最小化
TW101136606A TWI511264B (zh) 2011-10-03 2012-10-03 用於無窗之導線接合總成之短線最小化

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW101136592A TWI459537B (zh) 2011-10-03 2012-10-03 用於無窗之導線結合總成之短線最小化
TW101136606A TWI511264B (zh) 2011-10-03 2012-10-03 用於無窗之導線接合總成之短線最小化

Country Status (5)

Country Link
EP (2) EP2766931B1 (enExample)
JP (2) JP5857129B2 (enExample)
KR (2) KR101945334B1 (enExample)
TW (3) TWI491015B (enExample)
WO (3) WO2013052411A1 (enExample)

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EP3017463A4 (en) * 2014-10-03 2017-03-01 Intel Corporation Overlapping stacked die package with vertical columns
KR102497239B1 (ko) * 2015-12-17 2023-02-08 삼성전자주식회사 고속 신호 특성을 갖는 반도체 모듈
JP7353729B2 (ja) 2018-02-09 2023-10-02 キヤノン株式会社 半導体装置、半導体装置の製造方法
US11227846B2 (en) 2019-01-30 2022-01-18 Mediatek Inc. Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
US11587919B2 (en) * 2020-07-17 2023-02-21 Micron Technology, Inc. Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
US20040145042A1 (en) * 2003-01-14 2004-07-29 Sadayuki Morita Semiconductor device
US7405471B2 (en) * 2000-10-16 2008-07-29 Legacy Electronics, Inc. Carrier-based electronic module
US20090250255A1 (en) * 2008-04-02 2009-10-08 Spansion Llc Connections for electronic devices on double-sided circuit board

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JP3685947B2 (ja) * 1999-03-15 2005-08-24 新光電気工業株式会社 半導体装置及びその製造方法
JP2000315776A (ja) * 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6633078B2 (en) * 2000-03-21 2003-10-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, method for manufacturing an electronic equipment, electronic equipment and portable information terminal
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
DE10055001A1 (de) * 2000-11-07 2002-05-16 Infineon Technologies Ag Speicheranordnung mit einem zentralen Anschlussfeld
DE10139085A1 (de) * 2001-08-16 2003-05-22 Infineon Technologies Ag Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung
JP3785083B2 (ja) * 2001-11-07 2006-06-14 株式会社東芝 半導体装置、電子カード及びパッド再配置基板
JP2004128155A (ja) * 2002-10-01 2004-04-22 Renesas Technology Corp 半導体パッケージ
US7260691B2 (en) * 2004-06-30 2007-08-21 Intel Corporation Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins
US7372169B2 (en) 2005-10-11 2008-05-13 Via Technologies, Inc. Arrangement of conductive pads on grid array package and on circuit board
JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
DE102006042775B3 (de) 2006-09-12 2008-03-27 Qimonda Ag Schaltungsmodul und Verfahren zur Herstellung eines Schaltungsmoduls
JP4913640B2 (ja) * 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
TW200842998A (en) * 2007-04-18 2008-11-01 Siliconware Precision Industries Co Ltd Semiconductor device and manufacturing method thereof
KR20100020772A (ko) * 2008-08-13 2010-02-23 주식회사 하이닉스반도체 반도체 패키지
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US8304286B2 (en) * 2009-12-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with shielded package and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
US7405471B2 (en) * 2000-10-16 2008-07-29 Legacy Electronics, Inc. Carrier-based electronic module
US20040145042A1 (en) * 2003-01-14 2004-07-29 Sadayuki Morita Semiconductor device
US20090250255A1 (en) * 2008-04-02 2009-10-08 Spansion Llc Connections for electronic devices on double-sided circuit board

Also Published As

Publication number Publication date
WO2013052411A1 (en) 2013-04-11
TWI511264B (zh) 2015-12-01
WO2013052441A3 (en) 2013-08-15
TW201322417A (zh) 2013-06-01
JP2015501532A (ja) 2015-01-15
EP2766931A1 (en) 2014-08-20
EP2764545A1 (en) 2014-08-13
EP2764545B1 (en) 2018-07-04
TW201322415A (zh) 2013-06-01
KR20140085490A (ko) 2014-07-07
KR20140085489A (ko) 2014-07-07
WO2013052448A1 (en) 2013-04-11
KR101895017B1 (ko) 2018-10-04
WO2013052411A4 (en) 2013-07-04
TWI459537B (zh) 2014-11-01
WO2013052441A2 (en) 2013-04-11
KR101945334B1 (ko) 2019-02-07
JP5857130B2 (ja) 2016-02-10
JP2014534625A (ja) 2014-12-18
TW201324734A (zh) 2013-06-16
EP2766931B1 (en) 2021-12-01
JP5857129B2 (ja) 2016-02-10

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