TWI489662B - Semiconductor light emitting device and method for manufacturing the same - Google Patents

Description

Semiconductor light emitting device and method of manufacturing same

Cross-reference to related applications

The present application is based on Japanese Patent Application No. 2010-130481, filed on Jun.

Embodiments described herein are generally related to semiconductor light emitting devices and methods of fabricating the same

Semiconductor light-emitting devices that emit visible light or white light have been widely used in lighting devices, backlights for image displays, display devices, and the like. In these areas, the need to shrink devices has been increasing. Moreover, it is necessary to increase productivity, reduce costs, and replace fluorescent and incandescent lamps with semiconductor light-emitting devices that consume less power.

Embodiments of the present invention implement a semiconductor light emitting device and a method of fabricating the same that consume less power.

According to an embodiment, a semiconductor light emitting device includes: a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and Second insulating layer. The semiconductor layer includes a first major surface, a second major surface opposite the first major surface, and a luminescent layer. The first electrode is disposed on a region of the light-emitting layer including the second major surface. The second electrode is disposed on the second major surface. The first insulating layer is disposed on the second major surface of the semiconductor layer and includes a first opening in communication with the first electrode and a second opening in communication with the second electrode. The first interconnect layer is disposed in the first opening in the first insulating layer and is connected to the first electrode. The second interconnect layer is disposed in the second opening in the first insulating layer and is connected to the second electrode. The first metal pillar is disposed on a surface of the first interconnect layer opposite to the first electrode. The second metal pillar is disposed on a surface of the second interconnect layer opposite to the second electrode. The second insulating layer is disposed between a side of the first metal post and a side of the second metal post. An edge of a portion of the first interconnect layer is laterally exposed from the first insulating layer and the second insulating layer.

Embodiments of the present invention can realize a semiconductor light emitting device and a method of manufacturing the same that consume less power.

Embodiments will now be described with reference to the drawings. In the drawings, like components are labeled with the same reference characters. The local area in the wafer state is illustrated in the schematic of the display process.

Fig. 1 is a schematic cross-sectional view showing a semiconductor light emitting device of an embodiment.

The semiconductor light emitting device of this embodiment includes a semiconductor layer 15. The semiconductor layer 15 includes a first major surface 15a and a second major surface formed on an opposite side of the first major surface 15a. The electrode, the interconnect layer, and the resin layer are disposed on the second major surface, and the light is primarily drawn from the first major surface 15a.

The semiconductor layer 15 includes a first semiconductor layer 11 and a second semiconductor layer 13. The first semiconductor layer 11 is, for example, an n-type GaN layer used as a lateral current path. However, the conductivity type of the first semiconductor layer 11 is not limited to the n-type, and the conductivity type may be a p-type. The second semiconductor layer 13 includes a stacked structure in which an illuminating layer (active layer) 12 is interposed between the n-type layer and the p-type layer.

The semiconductor layer 15 is patterned into a concavo-convex arrangement on the second main surface side; and the upper portion and the lower portion are disposed on the second main surface side.

The upper portion is higher than the lower portion with respect to the first major surface 15a. The upper portion already contains the luminescent layer 12. The lower portion does not include the light emitting layer and is disposed outside the periphery (edge) of the light emitting layer 12.

The p-side electrode 16 is provided on the surface (surface of the upper portion) of the second semiconductor layer 13 as a first electrode. That is, the p-side electrode 16 is disposed on a region including the light-emitting layer 12. The n-side electrode 17 is provided on the surface of the first semiconductor layer 11 of the lower portion as a second electrode. In a wafer, that is, in the semiconductor layer 15, the p-side electrode 16 has a larger area than the n-side electrode 17. Therefore, the light-emitting area can be increased.

One of the side surface and the second main surface of the semiconductor layer 15 partially covers the insulating layers 14 and 18. The insulating layers 14 and 18 are also formed on the step portion between the p-side electrode 16 and the n-side electrode 17. The insulating layer 14 contains, for example, hafnium oxide or tantalum nitride. The insulating layer 18 contains, for example, a resin such as polyimide or the like, which is preferably on the patterned pores. Alternatively, the insulating layer 18 can also be based on yttrium oxide. The insulating layer 14 does not cover the p-side electrode 16 and the n-side electrode 17.

The P-side interconnect layer 21 is disposed on the surface 18c of the insulating layer 18 on the opposite side of the semiconductor layer 15 as the first inter-transport layer. The n-side interconnect layer 22 is disposed on the surface 18c of the insulating layer 18 on the opposite side of the semiconductor layer 15 as a second interconnect layer. The P-side interconnect layer 21 is also disposed in the first opening 18a, which is in communication with the p-side electrode 16 through the insulating layer 18, and the P-side interconnect layer 21 is connected to the p-side electrode 16. The n-side interconnect layer 22 is also disposed in the second opening 18b, which is in communication with the n-side electrode 17 through the insulating layer 18, and the n-side interconnect layer 22 is connected to the n-side electrode 17.

The P-side metal pillar 23 is provided on the surface of the P-side interconnect layer 21 opposite to the p-side electrode 16 as a first metal pillar. The n-side metal pillar 24 is disposed on the surface of the n-side interconnect layer 22 opposite to the n-side electrode 17 as a second metal pillar.

For example, the resin layer 25 covers the periphery of the P-side metal pillar 23, the periphery of the n-side metal pillar 24, the surface of the P-side interconnect layer 21, and the surface of the n-side interconnect layer 22 as the second insulating layer. The gap between the adjacent columns is filled with the resin layer 25. The respective end faces of the P-side metal pillar 23 and the n-side metal pillar 24 are exposed from the resin layer 25. The second insulating layer may be made of the same material as the first insulating layer (insulating layer 18).

The end face 21a of a portion of the P-side interconnect layer 21 is laterally exposed from the resin layer 25, and is also laterally exposed from the insulating layer 18. The end face 21a of a portion of the P-side interconnect layer 21 does not cover the insulating layer 18 and the resin layer 25. All of the end faces of the n-side interconnect layer 22 cover the resin layer 25 or the insulating layer 18.

The n-side interconnect layer 22 is connected to the n-side electrode 17, which is disposed on a portion of the semiconductor layer 15 that does not include the light-emitting layer 12. The area of the n-side interconnect layer 22 opposite to the n-side electrode 17 is larger than the area on the n-side electrode side. That is, the contact area between the n-side interconnect layer 22 and the n-side metal pillar 24 is larger than the contact area between the n-side interconnect layer 22 and the n-side electrode 17. The contact area between the P-side interconnect layer 21 and the P-side metal pillar 23 is larger than the contact area between the P-side interconnect layer 21 and the p-side electrode 16. Alternatively, the contact area between the P-side interconnect layer 21 and the P-side metal pillar 23 may be smaller than the contact area between the P-side interconnect layer 21 and the p-side electrode 16. A portion of the n-side interconnect layer 22 extends over the surface 18c of the insulating layer 18 to a position facing a portion below the light-emitting layer 12.

Thereby, the amplified extraction electrode can be formed via the n-side interconnection layer 22 by the n-side electrode 17 disposed on a small region of the semiconductor layer 15 that does not include the portion of the light-emitting layer 12, but is held by the larger light-emitting layer 12. High light output.

The first semiconductor layer 11 is electrically connected to the n-side metal pillar 24 via the n-side interconnect layer 22 and the n-side electrode 17. The second semiconductor layer 13 is electrically connected to the P-side metal pillar 23 via the p-side electrode 16 and the P-side interconnect layer 21.

A surface treatment film (for example, electroless plating such as a film of Ni or Au, pre-coated solder, etc.) may be formed on each of the P-side metal pillars 23 and the n-side metal pillars 24 to avoid rust.

The material of the n-side interconnect layer 22, the P-side interconnect layer 21, the n-side metal pillars 24, and the P-side metal pillars 23 may include copper, gold, nickel, silver, or the like. Among these materials, copper which has good thermal conductivity, high migration resistance, and excellent adhesion to an insulating material is preferably used.

The patterning of the plurality of thin openings 18a and 18b is performed on the insulating layer 18. Therefore, it is preferable to use a resin such as a polyimide having excellent patterning properties, for example, the insulating layer 18.

It is preferable to use a resin which can be formed into a thick layer at a low cost and which is suitable for reinforcing the n-side metal pillar 24 and the P-side metal pillar 23. Examples of the resin layer 25 may include an epoxy resin, a enamel resin, a fluororesin, or the like.

The phosphor layer 28 is disposed on the first main surface 15a of the semiconductor layer 15. The phosphor layer 28 can absorb light from the light-emitting layer 12 and emit wavelength-converted light. Therefore, the mixed light including the light from the light-emitting layer 12 and the wavelength-converted light from the fluorescent layer 28 can be externally emitted. For example, in the case where the light-emitting layer 12 is a nitrogen system, white light, light, or the like can be obtained as a mixed color light of the blue light from the light-emitting layer 12 and the yellow light of the wavelength-converted light from the fluorescent layer 28, for example. The phosphor layer 28 can comprise a plurality of phosphorous species (e.g., red phosphorus and green phosphorous).

The light emitted from the light-emitting layer 12 is mainly transmitted through the first semiconductor layer 11, the first main surface 15a, the transparent resin 27, and the fluorescent layer 28 to be emitted to the outside.

The underside of the P-side metal pillars 23 and the n-side metal pillars 24 may be bonded to circuitry formed on the mounting board or circuit board via a ball or ridge shaped terminal such as, for example, solder or other metal. Thereby, the semiconductor light emitting device can receive power.

The thickness of each of the n-side metal pillars 24 and the thickness of the P-side metal pillars 23 (the longitudinal thickness of FIG. 1) are larger than that of the semiconductor layer 15, the n-side electrode 17, the p-side electrode 16, the insulating layer 14, the insulating layer 18, and the n-side. The thickness of the stack of interconnect layer 22 and P-side interconnect layer 21. The aspect ratio (ratio of thickness to plane size) of the metal posts 23 and 24 is not limited to 1 or more, and the aspect ratio may be less than 1. The thickness of the metal posts 23 and 24 can be thinner than their planar dimensions.

According to the configuration of the present embodiment, even if the semiconductor layer 15 is thin, it can be formed thick by the n-side metal pillar 24, the P-side metal pillar 23, and the resin layer 25, maintaining mechanical strength. When the semiconductor light-emitting device is mounted on the mounting board, the n-side metal pillars 24 and the P-side metal pillars 23 can absorb and migrate the stress applied to the semiconductor layer 15 via the external terminals.

Figure 1 shows a wafer of a semiconductor light emitting device. In the present embodiment, as will be described later, all of the device elements shown in FIG. 1 are collectively formed in a wafer state, and the wafer is divided into a plurality of wafers.

Therefore, a miniaturized light-emitting device as small as the semiconductor layer 15 (for example, bare crystal) can be obtained.

When the diced semiconductor light-emitting device is mounted on the mounting board, the lower side of the P-side metal post 23 and the n-side metal post 24 exposed from the resin layer 25 correspond to individual polarities and are bonded to the circuit provided on the mounting board. Therefore, each of the P-side metal pillar 23 and the n-side metal pillar 24 must be different from each other. However, the side of the metal post covers the resin layer 25 and only the lower surface is exposed. Therefore, it is difficult to distinguish the two columns that are reduced.

In the present embodiment, the end surface 21a of a portion of the P-side interconnect layer 21 disposed under the P-side metal pillar 23 is exposed from the resin layer 25. In contrast, all of the end faces of the n-side interconnect layer 22 disposed under the n-side metal pillars 24 cover the resin layer 25 and are not exposed. Therefore, it is possible to easily distinguish which metal pillar P side or n side by recognizing the end surface 21a exposed to the side surface of the resin layer 25. As a result, the installation becomes easy, the productivity is increased, and the production cost can be reduced.

A method of fabricating a semiconductor light emitting device of the present embodiment will now be described with reference to Figs. 2A through 7.

As shown in FIG. 2A, the first semiconductor layer 11 is grown on the main surface of the substrate 10, and the light-emitting layer 13 including the second semiconductor layer 12 is grown thereon. In the case where the semiconductor layer 15 is made of, for example, a nickel semiconductor, the semiconductor layer 15 can be epitaxially formed on the sapphire substrate.

Next, as shown in FIG. 2B, the separation trench 9 penetrating the semiconductor layer 15 and reaching the substrate 10 is formed by, for example, reactive ion etching (RIE) using a photoresist (not shown) as a mask. As shown in FIG. 2C, the separation trenches 9 are formed, for example, in a lattice arrangement of the substrate 10 to separate the semiconductor layers 15 in multiple layers.

Next, a portion of the first semiconductor layer 11 is exposed by, for example, RIE using a photoresist (not shown), and a portion of the second semiconductor layer 13 including the light-emitting layer 12 is removed. Thereby, the upper portion 15b is formed on the second main surface side of the semiconductor layer 15. From the perspective of the substrate 10, the upper portion 15b is relatively located above. The lower portion 15c is formed on the second main surface side of the semiconductor layer 15. The lower portion 15c is located on the substrate 10 at a lower position than the upper portion 15b. The upper portion 15b includes the light emitting layer 12, and the lower portion 15c does not include the light emitting layer 12.

The substrate 10 includes a device region 61. A plurality of semiconductor layers 15 are formed on the device region 61. The peripheral zone 62 is outside the device area 61. 2A and 2B, 3A and 3B, 4A, 5A, 6A and 7 show a cross-sectional view of a region close to the outer peripheral region 62.

The insulating layer 14 shown in Fig. 3A covers the main surface of the substrate 10, the side surface of the semiconductor layer 15, and the second main surface. Next, after the insulating layer 14 is selectively removed, the p-side electrode 16 is formed on the surface of the upper portion 15b (the surface of the second semiconductor layer 13), and the n-side electrode 17 is formed on the surface of the lower portion 15c (the first semiconductor On the surface of layer 11). One of the p-side electrode 16 and the n-side electrode 17 may be formed before the other is formed, and alternatively, the p-side electrode 16 and the n-side electrode 17 may be simultaneously formed of the same material.

The insulating layer 18 shown in Fig. 3B covers all exposed surfaces of the substrate 10. Next, the insulating layer 18 is patterned by wet etching, and the first opening 18a and the second opening 18b are selectively formed on the insulating layer 18. The first opening 18a reaches the p-side electrode 16, and the second opening 18b reaches the n-side electrode 17. The separation trench 9 is filled with an insulating layer 18.

Next, as shown by the broken line in Fig. 3B, the continuous seed metal 19 is formed on the surface 18c of the insulating layer 18, and on the inner surfaces of the first opening 18a and the second opening 18b. And after selectively forming a plating resist (not shown) on the seed metal 19, copper plating is performed using the seed metal 19 as a current path.

Thereby, as shown in FIGS. 4A and 4B (top view of the entire wafer), the P-side interconnect layer 21 and the n-side interconnect layer 22 are selectively formed on the surface 18c of the insulating layer 18. The P-side interconnect layer 21 is also formed in the first opening 18a and is connected to the p-side electrode 16. The n-side interconnect layer 22 is also formed in the second opening 18b and is connected to the n-type electrode 17.

The face of the n-side transfer layer 22 on the opposite side of the n-type electrode 17 is formed in a pad shape having a larger area than the face connected to the n-side electrode 17. Similarly, the face of the P-side interconnect layer 21 on the opposite side of the p-side electrode 16 is formed in a pad shape having a larger area than the face connected to the p-side electrode 16.

The P-side interconnect layer 21 and the n-side interconnect layer 22 are simultaneously formed of a copper material by using an electroplating method. Moreover, during the plating of the P-side interconnect layer 21 and the n-side interconnect layer 22, the internal interconnect 65 and the peripheral interconnect 66 are simultaneously formed on the surface 18c of the insulating layer 18. The P-side interconnect layer 21, the n-side interconnect layer 22, the internal interconnect 65, and the peripheral interconnect 66 are made of the same material (e.g., copper) and have almost the same thickness. Also, the P-side interconnect layer 21 and the n-side interconnect layer 22 are not limited to being formed at the same time, and alternatively, one of the P-side interconnect layer 21 and the n-side interconnect layer 22 may be formed before the other.

The internal interconnect 65 is formed in a cutting region of the device region 61 in which the separation trench 9 is formed. Internal interconnects 65 are formed, for example, in a lattice configuration. The peripheral interconnect 66 is formed on the surface 18c of the insulating layer 18 in the peripheral region 62. The peripheral interconnects 66 are continuously formed along the circumference of the peripheral region 62 and surround the device region 61 in a continuous closed pattern.

The internal transfer 65 is integrally connected to a portion of the P-side interconnect layer 21. Moreover, the end of the internal interconnect 65 on the side of the peripheral region 62 is integrally connected to the peripheral interconnect 66. Therefore, the P-side interconnect layer 21 is electrically connected to the peripheral interconnect 66 via the internal interconnect 65. The n-side interconnect layer 22 is not connected to any of the P-side interconnect layer 21, the internal interconnect 65, and the peripheral interconnect 66.

Next, another plating resist (not shown) is selectively formed on the insulating layer 18 to fabricate a metal pillar, and copper plating is performed using the seed metal 19 as a current path.

Thereby, as shown in FIGS. 5A and 5B (top view of the entire wafer), the P-side metal pillars 23 are formed on the P-side interconnect layer 21, and the n-side metal pillars 24 are formed on the n-side interconnect layer 22 on. Again, metal is also formed on the peripheral interconnect 66 during electroplating. The P-side metal pillar 23, the n-side metal pillar 24, and the metal formed on the peripheral interconnect 66 are, for example, copper-containing.

During this plating, the internal interconnect 65 is covered with a plating resist to avoid plating, whereby the P-side metal pillars 23 are not disposed on the internal interconnect 65. Thus, the peripheral interconnect 66 becomes thicker than the inner interconnect 65. The thickness of the peripheral interconnect 66 is almost the same as the total thickness of the P-side interconnect layer 21 and the P-side metal pillar 23 or the total thickness of the n-side interconnect layer 22 and the n-side metal pillar 24. Since the relatively thick metal layer is continuously formed on the outer peripheral region 62 of the wafer in the circumferential direction, the mechanical strength of the wafer is increased, and the warpage of the wafer is suppressed. This makes it easy to carry out subsequent procedures.

After the electroplating, the P-side interconnect layer 21, the n-side interconnect layer 22, the P-side metal pillar 23, the n-side metal pillar 24, the internal interconnect 65, and the peripheral interconnect 66 are used as a mask to be exposed to the insulating layer 18. The seed metal 19 on the surface 18c is wet etched. Thereby, the electrical connection between the P side (the P side interconnect layer 21, the internal interconnect 65 and the peripheral interconnect 66) and the n-side interconnect layer 22 is separated via the seed metal 19.

Next, as shown in FIGS. 6A and 6B (top view of the entire wafer), the resin layer 25 is formed on the insulating layer 18. The resin layer 25 covers the P-side interconnect layer 21, the n-side interconnect layer 22, the P-side metal pillar 23, the n-side metal pillar 24, and the internal interconnect 65. The resin layer 25 is filled in the gap between the P-side metal pillar 23 and the n-side metal pillar 24, the gap between the P-side interconnection layer 21 and the n-side interconnection layer 22, and the gap between the n-side interconnection layer 22 and the internal interconnection 65. And a gap between the P-side interconnect layer 21 and the internal interconnect 65. The resin layer 25 also covers the interior of the peripheral interconnect 66. That is, the resin layer 25 covers a portion on the side of the device region 61 of the peripheral interconnect 66. The outer portion of the peripheral interconnect 66 is not covered with the resin layer 25 and exposed.

Moreover, after the formation of the resin layer 25, additional copper plating may be performed on the outside of the peripheral interconnection 66 exposed from the resin layer 25, whereby the peripheral interconnection 66 becomes as thick as shown in Fig. 8A. The increase in the thickness of the peripheral interconnect 66 enhances the mechanical strength of the wafer.

Next, the substrate 10 is removed. The substrate 10 is removed, for example, by using a laser lift-off method. Specifically, the laser light is irradiated from the back side of the substrate 10 toward the first semiconductor layer 11. The substrate 10 transmits laser light, and the laser light has a wavelength in the absorption region with respect to the first semiconductor layer 11.

When the laser light reaches the interface between the substrate 10 and the first semiconductor layer 11, the first semiconductor layer 11 close to the interface absorbs the energy of the laser light and decomposes. In the case where the first semiconductor layer 11 is made of a metal nitride such as GaN, the first semiconductor layer 11 is decomposed into Ga and nitrogen. By the decomposition reaction, a minute gap is formed between the substrate 10 and the first semiconductor layer 11, and the first semiconductor layer 11 is separated from the substrate 10.

By performing a plurality of times for each set area, laser light is irradiated throughout the entire wafer, and the substrate 10 is removed. Since the substrate 10 is removed from the first main surface 15a, the extraction efficiency of the emitted light from the semiconductor layer 15 can be improved.

Next, a voltage is applied to the exposed portions of the outer peripheral interconnects 66 on the first major surface 15a and the peripheral region 62 exposed by the removal of the substrate 10. Therefore, the light-emitting layer 12 emits light and measures the optical characteristics of light emitted from the first main surface 15a.

Specifically, as shown in FIG. 7, the surface of the peripheral interconnect 66 exposed from the resin layer 25 is supported by, for example, the ring-shaped measuring electrode 71. The outer peripheral surface of the insulating layer 14 exposed by the removal of the substrate 10 is pressed to the side of the measuring electrode 71 by, for example, a ring-shaped pressing member 72. Thereby, the surface of the peripheral interconnect 66 closely contacts the measuring electrode 71 and ensures good electrical contact between the peripheral interconnect 66 and the measuring electrode 71. A positive potential is applied to the peripheral interconnect 66 via the measuring electrode 71, and a ground potential is applied to the first main surface 15a of each of the semiconductor layers 15 via a probe (not shown) that is in contact with the first main surface 15a.

When GaN is decomposed by the above-described laser light irradiation, a gallium (Ga) film remains on the first main surface 15a. Gallium films often reduce the light output and, therefore, remove the gallium film. However, in the present embodiment, during the above measurement, the gallium film remains, and the negative side measuring electrode (probe) contacts the gallium film. Thereby, the contact resistance can be reduced more than the contact of the probe with GaN.

The peripheral interconnect 66 is connected to the P-side interconnect layer 21 via an internal interconnect 65. Therefore, by applying the above voltage, the holes from the side of the second semiconductor layer 13 and the electrons from the side of the first semiconductor layer 11 are incident on the light-emitting layer 12. Thereby, light generated by recombination of holes and electrons is emitted from the light-emitting layer 12. For example, the measurement wavelength is taken as the optical characteristic of the emitted light emitted from the first main surface 15a.

A hole is applied to the light-emitting layer 12, and a voltage is applied to the P-side metal pillar 23. This requires thinning the resin layer 25 and exposing the underside of the P-side metal pillar 23. However, thinning the resin layer 25 causes thinning of the entire wafer. Wafer processing becomes difficult and productivity is degraded.

In the present embodiment, as described above, by forming the peripheral interconnect 66 of the P-side interconnect layer 21 connected to the peripheral region 62, even if the P-side metal pillar 23 covers the resin layer 25, it can be interconnected via the peripheral interconnect 66. A voltage is applied to the P-side interconnect layer 21. Thereby, the wafer strength is ensured by the thick resin layer 25, measurement can be performed, and productivity reduction can be avoided.

After measuring the optical characteristics, the first major surface 15a is cleaned and the gallium film remaining on the first major surface 15a is removed. The first major surface 15a can be roughened to improve extraction efficiency.

Continuing, as shown in Fig. 1, the phosphor layer 28 is formed on the first major surface 15a. For example, a liquid transparent resin containing diffused phosphorus particles is applied by using a spin coating method, followed by curing to form a phosphor layer 28 by heat treatment. The transparent resin transmits the light emitted from the light-emitting layer 12 and the phosphor particles.

At this time, the thickness of the phosphor layer 28 can be adjusted in accordance with the above optical characteristic results. For example, the wavelength of light from the luminescent layer 12 between the wafer and the wafer may vary due to variations in wafer processing. In this case, the light of the desired color to be extracted can be controlled by adjusting the thickness of the phosphor layer 28 according to the measurement of the emission wavelength.

It is also possible to change the wavelength of the light emitted from each of the semiconductor layers 15 in a wafer, and in this case, the thickness of the phosphor layer 28 can be locally adjusted according to the wavelength of the light in each of the semiconductor layers 15. For example, a transparent material (transparent resin or glass) that transmits the emitted light may be formed on the first major surface 15a having an adjusted thickness corresponding to the wavelength of the light emitted from each of the semiconductor layers 15. Next, a phosphor layer 28 is formed on the entire wafer to have a polarized surface, and a portion where the germanium is formed with the transparent layer is thinner than a portion having no transparent layer. Also, the phosphor layer 28 is thinned by increasing the thickness of the transparent layer.

Next, after the phosphor layer 28 is formed, the resin layer 25 is polished to expose the underside of the P-side metal pillar 23 and the n-side metal pillar 24. The above procedure is performed in the wafer state.

Next, cutting is performed along the separation trench 9 (Figs. 2B and 2C) to cut the wafer. The substrate 10 has been removed during cutting. The separation trench 9 does not include a portion of the semiconductor layer 15. Further, the separation trench 9 is filled with a resin as the insulating layer 18. In this way, cutting can be easily performed and productivity can be improved. Moreover, damage to the semiconductor layer 15 can be avoided during the dicing. Further, after the dicing, the device structure in which the side surface of the semiconductor layer 15 covers the insulating layer 18 and is protected is obtained.

The inner interconnect 65 is formed in the dicing zone and has a dicing width that is almost the same as or wider than the width of the inner interconnect 65. In this case, the dicing wafer formation does not include internal interconnects 65. Moreover, since the P-side interconnect layer 21 is cut at a portion connected to the internal interconnect 65, the end face 21a of a portion of the P-side interconnect layer 21 is exposed from the resin layer 25. Thereby, the P-side interconnect layer 21 and the n-side interconnect layer 22 can be distinguished, wherein all of the end faces also cover the resin layer 25 after cutting.

As shown by the broken line in FIG. 4B, the diced semiconductor light-emitting device may have a single crystal structure including a semiconductor layer 15, or may have a plurality of semiconductor layers 15 as shown by the broken line in FIG. 4B. Crystal structure.

Since the above-described processes until the dicing are collectively performed in the wafer state, it is not necessary to perform electrode re-interconnection and packaging for each of the diced semiconductor light-emitting devices, and the manufacturing cost can be greatly reduced. In other words, electrode re-interconnection and packaging have been completed in the wafer state. It can also be inspected at the wafer stage. Therefore, productivity can be increased, thereby reducing costs.

In the wafer state, the P-side interconnect layer 21 of all the wafers need not be connected to the peripheral interconnect 66, and it is sufficient to connect at least one P-side interconnect layer 21 to the peripheral interconnect 66 for measuring the optical characteristics of the wafer.

As shown in FIG. 8B, the semiconductor layer 15 may remain on the outer peripheral region 62 of the substrate 10. The semiconductor layer 15 is provided as a dummy layer without electrodes, which does not function as a light-emitting device.

The semiconductor layer 15 remaining on the peripheral region 62 prevents the resin layer 25 from being irradiated by the laser light during the laser lift-off procedure. This can suppress cracking or the like of the resin layer 25 in the outer peripheral region 62.

The phosphor layer 28 may include a layer as described later, such as a red phosphor layer, a yellow phosphor layer, a green phosphor layer, and a blue phosphor layer.

The red phosphor layer may, for example, comprise CaAlSiN ₃ nitrogen-based phosphorus: Eu or SiAlON-based phosphorus.

Can be used when using SiAlON phosphorous

(M _1-x R _x ) _a1 AlSi _b1 O _c1 N _d1 composition formula (1)

Wherein M is at least one metal element not containing Si and Al, and preferably M may be at least one selected from the group consisting of Ca and Sr; R is a luminescent center element, R is preferably Eu; and x, a1, b1 C1 and d1 satisfy the following relationship: 0<x≦1, 0.6<a1<0.95, 2<b1<3.9, 0.25<c1<0.45, and 4<d1<5.7.

By using the SiAlON-based phosphorus represented by the chemical formula (1), the temperature characteristics of the wavelength conversion efficiency can be improved, and the efficiency in the high current density region can be further improved.

The yellow fluorescene layer may, for example, comprise (Sr, Ca, Ba) ₂ SiO ₄ : Eu citrate-based phosphorus.

The green fluorescent layer may, for example, contain (Ba, Ca, Mg) ₁₀ (PO ₄ ) ₆ : Cl ₂ : Eu halogenated phosphoric acid phosphorus or SiAlON phosphorus.

Can be used when using SiAlON phosphorous

(M _1-x R _x ) _a2 AlSi _b2 O _c2 N _d2 composition formula (2)

Wherein M is at least one metal element not containing Si and Al, and preferably M may be at least one selected from the group consisting of Ca and Sr; R is a luminescent center element, R is preferably Eu; and x, a2, b2 C2 and d2 satisfy the following relationship: 0<x≦1, 0.93<a2<1.3, 4.0<b2<5.8, 0.6<c2<1, and 6<d2<11.

By using the SiAlON-based phosphorus represented by the chemical formula (2), the temperature characteristics of the wavelength conversion efficiency can be improved, and the efficiency in the high current density region can be further improved.

The blue phosphor layer may, for example, comprise an oxide-based phosphorus of BaMgAl ₁₀ O ₁₇ :Eu.

While certain embodiments have been described, the embodiments are not intended to In fact, many of the novel embodiments described herein may be embodied in a variety of other forms. Also, various omissions, substitutions and changes may be made in the form of the embodiments described herein. The scope of the appended claims and the equivalents thereof are intended to cover the forms or modifications within the scope and spirit of the invention.

9. . . Separation trench

10. . . Substrate

11. . . First semiconductor layer

12. . . Second semiconductor layer

13. . . Luminous layer

14,18. . . Insulation

15. . . Semiconductor layer

15a. . . First major surface

15b. . . Upper department

15c. . . Lower part

16. . . P-side electrode

17. . . N-side electrode

18a. . . First opening

18b. . . Second opening

18c. . . surface

19. . . Seed metal

twenty one. . . P-side interconnect layer

21a. . . End face

twenty two. . . N-side interconnect layer

twenty three. . . P-side metal column

twenty four. . . N-side metal column

25. . . Resin layer

27. . . Transparent resin

28. . . Fluorescent layer

61. . . Device area

62. . . Peripheral area

65. . . Internal interconnection

66. . . Peripheral interconnection

71. . . Ring measuring electrode

72. . . Pressing piece

1 is a schematic cross-sectional view showing a semiconductor light emitting device of an embodiment;

2A to 7 are views showing a method of manufacturing a semiconductor light emitting device according to an embodiment;

8A and 8B are schematic cross-sectional views showing a semiconductor light emitting device of another embodiment.

11. . . First semiconductor layer

12. . . Second semiconductor layer

13. . . Luminous layer

14,18. . . Insulation

15. . . Semiconductor layer

15a. . . First major surface

16. . . P-side electrode

17. . . N-side electrode

18a. . . First opening

18b. . . Second opening

18c. . . surface

twenty one. . . P-side interconnect layer

21a. . . End face

twenty two. . . N-side interconnect layer

twenty three. . . P-side metal column

twenty four. . . N-side metal column

25. . . Resin layer

28. . . Fluorescent layer

Claims (20)

A semiconductor light emitting device comprising: a semiconductor layer comprising a first major surface, a second major surface opposite the first major surface, and a light emitting layer; a first electrode disposed in the region of the light emitting layer including the second major surface a second electrode disposed on the second major surface; a first insulating layer disposed on the second major surface of the semiconductor layer and including a first opening in communication with the first electrode and the second a second opening in which the electrode is connected; a first interconnect layer disposed in the first opening in the first insulating layer and connected to the first electrode; and a second interconnect layer disposed in the first insulating layer And in the second opening, and connected to the second electrode; a first metal pillar disposed on a surface of the first interconnect layer opposite to the first electrode; and a second metal pillar disposed in the second interconnect a second insulating layer disposed between the side of the first metal pillar and the side of the second metal pillar; and an edge of a portion of the first interconnect layer, Defacing laterally from the first insulating layer and the second insulating layer . The device of claim 1, wherein the second interconnect layer is covered by one of the first insulating layer and the second insulating layer. The device of claim 1, wherein the semiconductor light emitting device has a rectangular shape, and the edge of a portion of the first interconnect layer is exposed at a short side of the rectangle. The device of claim 1, wherein the semiconductor light emitting device has one side of the edge of the first interconnect layer exposed, the semiconductor layer, the first electrode, the second electrode, the first metal The post and the second metal post are not exposed on the side. The device of claim 1, wherein the side edge of the first interconnect layer is not exposed from the first insulating layer and the second insulating layer except for an exposed edge of a portion of the first interconnect layer. The device of claim 4, wherein the side edge of the first interconnect layer is not exposed from the first insulating layer and the second insulating layer except for an exposed edge of a portion of the first interconnect layer. A semiconductor light emitting device comprising: a plurality of semiconductor layers, each of the semiconductor layers comprising a first major surface, a second major surface opposite the first major surface, and a light emitting layer; a plurality of first electrodes, the first Each of the electrodes is disposed on a region of the light-emitting layer including the second major surface; a plurality of second electrodes, each of the second electrodes being disposed on the second major surface; the first insulating layer Provided on the second major surface of each of the semiconductor layers, and including a plurality of first openings in communication with the first electrodes and a plurality of second openings in communication with the second electrodes; First interconnect layers, each of the first interconnect layers being disposed The first openings in the first insulating layer are connected to the first electrodes; a plurality of second interconnect layers, each of the second interconnect layers being disposed in the first insulating layer And the second electrodes are connected to the second electrodes; a plurality of first metal pillars, each of the first metal pillars disposed on the first interconnect layer and the first electrodes a plurality of second metal pillars, each of the second metal pillars being disposed on a surface of the second interconnect layer opposite to the second electrodes; a second insulating layer disposed on Between the sides of the first metal posts and the sides of the second metal posts; and an inner interconnect disposed on the first insulating layer, the inner interconnect being connected to the side of the first interconnect layer The first interconnect layer on the edge. The device of claim 7, wherein the inner interconnect connects the first interconnect layer to another first interconnect layer disposed adjacent to the first interconnect layer. The device of claim 7, wherein the side edge of the first interconnect layer covers the first insulating layer or the second insulating layer except for contacting a side edge of the inner interconnect. The device of claim 7, wherein the second insulating layer is disposed between the second metal pillar and another second metal pillar disposed adjacent to the second metal pillar. The device of claim 7, further comprising: a peripheral interconnecting portion disposed outside the device region and a plurality of peripheral regions, a plurality of A semiconductor layer is disposed over the device region, the peripheral interconnect being connected to the first interconnect layer via the inner interconnect. The device of claim 11, wherein the peripheral interconnect continuously surrounds the device region. The device of claim 11, wherein the peripheral interconnect is connected to the first interconnect via the inner interconnect disposed in the cut region of the device region. The device of claim 13, wherein the peripheral interconnect is thicker than the inner interconnect. The device of claim 8, wherein the side edge of the first interconnect layer covers the first insulating layer or the second insulating layer except for contacting a side edge of the inner interconnect. A method of fabricating a semiconductor light emitting device, comprising: forming a first interconnect layer in a first opening provided in a first insulating layer, the first insulating layer being included in a stacked body, the stacked body comprising: a substrate, including a device region a semiconductor layer disposed in the device region of the substrate and including a first major surface, a second major surface opposite the first major surface, and a light-emitting layer; the first electrode disposed to include the first surface opposite the substrate a second electrode disposed on the second main surface; a first insulating layer disposed on the second main surface of the semiconductor layer and including the first electrode a first opening connected and a second opening communicating with the second electrode; Forming a peripheral interconnect on the outer peripheral region of the device region on the surface of the first insulating layer on which the first interconnect layer is disposed, the peripheral interconnect portion is connected to the first interconnect layer; forming a second mutual Laying in the second opening of the first insulating layer; forming a first metal pillar on a surface of the first interconnect layer opposite to the first electrode; forming a second metal pillar on the second interconnect layer a surface opposite to the second electrode; forming a second insulating layer between the first metal pillar and the second metal pillar by exposing at least a portion of the peripheral interconnect; forming the second insulating layer Thereafter, the substrate is removed; and when a voltage is applied between the peripheral interconnect and the first major surface exposed by removing the substrate, optical properties of light emerging from the first major surface are measured. The method of claim 16, wherein the step of removing the substrate comprises: irradiating the first major surface of the semiconductor layer containing the metal nitride with laser light, and decomposing the metal nitride into metal and nitrogen. Separating the substrate from the first main surface; measuring the optical characteristic by contacting a measuring electrode with a metal film remaining on the first main surface during decomposition of the metal nitride by laser irradiation; After measuring the optical characteristics, the metal film remaining on the first major surface is removed. For example, the method of claim 16 of the patent scope, wherein the second Measuring the optical characteristic when the edge layer covers the first metal pillar and the second metal pillar; and exposing the first metal pillar from the second insulating layer by thinning the second insulating layer after measuring the optical characteristic a face opposite the first interconnect layer and a face of the second metal post opposite the second interconnect layer. The method of claim 16, wherein the first interconnect layer and the second interconnect layer are simultaneously formed by electroplating; the first metal pillar and the second metal pillar are simultaneously formed by electroplating; The plating of the first and second interconnect layers and the plating of the first and second metal pillars are also formed by electroplating on the peripheral region. The method of claim 16, further comprising, after measuring the optical characteristic, forming a phosphor layer on the first major surface, and adjusting a thickness of the phosphor layer according to a measurement result of the optical characteristic.