JP2000244012A - Manufacture of group iii nitride compound semiconductor element - Google Patents

Manufacture of group iii nitride compound semiconductor element

Info

Publication number
JP2000244012A
JP2000244012A JP36531799A JP36531799A JP2000244012A JP 2000244012 A JP2000244012 A JP 2000244012A JP 36531799 A JP36531799 A JP 36531799A JP 36531799 A JP36531799 A JP 36531799A JP 2000244012 A JP2000244012 A JP 2000244012A
Authority
JP
Japan
Prior art keywords
layer
group iii
iii nitride
resin
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP36531799A
Other languages
Japanese (ja)
Inventor
Toshiya Kamimura
俊也 上村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Gosei Co Ltd
Original Assignee
Toyoda Gosei Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Gosei Co Ltd filed Critical Toyoda Gosei Co Ltd
Priority to JP36531799A priority Critical patent/JP2000244012A/en
Publication of JP2000244012A publication Critical patent/JP2000244012A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase the productivity of a semiconductor element made of a group III nitride compound semiconductor by applying and hardening sealing resin on the electrode formed side of a substrate and then dividing the substrate into individual elements. SOLUTION: A buffer layer 102 is formed on a sapphire substrate 101 and then a high carrier density n+ layer 103 and a light emitting layer 104 of a multiple quantum well structure are formed on the buffer layer 102. On the light emitting layer 104, P type layers 105, 106 are stacked. Then, a multiple thick film electrode 102 is formed by evaporation of metal on the P type layer 106 and a negative electrode 140 is formed on the n+ layer 103. Between the electrodes 120 and 140, an SiO2 protective film 130 is formed. In an element having a layer made of a group III nitride compound semiconductor formed on a substrate, a positive and a negative electrode are formed on the same side of the substrate and therefore sealing resin is only applied on one side where the positive and the negative electrode are formed. A group III nitride compound semiconductor element 100 has its electrode section resin-sealed and therefore the productivity of a flip-chip type semiconductor element having a high stability and durability can be increased.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、III族窒化物系化
合物半導体から成る半導体素子の製造方法に関する。特
に、フリップチップ型及びワイヤボンディング型の素子
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device comprising a group III nitride compound semiconductor. In particular, the present invention relates to a method for manufacturing a flip chip type and a wire bonding type element.

【0002】[0002]

【従来の技術】従来、例えば、フリップチップ型の素子
をIII族窒化物系化合物半導体から形成した後、外部部
材と接続、封止する工程は以下のようであった。図6に
その概略を示す。
2. Description of the Related Art Conventionally, for example, after a flip-chip type element is formed from a group III nitride compound semiconductor, a step of connecting and sealing with an external member has been performed as follows. FIG. 6 shows the outline.

【0003】即ち、図6の(a)に示すように、個別に
分割されたIII族窒化物系化合物半導体から成るフリッ
プチップ型の素子100は、図6の(b)のように基板
10上に素子層の上に形成された正電極11、負電極1
2がバンプ1が形成された外部部材(フレーム)6と金
ボール又はハンダ等により接合されて、樹脂3で封止さ
れている。あるいは、図6の(c)に示すように、正電
極11及び負電極12が間接部材(サブフレーム)20
上にパターニングされた電極21及び22にバンプ1に
より接合された後、その間接部材20が導電性接着剤4
により外部部材(フレーム)6に接合されている。そし
て、電極21及び22が外部部材(フレーム)6とワイ
ヤ5によりボンディングされている。その後、素子10
0、間接部材20、外部部材6とが樹脂3で封止されて
いる。尚、素子100と外部部材(フレーム)6との間
隙33、又は素子100と間接部材(サブフレーム)2
0との間隙33は非常に狭窄しており、通常の封止に用
いられている樹脂3では充分に充填されない場合が有る
ため、専用の樹脂(アンダーフィル剤)で予め間隙33
を封止した後に、通常の樹脂3で全体を封止するという
工夫も行われている。ワイヤボンディング型の素子も存
在するが、この素子においても、ウエハを各チップに分
割した後に、各個別のチップ毎に樹脂封止が行われてい
る。
That is, as shown in FIG. 6A, a flip-chip type device 100 made of an individually divided group III nitride compound semiconductor is mounted on a substrate 10 as shown in FIG. Positive electrode 11 and negative electrode 1 formed on the element layer
2 is joined to an external member (frame) 6 on which the bumps 1 are formed by a gold ball or solder, and is sealed with a resin 3. Alternatively, as shown in FIG. 6C, the positive electrode 11 and the negative electrode 12 are connected to an indirect member (subframe) 20.
After bonding to the patterned electrodes 21 and 22 by the bump 1, the indirect member 20 is connected to the conductive adhesive 4.
To the external member (frame) 6. The electrodes 21 and 22 are bonded to the external member (frame) 6 by wires 5. Then, the element 10
0, the indirect member 20, and the external member 6 are sealed with the resin 3. The gap 33 between the element 100 and the external member (frame) 6 or the element 100 and the indirect member (subframe) 2
Since the gap 33 with respect to 0 is very narrow and may not be sufficiently filled with the resin 3 used for normal sealing, the gap 33 may be previously filled with a special resin (underfill agent).
After the sealing, a method of sealing the entire structure with a normal resin 3 has also been devised. There is also a wire bonding type element, but in this element as well, after the wafer is divided into chips, resin sealing is performed for each individual chip.

【0004】[0004]

【発明が解決しようとする課題】上記の通り、従来のフ
リップチップ型やワイヤボンディング型の素子は、1つ
ずつ、樹脂のポッティングと加熱硬化処理を行ってい
た。このため、作業効率が悪いという問題点があった。
そこで本発明者らは、作業効率を上げる製造方法を開発
し、本発明を完成した。よって本発明の目的は、III族
窒化物系化合物半導体から成る半導体素子の製造方法の
生産性を向上させることである。また、他の目的は、樹
脂封止前と樹脂封止後にそれぞれ行われていた検査工程
を一本化かすることで、検査を簡便とすることである。
As described above, the conventional flip-chip type and wire bonding type elements have been subjected to resin potting and heat curing treatment one by one. For this reason, there was a problem that work efficiency was poor.
Therefore, the present inventors have developed a manufacturing method for improving work efficiency, and have completed the present invention. Therefore, an object of the present invention is to improve the productivity of a method for manufacturing a semiconductor device made of a group III nitride compound semiconductor. Another object is to simplify the inspection by unifying the inspection steps performed before and after the resin sealing, respectively.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
には、以下の手段が有効である。即ち、第1の手段は、
基板上にIII族窒化物系化合物半導体から成る層が積層
された半導体素子の製造方法において、個別の素子に分
割する前に、電極形成側に封止樹脂を塗布し、硬化させ
た後、個別の素子に分割することを特徴とする。これら
の半導体素子にはフリップチップ型又はワイヤボンディ
ング型の素子を用いることができる。フリップチップ型
の素子は、フェースダウンによりフレームに搭載する型
の素子であり、ワイヤボンディング型の層はフェースア
ップにより素子の電極とフレームとをワイヤボンディン
グにより接続する素子である。
The following means are effective in solving the above-mentioned problems. That is, the first means is:
In a method of manufacturing a semiconductor device in which a layer made of a group III nitride-based compound semiconductor is laminated on a substrate, before dividing into individual devices, a sealing resin is applied to an electrode forming side, cured, and then separated. Is divided into the elements. As these semiconductor elements, flip-chip type or wire bonding type elements can be used. The flip-chip type element is an element of a type mounted on a frame by face-down, and the wire bonding type layer is an element for connecting an electrode of the element and the frame by wire bonding by face-up.

【0006】また、第2の手段は、基板上にIII族窒化
物系化合物半導体から成る層が積層された半導体素子の
製造方法において、個別の素子に分割する前に、各電極
面上に金属柱又は電極パッドを形成し、金属柱又は電極
パッドの形成されていない部分に封止樹脂を塗布し、封
止樹脂を硬化させた後、個別の素子に分割することを特
徴とする。封止樹脂の塗布前に、金属柱や電極パッドを
形成するので、樹脂封止後の回路接続が容易となる。
尚、金属柱はフリップチップ型の素子の電極の上に形成
される金属体であり、電極パッドはワイヤボンディング
型の素子の電極の上に形成されるボンディングのための
台の意味であり、ランドとも呼ばれる。
A second means is that in a method of manufacturing a semiconductor device in which a layer made of a group III nitride compound semiconductor is laminated on a substrate, a metal is formed on each electrode surface before being divided into individual devices. A column or an electrode pad is formed, a sealing resin is applied to a portion where the metal column or the electrode pad is not formed, and after the sealing resin is cured, the device is divided into individual elements. Since the metal columns and the electrode pads are formed before the application of the sealing resin, circuit connection after the resin sealing is facilitated.
The metal pillar is a metal body formed on the electrode of the flip-chip type element, and the electrode pad is a stand for bonding formed on the electrode of the wire bonding type element. Also called.

【0007】また、第3の手段は、窓の形成された樹脂
マスクを形成し、窓に金属柱又は電極パッドを形成し、
その後に、樹脂マスクを除去した後、封止樹脂を塗布す
ることを特徴とする。この方法は、金属柱又は電極パッ
ドを形成するためのマスク樹脂と封止樹脂とを別にした
ものである。また、第4の手段は、封止樹脂は感光性樹
脂であり、塗布した後、フォトリソグラフにより所定の
位置に窓を形成し、この窓に金属柱又は電極パッドを形
成することを特徴とする。この方法は、金属柱又は電極
パッドを形成するためのマスク樹脂と封止樹脂とを同一
にして、マスク形成工程と封止工程とを同一とすること
で、工程を簡略化したものである。
A third means is to form a resin mask having a window, to form a metal column or an electrode pad in the window,
Thereafter, after removing the resin mask, a sealing resin is applied. In this method, a mask resin and a sealing resin for forming a metal pillar or an electrode pad are separated. The fourth means is that the sealing resin is a photosensitive resin, and after application, a window is formed at a predetermined position by photolithography, and a metal column or an electrode pad is formed in the window. . In this method, the mask resin and the sealing resin for forming the metal pillars or the electrode pads are made the same, and the mask forming step and the sealing step are made the same, thereby simplifying the steps.

【0008】また、第5の手段は、封止樹脂を一面に塗
布した後、金属柱又は電極パッドの上部における封止樹
脂を除去することで、金属柱又は電極パッドの上面を露
出させることを特徴とする。更に、第6の手段は、金属
柱又は電極パッドは、メッキにより形成されることを特
徴とする。
A fifth means is to expose the upper surface of the metal pillar or the electrode pad by applying the sealing resin on one surface and then removing the sealing resin above the metal pillar or the electrode pad. Features. Further, the sixth means is characterized in that the metal pillar or the electrode pad is formed by plating.

【0009】[0009]

【作用及び発明の効果】基板上にIII族窒化物系化合物
半導体から成る層が積層された素子は正負電極が基板面
に対して同一側に形成される。よって、封止樹脂も正負
電極が形成された側だけで良い。III族窒化物系化合物
半導体は安定性が高く、耐久性も高いので、この面から
も封止樹脂は電極が形成された側だけで良い。この封止
樹脂について、個別素子毎に塗布、硬化するのでなく、
封止樹脂の塗布、硬化が複数の素子に対して同時に行っ
ているので、生産性が向上し、又、検査工程も1基板に
関して1回にすることができる。例えばチップ型のフリ
ップチップ型発光ダイオード(LED)であれば、本発
明にかかる製造方法により分割された段階で最終製品と
なる。また、チップ型のワイヤボンディング型発光ダイ
オード(LED)であれば、本発明にかかる製造方法に
より分割された後にフレームに搭載して、露出している
電極パッドとフレームのランドとをワイヤでボンディン
グすれば良い。さらに、ワイヤボンディング型素子の場
合には、この後に、電極パッド、ワイヤを保護するため
に、フレームを含めて全体を樹脂封止すれば良い。ま
た、例えばランプ型のフリップチップ型又はワイヤボン
ディング型発光ダイオード(LED)とする場合は、フ
レームにマウント後、キャップを装着するだけで最終製
品とすることができる。このように、本発明により、大
幅な生産性の向上を図ることが可能となる。
In the device in which the layer made of the group III nitride compound semiconductor is laminated on the substrate, the positive and negative electrodes are formed on the same side with respect to the substrate surface. Therefore, the sealing resin may be provided only on the side where the positive and negative electrodes are formed. Since the group III nitride-based compound semiconductor has high stability and high durability, the sealing resin only needs to be provided on the side where the electrode is formed from this surface. Instead of applying and curing this sealing resin for each individual element,
Since the application and curing of the sealing resin are performed simultaneously on a plurality of elements, the productivity is improved, and the inspection process can be performed once for one substrate. For example, in the case of a chip-type flip-chip light emitting diode (LED), a final product is obtained at the stage of division by the manufacturing method according to the present invention. Further, in the case of a chip-type wire bonding type light emitting diode (LED), it is mounted on a frame after being divided by the manufacturing method according to the present invention, and the exposed electrode pads and the lands of the frame are bonded by wires. Good. Further, in the case of a wire bonding type element, the entire structure including the frame may be sealed with a resin in order to protect the electrode pads and wires. For example, in the case of a lamp type flip chip type or wire bonding type light emitting diode (LED), a final product can be obtained simply by mounting a cap after mounting on a frame. Thus, according to the present invention, it is possible to significantly improve productivity.

【0010】[0010]

【発明の実施の形態】以下、本発明を具体的な実施例に
基づいて説明する。なお、本発明は、以下の実施例に限
定されるものではない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. Note that the present invention is not limited to the following embodiments.

【0011】(第1実施例)図1に、本発明の具体的な
実施例に使用するフリップチップ型の半導体素子100
の模式的断面図を示す。半導体素子100は発光ダイオ
ードの例である。サファイヤ基板101の上には窒化ア
ルミニウム(AlN)から成る膜厚約200Åのバッファ層10
2が設けられ、その上にシリコン(Si)ドープのGaNから
成る膜厚約4.0μmの高キャリア濃度n+層103が形成
されている。そして、層103の上にGaNとGa0.8In0.2N
からなる多重量子井戸構造(MQW)の発光層104が
形成されている。発光層104の上にはマグネシウム(M
g)ドープのAl0.15Ga0.85Nから成る膜厚約600Åのp型層
105が形成されている。さらに、p型層105の上に
はマグネシウム(Mg)ドープのGaNから成る膜厚約1500Å
のp型層106が形成されている。
(First Embodiment) FIG. 1 shows a flip-chip type semiconductor device 100 used in a specific embodiment of the present invention.
1 shows a schematic sectional view of FIG. The semiconductor element 100 is an example of a light emitting diode. On the sapphire substrate 101, a buffer layer 10 of aluminum nitride (AlN) having a thickness of about 200 °
2, and a high carrier concentration n + layer 103 of about 4.0 μm in thickness made of silicon (Si) doped GaN is formed thereon. Then, GaN and Ga 0.8 In 0.2 N are formed on the layer 103.
A light emitting layer 104 having a multiple quantum well structure (MQW) made of Magnesium (M
g) A p-type layer 105 made of doped Al 0.15 Ga 0.85 N and having a thickness of about 600 ° is formed. Further, on the p-type layer 105, a film made of magnesium (Mg) -doped GaN having a thickness of about 1500
Is formed.

【0012】また、p型層106の上には金属蒸着によ
る多重厚膜電極120が、n+層103上には負電極1
40が形成されている。多重厚膜電極120は、p型層
106に接合する膜厚約0.3μmのロジウム(Rh)又は白金
(Pt)より成る第1金属層111、第1金属層111の上
部に形成される膜厚約1.2μmの金(Au)より成る第2金属
層112、更に第2金属層112の上部に形成される膜
厚約30Åのチタン(Ti)より成る第3金属層113の3層
構造である。一方、2層構造の負電極140は、膜厚約
175Åのバナジウム(V)層141と、膜厚約1.8μmのアル
ミニウム(Al)層142とを高キャリア濃度n+層103
の一部露出された部分の上から順次積層させることによ
り構成されている。
On the p-type layer 106, a multi-thick film electrode 120 formed by metal deposition is provided, and on the n + layer 103, a negative electrode 1 is provided.
40 are formed. The multi-thick film electrode 120 is made of rhodium (Rh) or platinum having a thickness of about 0.3 μm to be joined to the p-type layer 106.
A first metal layer 111 of (Pt), a second metal layer 112 of gold (Au) having a thickness of about 1.2 μm formed on the first metal layer 111, and further formed on the second metal layer 112. This is a three-layer structure of a third metal layer 113 made of titanium (Ti) having a thickness of about 30 ° to be formed. On the other hand, the negative electrode 140 having a two-layer structure has a thickness of about
And 175Å of vanadium (V) layer 141, a high carrier concentration and an aluminum (Al) layer 142 having a thickness of about 1.8 .mu.m n + layer 103
Are sequentially laminated on a part of the exposed part.

【0013】このように形成された多重厚膜正電極12
0と負電極140との間にはSiO2膜より成る保護膜13
0が形成されている。保護層130は、負電極140を
形成するために露出したn+層103から、エッチング
されて露出した、発光層104の側面、p型層105の
側面、及びp型層106の側面及び上面の一部、第1金
属層111、第2金属層112の側面、第3金属層11
3の上面の一部を覆っている。SiO2膜より成る保護膜1
30の第3金属層113を覆う部分の厚さは0.5μmであ
る。
The multiple thick film positive electrode 12 thus formed
Protective film 13 made of a SiO 2 film between
0 is formed. The protective layer 130 is formed by etching the side surface of the light emitting layer 104, the side surface of the p-type layer 105, and the side surface and the upper surface of the p-type layer 106, which are exposed by etching from the n + layer 103 exposed to form the negative electrode 140. Part of the first metal layer 111, side surfaces of the second metal layer 112, the third metal layer 11
3 is partially covered. Protective film 1 made of SiO 2 film
The thickness of the portion covering the third metal layer 113 is 0.5 μm.

【0014】このように形成されたフリップチップ型素
子100の、樹脂封止と個別分離(ダイシング)の工程
を図2に示す。図2の(a)に示す通り、フリップチッ
プ型素子100にマスクとして感光性の厚膜レジスト2
10を形成する。厚膜レジスト210は、フォトリソグ
ラフィによりメッキ膜成長部211を除去して、パター
ニングした。次に、無電解メッキにより、金属柱として
のニッケル(Ni)メッキ膜220を100μm形成した
(b)。この後、厚膜レジスト210を除去し(c)、
封止樹脂としてエポキシレジン230をニッケル(Ni)メ
ッキ膜220の高さまで封止した。この後、スクリーン
印刷にて、ハンダバンプ240をニッケル(Ni)メッキ膜
220上に形成した(e)。リフロー炉にてハンダバン
プの形状を整えた後、ダイシングして個々の樹脂封止さ
れたIII族窒化物系化合物半導体素子100とした
(f)。
FIG. 2 shows steps of resin sealing and individual separation (dicing) of the flip-chip type element 100 thus formed. As shown in FIG. 2A, a photosensitive thick film resist 2 is used as a mask for the flip-chip type device 100.
Form 10. The thick film resist 210 was patterned by removing the plated film growth portion 211 by photolithography. Next, a nickel (Ni) plating film 220 as a metal pillar was formed to 100 μm by electroless plating (b). Thereafter, the thick film resist 210 is removed (c).
Epoxy resin 230 was sealed to the height of nickel (Ni) plating film 220 as a sealing resin. Thereafter, solder bumps 240 were formed on the nickel (Ni) plating film 220 by screen printing (e). After adjusting the shape of the solder bumps in a reflow furnace, dicing was performed to obtain individual resin-sealed group III nitride compound semiconductor elements 100 (f).

【0015】このように製造されたIII族窒化物系化合
物半導体素子100は、電極部分は樹脂封止されてお
り、安定性及び耐久性の高いフリップチップ型の半導体
素子とすることができる。このように製造されたIII族
窒化物系化合物半導体素子100は封止樹脂の塗布、硬
化が複数の素子を同時に行えるので、生産性が向上し、
又、検査工程も1回にすることができた。このように、
本発明により、大幅な生産性の向上を図ることが可能と
なった。
The group III nitride-based compound semiconductor device 100 manufactured as described above can be a flip-chip type semiconductor device having high stability and durability because the electrode portion is sealed with resin. Since the group III nitride-based compound semiconductor device 100 thus manufactured can apply and cure a sealing resin to a plurality of devices at the same time, the productivity is improved,
Also, the number of inspection steps could be reduced to one. in this way,
According to the present invention, it has become possible to significantly improve productivity.

【0016】本発明の具体的一実施例にかかる上記の製
造方法の、封止樹脂としてのエポキシレジン230をニ
ッケル(Ni)メッキ膜220の高さまで封止する工程にお
いて、エポキシレジン230がニッケル(Ni)メッキ膜2
20の上面を一部或いは全部覆ってしまった場合の措置
としては、次のような手段を講じることができる。いず
れの手段も、エポキシレジン230の薄膜がニッケル(N
i)メッキ膜220の上面に固着しないことを多用したも
のである。 (1)洗浄工程を設け、ニッケル(Ni)メッキ膜220の
上面のエポキシレジン230の薄膜のみを溶媒で物理的
に取り除く。 (2)粘着テープ等を貼り、ニッケル(Ni)メッキ膜22
0の上面のエポキシレジン230の薄膜のみを剥離させ
る。 (3)加圧整形により、ニッケル(Ni)メッキ膜220の
上面のエポキシレジン230の薄膜のみを物理的に取り
除く。
In the above-described manufacturing method according to a specific embodiment of the present invention, in the step of sealing the epoxy resin 230 as a sealing resin to the height of the nickel (Ni) plating film 220, the epoxy resin 230 is made of nickel (Ni). Ni) plating film 2
The following measures can be taken as measures to be taken when part or all of the upper surface of 20 has been covered. In either case, the thin film of the epoxy resin 230 is made of nickel (N
i) It is often used not to adhere to the upper surface of the plating film 220. (1) A washing step is provided, and only the thin film of the epoxy resin 230 on the upper surface of the nickel (Ni) plating film 220 is physically removed with a solvent. (2) Adhesive tape or the like is applied, and nickel (Ni) plating film 22
Then, only the thin film of the epoxy resin 230 on the upper surface of No. 0 is removed. (3) Only the thin film of the epoxy resin 230 on the upper surface of the nickel (Ni) plating film 220 is physically removed by pressure shaping.

【0017】上記の実施例ではメッキ膜をニッケル(Ni)
としたが、銅(Cu)、金(Au)、銀(Ag)、スズ(Sn)その他、
導電性金属を使用することができる他、それらの合金或
いは積層膜として形成しても良い。また、上記の実施例
では封止樹脂としてエポキシレジンを使用したが、ポリ
エステルレジン、ポリイミドレジン、フェノールレジ
ン、ポリウレタンレジン、シリコーンレジン、その他、
熱硬化性樹脂を使用しても良い。また、上記の実施例で
はハンダバンプを形成するものを示したが、ワイヤボン
ディングを使用する半導体素子にも本発明は適用でき
る。
In the above embodiment, the plating film is made of nickel (Ni).
But copper (Cu), gold (Au), silver (Ag), tin (Sn), etc.
In addition to using a conductive metal, it may be formed as an alloy or a stacked film thereof. Further, in the above embodiments, epoxy resin was used as the sealing resin, but polyester resin, polyimide resin, phenolic resin, polyurethane resin, silicone resin, and others,
A thermosetting resin may be used. Further, in the above-described embodiment, an example in which a solder bump is formed has been described. However, the present invention can be applied to a semiconductor element using wire bonding.

【0018】第2実施例 第2実施例は、第1実施例において、金属柱としてのニ
ッケル(Ni)メッキ膜220を形成するためのマスクとし
て機能する厚膜レジスト210を封止樹脂としてのレジ
ン230と共通化したものである。第3図において、レ
ジン230は、感光性ポリイミッド樹脂から成る。各層
及び各電極が形成された基板10上に、一様に、感光性
ポリイミッド樹脂230をスピンコーティング法により
コートする。次に、180℃で30分加熱して、感光性
ポリイミッド樹脂230を半硬化させる。次に、ポジ型
レジストをコートし、90℃で2分間ベークする。次
に、マスクパターンを用いて露光する。現像液を用い
て、感光性ポリイミッド樹脂230の感光部分をエッチ
ングして除去する。感光性ポリイミッド樹脂230は感
光すると、アルカリ液に溶解する。アセトン又はIPA
等によりポジ型レジストのみを除去する。次に、残った
感光性ポリイミッド樹脂230を300℃で30分ベー
クして、完全に硬化させる。このようにして、図3
(a)に示すように、図2(a)と同様にメッキ膜成長
部211が形成される。次に、図3(b)に示すよう
に、無電界メッキによりにより、金属柱であるニッケル
(Ni)メッキ膜220が形成される。次に、図3(c)に
示すように、スクリーン印刷によりハンダバンプ220
が形成される。その後の工程は、第1実施例と同一であ
る。
Second Embodiment The second embodiment is different from the first embodiment in that a thick-film resist 210 functioning as a mask for forming a nickel (Ni) plating film 220 as a metal pillar is replaced with a resin as a sealing resin. 230 is common. In FIG. 3, the resin 230 is made of a photosensitive polyimide resin. The photosensitive polyimide resin 230 is uniformly coated on the substrate 10 on which each layer and each electrode are formed by a spin coating method. Next, the photosensitive polyimide resin 230 is semi-cured by heating at 180 ° C. for 30 minutes. Next, a positive resist is coated and baked at 90 ° C. for 2 minutes. Next, exposure is performed using a mask pattern. The photosensitive portion of the photosensitive polyimide resin 230 is etched away using a developer. When the photosensitive polyimide resin 230 is exposed to light, it is dissolved in an alkaline solution. Acetone or IPA
For example, only the positive resist is removed. Next, the remaining photosensitive polyimide resin 230 is baked at 300 ° C. for 30 minutes to be completely cured. Thus, FIG.
As shown in FIG. 2A, a plating film growth portion 211 is formed as in FIG. Next, as shown in FIG. 3B, nickel which is a metal pillar is formed by electroless plating.
The (Ni) plating film 220 is formed. Next, as shown in FIG. 3C, the solder bumps 220 are formed by screen printing.
Is formed. Subsequent steps are the same as in the first embodiment.

【0019】第3 実施例 第3 実施例は、ワイヤボンディング型の発光素子に関す
るものである。図4は、ワイヤボンディング型の発光素
子300の構造を示している。サファイヤ基板301の
上には窒化アルミニウム(AlN) から成る膜厚約200Å
のバッファ層302が設けられ、その上にシリコン(Si)
ドープのGaN から成る膜厚約4.0 μmの高キャリア濃度
+ 層303が形成されている。
Third Embodiment The third embodiment relates to a wire bonding type light emitting device. FIG. 4 shows a structure of a wire bonding type light emitting element 300. On the sapphire substrate 301, a film thickness of about 200 mm made of aluminum nitride (AlN)
Buffer layer 302 is provided, and silicon (Si)
A high carrier concentration n + layer 303 made of doped GaN and having a thickness of about 4.0 μm is formed.

【0020】この高キャリア濃度n+ 層303の上に
は、ノンドープのIn0.03Ga0.97N から成る膜厚約200
0Åの中間層304が形成されている。
On this high carrier concentration n + layer 303, a film thickness of about 200 made of non-doped In 0.03 Ga 0.97 N
A 0 ° intermediate layer 304 is formed.

【0021】そして、中間層304の上には、膜厚約1
50ÅのGaN から成るn型クラッド層305が積層さ
れ、更に、膜厚約30ÅのGa0.8In0.2N から成る井戸層3
61と、膜厚約70ÅのGaN から成るバリア層362とが
交互に積層された多重量子井戸(MQW) 構造のMQW活性
層360が形成されている。即ち、3層の井戸層361
と2層のバリア層362とが交互に積層されることによ
り、合計5層で2周期、膜厚約230ÅのMQW構造が
構成されている。
The intermediate layer 304 has a thickness of about 1
An n-type cladding layer 305 made of 50 ° GaN is laminated, and a well layer 3 made of Ga 0.8 In 0.2 N having a thickness of about 30 ° is further formed.
An MQW active layer 360 having a multiple quantum well (MQW) structure in which 61 and barrier layers 362 made of GaN having a thickness of about 70 ° are alternately stacked. That is, three well layers 361
By alternately laminating the two barrier layers 362, an MQW structure having a total of five layers and two periods and a film thickness of about 230 ° is formed.

【0022】このMQW活性層360の上には、膜厚約
140ÅのGaN から成るキャップ層307、及びp型Al
0.12Ga0.88N から成る膜厚約200Åのp型クラッド層
308が形成されている。さらに、p型クラッド層30
8の上にはp型Al0.05Ga0.95N から成る膜厚約600Å
のp型コンタクト層309が形成されている。
On the MQW active layer 360, a cap layer 307 made of GaN having a thickness of about 140 ° and a p-type Al
A p-type cladding layer 308 made of 0.12 Ga 0.88 N and having a thickness of about 200 ° is formed. Further, the p-type cladding layer 30
8 is made of p-type Al 0.05 Ga 0.95 N and has a thickness of about 600 °.
P-type contact layer 309 is formed.

【0023】又、p型コンタクト層309の上には金属
蒸着による透光性薄膜正電極310が、n+ 層303上
には負電極340が形成されている。透光性薄膜正電極
310は、p型コンタクト層309に接合する膜厚約15
Åのコバルト(Co)より成る薄膜正電極第1層311と、
Coに接合する膜厚約60Åの金(Au)より成る薄膜正電極第
2層312とで構成されている。
On the p-type contact layer 309, a translucent thin film positive electrode 310 is formed by metal evaporation, and on the n + layer 303, a negative electrode 340 is formed. The translucent thin film positive electrode 310 has a thickness of about 15 to be bonded to the p-type contact layer 309.
薄膜, a thin film positive electrode first layer 311 made of cobalt (Co);
And a second layer 312 of a thin film positive electrode made of gold (Au) having a thickness of about 60 ° bonded to Co.

【0024】厚膜正電極(パッド)320は、膜厚約1
75Åのバナジウム(V)より成る厚膜正電極第1層3
21と、膜厚約15000Åの金(Au)より成る厚膜
正電極第2層322と、膜厚約100Åのアルミニウム
(Al)より成る厚膜正電極第3層323とを透光性薄
膜正電極310の上から順次積層させることにより構成
されている。多層構造の負電極(パッド)340は、膜
厚約175Åのバナジウム(V) 層341と、膜厚約1.
8μmのアルミニウム(Al)層342とを高キャリア濃度
+ 層303の一部露出された部分の上から順次積層さ
せることにより構成されている。
The thick film positive electrode (pad) 320 has a thickness of about 1
Thick film positive electrode first layer 3 made of 75 ° vanadium (V)
21, a thick positive electrode second layer 322 made of gold (Au) having a thickness of about 15000 °, and a thick positive electrode third layer 323 made of aluminum (Al) having a thickness of about 100 °. It is configured by sequentially laminating the electrodes 310 from above. The negative electrode (pad) 340 having a multilayer structure includes a vanadium (V) layer 341 having a thickness of about 175 ° and a thickness of about 1.
An aluminum (Al) layer 342 having a thickness of 8 μm is sequentially laminated on a part of the high carrier concentration n + layer 303 which is partially exposed.

【0025】また、最上部には、SiO2 膜より成る保
護膜330が形成されており、また、サファイヤ基板3
01の底面に当たる反対側の最下部には、膜厚約500
0Åのアルミニウム(Al)より成る反射金属層350
が、金属蒸着により成膜されている。
Further, a protective film 330 made of a SiO 2 film is formed on the uppermost portion.
The lowermost part on the opposite side, which corresponds to the bottom surface of No. 01, has a thickness of about 500
Reflective metal layer 350 made of 0 ° aluminum (Al)
Is formed by metal evaporation.

【0026】上記の構造を有した複数の発光素子ユニッ
トを共通の基板301に形成した後、図5に示す工程が
実行される。即ち、図5(a)に示すように、封止樹脂
である感光性樹脂410を一様に塗布した後、各電極の
パッド部320、340の上だけを露光する。そして、
露光部をエッチング除去して、図5(a)のようにパッ
ド部上に窓411が形成される。この窓411により露
出したパッド320、340が外部のフレームに接続す
るためのワイヤボンディングに使用される。このように
樹脂で基板の表面を封止した後、図5(b)のように各
チップに分離される。
After a plurality of light emitting element units having the above structure are formed on a common substrate 301, the step shown in FIG. 5 is performed. That is, as shown in FIG. 5A, after uniformly applying a photosensitive resin 410 as a sealing resin, only the pad portions 320 and 340 of each electrode are exposed. And
The exposed portion is removed by etching, and a window 411 is formed on the pad portion as shown in FIG. The pads 320 and 340 exposed by the window 411 are used for wire bonding for connecting to an external frame. After sealing the surface of the substrate with the resin as described above, the substrate is separated into chips as shown in FIG.

【0027】尚、本実施例において、保護膜330は特
になくとも良い。即ち、封止用の感光性樹脂420がこ
の保護作用をする。又、本実施例では、パッド320、
340まで形成してから、樹脂封止しているが、パッド
320、340を形成する前に樹脂封止工程を行って良
い。その場合には、第1、2実施例におけるメッキ工程
によりパッド320、340が形成される。このワイヤ
ボンディング型の発光素子においても、第2実施例のよ
うにマスク樹脂と封止樹脂とを共通して、感光性樹脂に
よりマスク形成を兼ねて樹脂封止しても良い。
In this embodiment, the protective film 330 need not be particularly provided. That is, the photosensitive resin 420 for sealing performs this protective action. In this embodiment, the pad 320,
Although resin sealing is performed after forming up to 340, a resin sealing step may be performed before forming the pads 320 and 340. In that case, the pads 320 and 340 are formed by the plating process in the first and second embodiments. Also in this wire bonding type light emitting element, as in the second embodiment, a mask resin and a sealing resin may be used in common, and a photosensitive resin may be used to form a mask and resin sealing.

【0028】上記の実施例では、発光素子を封止するも
のを示したが、本発明は、III族窒化物系化合物半導体
を積層してなる任意の半導体素子に適用できる。又、本
発明は、III族窒化物系化合物半導体以外であっても、
安定性及び耐久性の高いフリップチップ型の半導体素子
であれば、任意の半導体からなるフリップチップ型の半
導体素子に適用できる。
In the above embodiment, the light emitting element is sealed. However, the present invention can be applied to any semiconductor element formed by laminating a group III nitride compound semiconductor. Further, the present invention, even other than the group III nitride compound semiconductor,
Any flip-chip type semiconductor element having high stability and durability can be applied to a flip-chip type semiconductor element made of any semiconductor.

【0029】上記の実施例における半導体素子の各層の
構成は、あくまでも各層を形成する際の物理的または化
学的構成であって、その後、より強固な密着性を得るた
めに、あるいは、コンタクト抵抗の値を下げる等の目的
で実施される例えば熱処理などのような物理的または化
学的処理によって各層間では、固溶あるいは化合物形成
が起きていることは言うまでもない。
The structure of each layer of the semiconductor element in the above embodiment is a physical or chemical structure at the time of forming each layer, and thereafter, in order to obtain stronger adhesion, or to reduce contact resistance. It goes without saying that a solid solution or a compound is formed between the layers by a physical or chemical treatment such as a heat treatment performed for the purpose of lowering the value.

【0030】なお、上記の実施例では、発光素子10
0、300の発光層104、360はMQW構造とした
が、SQW構造やホモ接合構造でもよい。また、本発明
の素子を形成するIII族窒化物系化合物半導体層は、任
意の混晶比の4元、3元、2元系のAlxGayIn1-x-yN(0
≦x≦1,0≦y≦1,0≦x+y≦1)としても良い。又、p型
不純物としては、マグネシウム(Mg)の他、ベリリウム(B
e)、亜鉛(Zn)等の2族元素を用いることができる。ま
た、正電極140、負電極120の積層構造や使用する
金属も任意である。又、本発明が応用できる半導体素子
としては、フリップチップ型、ワイヤボンディング型の
発光ダイオード、レーザダイオード、FET等のトラン
ジスタをあげることができる。
In the above embodiment, the light emitting element 10
Although the light emitting layers 104 and 360 of 0 and 300 have the MQW structure, they may have an SQW structure or a homojunction structure. Further, the group III nitride compound semiconductor layer forming the device of the present invention is composed of a ternary, ternary, or binary Al x Ga y In 1-xy N (0
≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). As the p-type impurity, besides magnesium (Mg), beryllium (B
e), a group 2 element such as zinc (Zn) can be used. Further, the laminated structure of the positive electrode 140 and the negative electrode 120 and the metal used are also arbitrary. Examples of the semiconductor element to which the present invention can be applied include flip-chip type and wire bonding type light emitting diodes, laser diodes, and transistors such as FETs.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の具体的な第1実施例のIII族窒化物系
化合物半導体素子の製造方法にかかる半導体素子の模式
的断面図。
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a method for manufacturing a group III nitride compound semiconductor device according to a first specific example of the present invention.

【図2】第1実施例の製造方法にかかる樹脂封止と分離
の一連の手順を示した模式図。
FIG. 2 is a schematic diagram showing a series of procedures of resin sealing and separation according to the manufacturing method of the first embodiment.

【図3】本発明の具体的な第2実施例の製造方法にかか
る樹脂封止と分離の一連の手順を示した模式図。
FIG. 3 is a schematic view showing a series of steps of resin sealing and separation according to a specific manufacturing method of a second embodiment of the present invention.

【図4】本発明の具体的な第3実施例のIII族窒化物系
化合物半導体素子の製造方法にかかる半導体素子の模式
的断面図。
FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a method of manufacturing a group III nitride compound semiconductor device according to a third specific example of the present invention.

【図5】第3実施例の製造方法にかかる樹脂封止と分離
の一連の手順を示した模式図。
FIG. 5 is a schematic diagram showing a series of steps of resin sealing and separation according to the manufacturing method of the third embodiment.

【図6】従来の樹脂封止の一連の手順を示した模式図。FIG. 6 is a schematic view showing a series of conventional resin sealing procedures.

【符号の説明】[Explanation of symbols]

100…III族窒化物系化合物半導体素子(半導体発光
素子) 101…サファイヤ基板 102…AlNバッファ層 103…n型のGaN層 104…発光層 105…p型のAlGaN層 106…p型のGaN層 111…第1薄膜金属層 112…第2薄膜金属層 120…厚膜正電極 130…保護膜 140…多層構造の負電極 220…金属柱(ニッケル(Ni)メッキ膜) 230…封止樹脂(レジン、感光性ポリイミッド樹脂) 300…発光素子 320…厚膜正電極(パッド) 340…負電極(パッド)
Reference Signs List 100: Group III nitride compound semiconductor element (semiconductor light emitting element) 101: Sapphire substrate 102: AlN buffer layer 103: n-type GaN layer 104: light emitting layer 105: p-type AlGaN layer 106: p-type GaN layer 111 ... first thin film metal layer 112 ... second thin film metal layer 120 ... thick film positive electrode 130 ... protective film 140 ... multilayer structure negative electrode 220 ... metal column (nickel (Ni) plating film) 230 ... sealing resin (resin, Photosensitive polyimide resin) 300: light emitting element 320: thick film positive electrode (pad) 340: negative electrode (pad)

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 基板上にIII族窒化物系化合物半導体か
ら成る層が積層された半導体素子の製造方法において、 個別の素子に分割する前に、電極形成側に封止樹脂を塗
布し、 前記封止樹脂を硬化させた後、個別の素子に分割するこ
とを特徴とする III族窒化物系化合物半導体素子の製造
方法。
In a method of manufacturing a semiconductor device in which a layer made of a group III nitride compound semiconductor is laminated on a substrate, a sealing resin is applied to an electrode forming side before dividing into individual devices, A method for producing a group III nitride compound semiconductor device, comprising dividing an individual device after curing a sealing resin.
【請求項2】 前記半導体素子はフリップチップ型の素
子であることを特徴とする請求項1に記載の III族窒化
物系化合物半導体素子の製造方法。
2. The method according to claim 1, wherein the semiconductor device is a flip-chip type device.
【請求項3】 前記半導体素子はワイヤボンディング型
の素子であることを特徴とする請求項1に記載の III族
窒化物系化合物半導体素子の製造方法。
3. The method according to claim 1, wherein the semiconductor device is a wire bonding type device.
【請求項4】 基板上にIII族窒化物系化合物半導体か
ら成る層が積層された半導体素子の製造方法において、 個別の素子に分割する前に、各電極面上に金属柱又は電
極パッドを形成し、 前記金属柱又は前記電極パッドの形成されていない部分
に封止樹脂を塗布し、 前記封止樹脂を硬化させた後、個別の素子に分割するこ
とを特徴とするIII族窒化物系化合物半導体素子の製造
方法。
4. A method for manufacturing a semiconductor device in which a layer made of a group III nitride compound semiconductor is laminated on a substrate, wherein a metal column or an electrode pad is formed on each electrode surface before being divided into individual devices. A group III nitride-based compound, wherein a sealing resin is applied to a portion where the metal pillar or the electrode pad is not formed, and after the sealing resin is cured, it is divided into individual elements. A method for manufacturing a semiconductor device.
【請求項5】 窓の形成された樹脂マスクを形成し、 前記窓に前記金属柱又は前記電極パッドを形成し、 その後に、前記樹脂マスクを除去した後、前記封止樹脂
を塗布することを特徴とする請求項4に記載のIII族窒
化物系化合物半導体素子の製造方法。
5. A method of forming a resin mask having a window, forming the metal column or the electrode pad in the window, removing the resin mask, and then applying the sealing resin. The method for producing a group III nitride-based compound semiconductor device according to claim 4, wherein:
【請求項6】 前記封止樹脂は感光性樹脂であり、塗布
した後、フォトリソグラフにより所定の位置に窓を形成
し、この窓に前記金属柱又は前記電極パッドを形成する
ことを特徴とする請求項4に記載のIII族窒化物系化合
物半導体素子の製造方法。
6. The method according to claim 1, wherein the sealing resin is a photosensitive resin, and after application, a window is formed at a predetermined position by photolithography, and the metal column or the electrode pad is formed in the window. A method for manufacturing a group III nitride-based compound semiconductor device according to claim 4.
【請求項7】 前記封止樹脂を一面に塗布した後、前記
金属柱又は電極パッドの上部における封止樹脂を除去す
ることで、前記金属柱又は電極パッドの上面を露出させ
ることを特徴とする請求項4に記載のIII族窒化物系化
合物半導体素子の製造方法。
7. The method according to claim 7, wherein after applying the sealing resin on one surface, the sealing resin on the metal pillar or the electrode pad is removed to expose the upper surface of the metal pillar or the electrode pad. A method for manufacturing a group III nitride-based compound semiconductor device according to claim 4.
【請求項8】 前記金属柱又は電極パッドは、メッキに
より形成されることを特徴とする請求項4乃至請求項6
のいずれか1項に記載のIII族窒化物系化合物半導体素
子の製造方法。
8. The metal column or the electrode pad is formed by plating.
3. The method for producing a group III nitride compound semiconductor device according to claim 1.
JP36531799A 1998-12-22 1999-12-22 Manufacture of group iii nitride compound semiconductor element Withdrawn JP2000244012A (en)

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