WO2013084155A1 - Forming thick metal layers on a semiconductor light emitting device - Google Patents

Forming thick metal layers on a semiconductor light emitting device Download PDF

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Publication number
WO2013084155A1
WO2013084155A1 PCT/IB2012/056969 IB2012056969W WO2013084155A1 WO 2013084155 A1 WO2013084155 A1 WO 2013084155A1 IB 2012056969 W IB2012056969 W IB 2012056969W WO 2013084155 A1 WO2013084155 A1 WO 2013084155A1
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WIPO (PCT)
Prior art keywords
metal
metal layers
type region
layers
photoresist
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PCT/IB2012/056969
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French (fr)
Inventor
Stefano Schiaffino
Salman Akram
Grigoriy Basin
Anneli Munkholm
Jipu Lei
Alexander H. NICKEL
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Koninklijke Philips Electronics N.V.
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Publication of WO2013084155A1 publication Critical patent/WO2013084155A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to forming thick metal layers on a semiconductor light emitting device.
  • LEDs light emitting diodes
  • RCLEDs resonant cavity light emitting diodes
  • VCSELs surface- emitting lasers
  • edge emitting lasers are among the most efficient light sources currently available.
  • Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as Ill-nitride materials.
  • Ill-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, Ill-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p- type regions.
  • Fig. 9 illustrates an LED including large area metal-to -metal interconnects, described in more detail in US 7,348,212.
  • the structure illustrated in Fig. 9 includes a flip chip light emitting device attached to a mount 70.
  • the flip chip device includes a substrate 73 attached to semiconductor device layers 74, which include at least one light emitting or active layer disposed between an n-type region and a p-type region.
  • N-type contact 71 and p-type contact 72 are electrically connected to the n- and p-type regions of semiconductor structure 74.
  • Thin metal layers 76a and 77a are formed on contacts 71 and 72, and thin metal layers 76b and 77b are formed on mount 70.
  • Thick ductile metal layers 78 and 79 are plated on either mount 70 or semiconductor structure 74, thus on regions 76b and 77b or on regions 76a and 77a.
  • Metal layers 78 and 79 are selected to be ductile, have high thermal and electrical conductivity, and be reasonably resistant to oxidation.
  • metal layers 78 and 79 may be Au, which has good thermal conductivity and is inexpensive; Cu, which has even better thermal conductivity than Au; Ni; or Al, which is less expensive than Au or Cu.
  • Metal layers 78 and 79 may be between one and 50 microns thick and are often between 5 and 20 microns thick.
  • a method includes providing a wafer of semiconductor devices.
  • the wafer includes a growth substrate, a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region, and first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region.
  • First and second metal layers are formed on the first and second metal contacts of each semiconductor device, respectively. The first and second metal layers are sufficiently thick to support the semiconductor structure during later processing.
  • a method includes providing a wafer of semiconductor devices.
  • the wafer includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region, and first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region.
  • First and second metal layers are formed on the first and second metal contacts of each semiconductor device, respectively. The first and second metal layers are thicker than 50 ⁇ .
  • Fig. 1 illustrates a semiconductor LED with two electrical pads.
  • Fig. 2 illustrates an adhesion layer and a seed layer formed over the electrical pads of the LED of Fig. 1.
  • Fig. 3 illustrates the structure of Fig. 2 after depositing and patterning a photoresist layer.
  • Fig. 4 illustrates the structure of Fig. 3 after forming a thick metal layer on the exposed portions of the seed layer.
  • Fig. 5 illustrates the structure of Fig. 4 after removing the photoresist and metal layers underlying the photoresist.
  • Fig. 6 illustrates the structure of Fig. 5 after depositing an electrical isolation layer.
  • Fig. 7 illustrates the structure of Fig. 6 after planarizing the electrical isolation layer.
  • Fig. 8 illustrates the structure of Fig. 7 after forming bonding pads.
  • Fig. 9 illustrates a prior art LED with thick, ductile metal interconnects. DETAILED DESCRIPTION
  • Fig. 1 illustrates a semiconductor light emitting device suitable for use in
  • the semiconductor light emitting device is a Ill-nitride LED that emits blue or UV light
  • semiconductor light emitting devices besides LEDs such as laser diodes and semiconductor light emitting devices made from other materials systems such as other III-V materials, Ill-phosphide, Ill-arsenide, II-VI materials, ZnO, or Si-based materials may be used.
  • the device illustrated in Fig. 1 may be formed by first growing a semiconductor structure on a growth substrate 40, as is known in the art.
  • the growth substrate may be any suitable substrate such as, for example, sapphire, SiC, Si, GaN, or composite substrates.
  • An n- type region may be grown first and may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, and/or layers designed to facilitate removal of the growth substrate, which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical, material, or electrical properties desirable for the light emitting region to efficiently emit light.
  • a light emitting or active region is grown over the n-type region.
  • suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers.
  • a p-type region may then be grown over the light emitting region.
  • the p-type region may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers.
  • the total thickness of all the semiconductor material in the device is less than 10 ⁇ in some embodiments and less than 6 ⁇ in some embodiments.
  • a p-contact metal is formed on the p-type region.
  • the p-contact metal may be reflective and may be a multi-layer stack.
  • the p-contact metal may include a layer for making ohmic contact to the p-type semiconductor material, a reflective metal layer, and a guard metal layer that prevents or reduces migration of the reflective metal.
  • the semiconductor structure is then patterned by standard photolithographic operations and etched to remove a portion of the entire thickness of the p-contact metal, a portion of the entire thickness of the p- type region, and a portion of the entire thickness of the light emitting region, to form at least one mesa which reveals a surface of the n-type region on which a metal n-contact is formed.
  • FIG. 1 One example of a device after etching the mesa and forming the n-contact is illustrated in Fig. 1.
  • multiple mesas are formed such that the n- contact metal is distributed across multiple regions 82A, 82B, and 82C.
  • N-contact metals 82A, 82B, and 82C are in direct contact with n-type region 46.
  • N-contacts 82A, 82B, and 82C may be point contacts that are surrounded by active region, p-type region, and p-contact material that extends outside the plane shown in the cross section of Fig. 1.
  • N-contacts 82A and 82B are separated by a structure including a portion 47 A of the light emitting region, a portion 48A of the p-type region, and a portion 80A of the p-contact metal.
  • N-contacts 82B and 82C are separated by a structure including a portion 47B of the light emitting region, a portion 48B of the p-type region, and a portion 80B of the p-contact metal.
  • the n-contacts 82A, 82B, and 82C and the p- contacts 80A and 80B may be electrically isolated by gaps 54A, 54B, 54C, and 54D, which may be filled with air, ambient gas, or a solid material such as a dielectric, an oxide of silicon, or a nitride of silicon.
  • the mesa and p- and n-contacts may be formed in any suitable manner. Forming the mesa and p- and n-contacts is well known to a person of skill in the art. In some embodiments, a single mesa, a single n-contact, and a single p-contact are formed. In embodiments with multiple mesas and multiple n- and p-contact regions, more or fewer mesas and n- and p-contacts than illustrated in Fig. 1 may be used. Also, though a single light emitting device is illustrated in Fig. 1 , it is to be understood that the device illustrated in Fig. 1 is formed on a wafer that includes many such devices. In the regions between individual devices on a wafer of devices, the semiconductor structure may be etched down to an insulating layer, which may be an insulating semiconductor layer that is part of the semiconductor structure, or the growth substrate.
  • an insulating layer which may be an insulating semiconductor layer that is part of the semiconductor structure, or
  • the p- and n-contacts may be redistributed by a stack of insulating layers and metals as is known in the art to form at least two large electrical pads 84 and 86.
  • One of the electrical pads 86 is electrically connected to the p-type region 48B of the semiconductor structure through p-contact 80B and the other of the electrical pads 84 is electrically connected to the n-type region 46 of the semiconductor structure through n-contact 82A.
  • Electrical pads may be any suitable material with suitable electrical and thermal conductivity, including, for example, aluminum, copper, gold, and alloys, formed by any suitable technique including, for example, sputtering, plating, or a combination of techniques.
  • Electrical pad 84 is electrically isolated from p-contact 80A by dielectric region 85.
  • Electrical pad 86 is electrically isolated from n-contacts 82B and 82C by dielectric regions 85 and 87.
  • Dielectric regions 85 and 87 may be any suitable dielectric such as silicone, epoxy, an oxide of silicon, or a nitride of silicon.
  • the electrical pads 84 and 86 are electrically isolated from each other by a gap 89 which may be filled with an insulating material such as a solid, a dielectric, an oxide of silicon, a nitride of silicon, air, or ambient gas.
  • the stack of layers used to redistribute the contacts and the electrical pads is well known in the art.
  • Such a stack may include multiple metal and dielectric layers not illustrated in the simplified view shown in Fig. 1.
  • the stack of insulating layers and metals to redistribute the p- and n-contacts is omitted and the thick metal layers are formed as described below directly on the p- and n-contacts.
  • the combination of pads 84 and 86 and dielectric layers 85 and 87 are arranged in different configurations.
  • One exemplary implementation connects n-contacts 82B and 82C to pad 84 and connects p-contact 80A to pad 86 without electrically connecting pad 84 to 86.
  • Such configurations require a three dimensional approach.
  • the semiconductor structure including the n-type region 46, the p-type region 48A, 48B, and the light emitting region 47 A, 47B, the n- and p-contacts 82A, 82B, 82C, 80A, 80B, and the dielectric layers 54A, 54B, 54C, 54D, 85, 87 illustrated in Fig. 1 are represented by structure 20 in Figs. 2, 3, 4, 5, 6, 7, and 8.
  • thick metal layers are formed on the electrical pads 84 and 86.
  • the thick metal layers may be formed on a wafer scale, before a wafer of devices is diced into individual or smaller groups of devices.
  • the thick metal layers may support the device structure of Fig. 1 after the wafer of devices is diced, and may support the device structure of Fig. 1 during removal of the growth substrate in some embodiments.
  • the thick metal regions may be formed as illustrated in Figs. 2, 3, 4, 5, 6, 7, and 8.
  • a base layer or layers is formed.
  • the base layer is a metal layer on which the thick metal layers (formed in Fig. 4) are deposited.
  • the base layer illustrated in Fig. 2 includes two layers.
  • the first layer is an adhesion layer 22, the material of which is selected for good adhesion to the electrical pads 84 and 86 and insulating material 89 on which it is formed. Examples of suitable materials for adhesion layer 22 include but are not limited to Ti, W, and alloys such as TiW.
  • a seed layer 24 is formed over adhesion layer 22. Seed layer 24 may be any suitable material on which the thick metal layers can be deposited.
  • seed layer 24 may be copper.
  • Adhesion layer 22 and seed layer 24 may be formed by any suitable technique including, for example, sputtering. Adhesion layer 22 and seed layer 24 need not be formed by the same technique. Adhesion layer 22 and seed layer 24 may be formed to cover the entire surface of the wafer of semiconductor devices.
  • a photoresist layer is formed over seed layer 24. Photoresist layer is then patterned such that the only remaining photoresist 26 overlies the region of the insulating material 89 between electrical pads 84 and 86 and regions between adjacent devices (not shown in Fig. 3). Photoresist 26 defines a region that will electrically isolate thick metal layers formed in electrical connection with electrical pads 84 and 86. Photoresist layer 26 is formed and patterned using materials and techniques that are known in the art.
  • thick metal layers 28 and 30 are formed over electrical pads 86 and 84, respectively.
  • Thick metal layers 28 and 30 may be any suitable metal such as, for example, copper, nickel, gold, palladium, nickel-copper alloy, or other alloys.
  • Thick metal layers 28 and 30 may be between 20 ⁇ and 500 ⁇ in some embodiments, between 30 ⁇ and 200 ⁇ in some embodiments, and between 50 ⁇ and 100 ⁇ in some embodiments.
  • Thick metal layers 28 and 30 support the semiconductor structure during later processing steps, in particular removal of the growth substrate, and provide a thermal pathway to conduct heat away from the semiconductor structure, which may improve the efficiency of the device.
  • photoresist 26 and the portion of adhesion layer 22 and seed layer 24 underlying photoresist layer 26 are removed by conventional photoresist stripping and etching techniques.
  • the two thick metal layers 28 and 30 are electrically isolated from each other by the gap 32 left by stripping resist 26 and removing portions of adhesion layer 22 and seed layer 24.
  • an electrically insulating material 33 is formed over the wafer.
  • the electrically insulating materials fills gaps 32 (portion 34 of electrically insulating material 33), the spaces between neighboring devices (portion 37 of electrically insulating material 33), and is optionally disposed over the tops of thick metal layers 28 and 30 (portion 35 of electrically insulating material 33).
  • Electrically insulating material 33 is selected to electrically isolate metal layers 28 and 30 and to have a coefficient of thermal expansion that is matched or is relatively close to that of the metal in thick metal layers 28 and 30.
  • electrically insulating material 33 may be epoxy or silicone in some embodiments.
  • Electrically insulating material 33 may be formed by any suitable technique, including, for example, spinning on or molding.
  • Fig. 7 illustrates an optional processing step, where any electrically insulating material 33 overlying thick metal layers 28 and 30 is removed.
  • Electrically insulating material 33 may be removed by any suitable technique, including, for example, microbead blasting, fly cutting, cutting with a blade, or chemical mechanical polishing.
  • the electrically insulating material 34 between thick metal layers 28 and 30 and between neighboring devices is not removed.
  • metal contact pads 36 and 38 are formed on thick metal layers 28 and 30, respectively.
  • metal contact pads 36 and 38 are suitable for connection to a structure such as a PC board, for example by refiow-soldering.
  • Contact pads 36 and 38 may be, for example, gold microbumps or solder.
  • Contact pads 36 and 38 may be formed by any suitable technique, including, for example, plating or screen printing.
  • the growth substrate 40 shown in Fig. 1 is removed by any suitable technique.
  • the growth substrate may be removed by laser lift-off, etching, mechanical techniques such as grinding, or a combination of techniques.
  • the growth substrate is sapphire and is removed by wafer-scale laser lift off. Since the sapphire substrate does not need to be thinned before removal and has not been diced, it can be reused as a growth substrate.
  • the surface of the semiconductor structure exposed by removing the growth substrate typically a surface of n-type region 46, may be optionally thinned and roughened, for example by photoelectrochemical etching. In some embodiments, all or part of the growth substrate remains part of the final device structure.
  • the wafer of devices is then diced into individual or groups of LEDs.
  • the wafer is diced in an area between devices, which is filled with insulating material 33 as described in Fig. 6. Accordingly, the sidewall of a device after dicing is a substantially vertical sidewall of insulating material 33, as illustrated in Fig. 8. Insulating material 33 surrounds each device in some embodiments.
  • One or more optional structures such as filters, lenses, dichroic materials, or wavelength converting materials may be formed over the LEDs, before or after dicing.
  • a wavelength converting material may be formed such that all or only a portion of the light emitted by the light emitting device and incident on the wavelength converting material may be converted by the wavelength converting material. Unconverted light emitted by the light emitting device may be part of the final spectrum of light, though it need not be.
  • Examples of common combinations include a blue-emitting LED combined with a yellow-emitting wavelength converting material, a blue-emitting LED combined with green- and red-emitting wavelength converting materials, a UV-emitting LED combined with blue- and yellow-emitting wavelength converting material, and a UV-emitting LED combined with blue-, green-, and red- emitting wavelength converting materials.
  • Wavelength converting materials emitting other colors of light may be added to tailor the spectrum of light emitted from the device.
  • the wavelength converting material may be conventional phosphor particles, organic
  • Any suitable phosphor may be used, including but not limited to garnet-based phosphors such as Y 3 Al 5 0i 2 :Ce (YAG), Lu 3 Al 5 0i 2 :Ce (LuAG), Y 3 Al 5 _ x Ga x Oi 2 :Ce (YAlGaG), (Bai_ x Sr x )Si0 3 :Eu (BOSE), and nitride- based phosphors such as (Ca,Sr)AlSiN 3 :Eu and (Ca,Sr,Ba) 2 Si 5 8 :Eu.
  • garnet-based phosphors such as Y 3 Al 5 0i 2 :Ce (YAG), Lu 3 Al 5 0i 2 :Ce (LuAG), Y 3 Al 5 _ x Ga x Oi 2 :Ce (YAlGaG), (Bai_ x Sr x )Si0 3 :Eu
  • the thick metal layers 28 and 30 provide mechanical support to the semiconductor structure, such that an additional mount such as a silicon or ceramic mount is not required.
  • Eliminating the mount may reduce the cost of the device and may simplify the processing required to form the device.

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Abstract

A method according to embodiments of the invention includes providing a wafer of semiconductor devices. The wafer includes a growth substrate (40 ), a semiconductor structure including a light emitting layer (47) sandwiched between an n-type region (46) and a p-type region (48), and first and second metal contacts (80,82) for each semiconductor device, wherein each first metal contact (82) is in direct contact with the n-type region and each second metal contact (80) is in direct contact with the p-type region. First and second metal layers (28, 30) are formed on the first and second metal contacts of each semiconductor device, respectively. The first and second metal layers are sufficiently thick to support the semiconductor structure during later processing.

Description

FORMING THICK METAL LAYERS ON A
SEMICONDUCTOR LIGHT EMITTING DEVICE
BACKGROUND FIELD OF INVENTION
[0001] The present invention relates to forming thick metal layers on a semiconductor light emitting device.
DESCRIPTION OF RELATED ART
[0002] Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes such as surface- emitting lasers (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as Ill-nitride materials. Typically, Ill-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, Ill-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p- type regions.
[0003] Fig. 9 illustrates an LED including large area metal-to -metal interconnects, described in more detail in US 7,348,212. The structure illustrated in Fig. 9 includes a flip chip light emitting device attached to a mount 70. The flip chip device includes a substrate 73 attached to semiconductor device layers 74, which include at least one light emitting or active layer disposed between an n-type region and a p-type region. N-type contact 71 and p-type contact 72 are electrically connected to the n- and p-type regions of semiconductor structure 74. Thin metal layers 76a and 77a are formed on contacts 71 and 72, and thin metal layers 76b and 77b are formed on mount 70. Thick ductile metal layers 78 and 79 are plated on either mount 70 or semiconductor structure 74, thus on regions 76b and 77b or on regions 76a and 77a. Metal layers 78 and 79 are selected to be ductile, have high thermal and electrical conductivity, and be reasonably resistant to oxidation. For example, metal layers 78 and 79 may be Au, which has good thermal conductivity and is inexpensive; Cu, which has even better thermal conductivity than Au; Ni; or Al, which is less expensive than Au or Cu. Metal layers 78 and 79 may be between one and 50 microns thick and are often between 5 and 20 microns thick.
SUMMARY
[0004] It is an object of the invention to provide a semiconductor device including thick metal layers that mechanically support the semiconductor device such that a mount is not required to support the semiconductor device.
[0005] A method according to embodiments of the invention includes providing a wafer of semiconductor devices. The wafer includes a growth substrate, a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region, and first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. First and second metal layers are formed on the first and second metal contacts of each semiconductor device, respectively. The first and second metal layers are sufficiently thick to support the semiconductor structure during later processing.
[0006] A method according to embodiments of the invention includes providing a wafer of semiconductor devices. The wafer includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region, and first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. First and second metal layers are formed on the first and second metal contacts of each semiconductor device, respectively. The first and second metal layers are thicker than 50 μιη.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Fig. 1 illustrates a semiconductor LED with two electrical pads.
[0008] Fig. 2 illustrates an adhesion layer and a seed layer formed over the electrical pads of the LED of Fig. 1.
[0009] Fig. 3 illustrates the structure of Fig. 2 after depositing and patterning a photoresist layer.
[0010] Fig. 4 illustrates the structure of Fig. 3 after forming a thick metal layer on the exposed portions of the seed layer.
[0011] Fig. 5 illustrates the structure of Fig. 4 after removing the photoresist and metal layers underlying the photoresist.
[0012] Fig. 6 illustrates the structure of Fig. 5 after depositing an electrical isolation layer. [0013] Fig. 7 illustrates the structure of Fig. 6 after planarizing the electrical isolation layer. [0014] Fig. 8 illustrates the structure of Fig. 7 after forming bonding pads. [0015] Fig. 9 illustrates a prior art LED with thick, ductile metal interconnects. DETAILED DESCRIPTION
[0016] Fig. 1 illustrates a semiconductor light emitting device suitable for use in
embodiments of the invention. Though in the discussion below the semiconductor light emitting device is a Ill-nitride LED that emits blue or UV light, semiconductor light emitting devices besides LEDs such as laser diodes and semiconductor light emitting devices made from other materials systems such as other III-V materials, Ill-phosphide, Ill-arsenide, II-VI materials, ZnO, or Si-based materials may be used.
[0017] The device illustrated in Fig. 1 may be formed by first growing a semiconductor structure on a growth substrate 40, as is known in the art. The growth substrate may be any suitable substrate such as, for example, sapphire, SiC, Si, GaN, or composite substrates. An n- type region may be grown first and may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, and/or layers designed to facilitate removal of the growth substrate, which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical, material, or electrical properties desirable for the light emitting region to efficiently emit light. A light emitting or active region is grown over the n-type region. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers. A p-type region may then be grown over the light emitting region. Like the n- type region, the p-type region may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers. The total thickness of all the semiconductor material in the device is less than 10 μπι in some embodiments and less than 6 μπι in some embodiments.
[0018] A p-contact metal is formed on the p-type region. The p-contact metal may be reflective and may be a multi-layer stack. For example, the p-contact metal may include a layer for making ohmic contact to the p-type semiconductor material, a reflective metal layer, and a guard metal layer that prevents or reduces migration of the reflective metal. The semiconductor structure is then patterned by standard photolithographic operations and etched to remove a portion of the entire thickness of the p-contact metal, a portion of the entire thickness of the p- type region, and a portion of the entire thickness of the light emitting region, to form at least one mesa which reveals a surface of the n-type region on which a metal n-contact is formed.
[0019] One example of a device after etching the mesa and forming the n-contact is illustrated in Fig. 1. In the device illustrated in Fig. 1 , multiple mesas are formed such that the n- contact metal is distributed across multiple regions 82A, 82B, and 82C. N-contact metals 82A, 82B, and 82C are in direct contact with n-type region 46. N-contacts 82A, 82B, and 82C may be point contacts that are surrounded by active region, p-type region, and p-contact material that extends outside the plane shown in the cross section of Fig. 1. N-contacts 82A and 82B are separated by a structure including a portion 47 A of the light emitting region, a portion 48A of the p-type region, and a portion 80A of the p-contact metal. N-contacts 82B and 82C are separated by a structure including a portion 47B of the light emitting region, a portion 48B of the p-type region, and a portion 80B of the p-contact metal. The n-contacts 82A, 82B, and 82C and the p- contacts 80A and 80B may be electrically isolated by gaps 54A, 54B, 54C, and 54D, which may be filled with air, ambient gas, or a solid material such as a dielectric, an oxide of silicon, or a nitride of silicon.
[0020] The mesa and p- and n-contacts may be formed in any suitable manner. Forming the mesa and p- and n-contacts is well known to a person of skill in the art. In some embodiments, a single mesa, a single n-contact, and a single p-contact are formed. In embodiments with multiple mesas and multiple n- and p-contact regions, more or fewer mesas and n- and p-contacts than illustrated in Fig. 1 may be used. Also, though a single light emitting device is illustrated in Fig. 1 , it is to be understood that the device illustrated in Fig. 1 is formed on a wafer that includes many such devices. In the regions between individual devices on a wafer of devices, the semiconductor structure may be etched down to an insulating layer, which may be an insulating semiconductor layer that is part of the semiconductor structure, or the growth substrate.
[0021] The p- and n-contacts may be redistributed by a stack of insulating layers and metals as is known in the art to form at least two large electrical pads 84 and 86. One of the electrical pads 86 is electrically connected to the p-type region 48B of the semiconductor structure through p-contact 80B and the other of the electrical pads 84 is electrically connected to the n-type region 46 of the semiconductor structure through n-contact 82A. Electrical pads may be any suitable material with suitable electrical and thermal conductivity, including, for example, aluminum, copper, gold, and alloys, formed by any suitable technique including, for example, sputtering, plating, or a combination of techniques. Electrical pad 84 is electrically isolated from p-contact 80A by dielectric region 85. Electrical pad 86 is electrically isolated from n-contacts 82B and 82C by dielectric regions 85 and 87. Dielectric regions 85 and 87 may be any suitable dielectric such as silicone, epoxy, an oxide of silicon, or a nitride of silicon. The electrical pads 84 and 86 are electrically isolated from each other by a gap 89 which may be filled with an insulating material such as a solid, a dielectric, an oxide of silicon, a nitride of silicon, air, or ambient gas. The stack of layers used to redistribute the contacts and the electrical pads is well known in the art. Such a stack may include multiple metal and dielectric layers not illustrated in the simplified view shown in Fig. 1. In some embodiments, the stack of insulating layers and metals to redistribute the p- and n-contacts is omitted and the thick metal layers are formed as described below directly on the p- and n-contacts. In some embodiments the combination of pads 84 and 86 and dielectric layers 85 and 87 are arranged in different configurations. One exemplary implementation connects n-contacts 82B and 82C to pad 84 and connects p-contact 80A to pad 86 without electrically connecting pad 84 to 86. Such configurations require a three dimensional approach.
[0022] The semiconductor structure including the n-type region 46, the p-type region 48A, 48B, and the light emitting region 47 A, 47B, the n- and p-contacts 82A, 82B, 82C, 80A, 80B, and the dielectric layers 54A, 54B, 54C, 54D, 85, 87 illustrated in Fig. 1 are represented by structure 20 in Figs. 2, 3, 4, 5, 6, 7, and 8.
[0023] In embodiments of the invention, thick metal layers are formed on the electrical pads 84 and 86. The thick metal layers may be formed on a wafer scale, before a wafer of devices is diced into individual or smaller groups of devices. The thick metal layers may support the device structure of Fig. 1 after the wafer of devices is diced, and may support the device structure of Fig. 1 during removal of the growth substrate in some embodiments.
[0024] The thick metal regions may be formed as illustrated in Figs. 2, 3, 4, 5, 6, 7, and 8. In Fig. 2, a base layer or layers is formed. The base layer is a metal layer on which the thick metal layers (formed in Fig. 4) are deposited. The base layer illustrated in Fig. 2 includes two layers. The first layer is an adhesion layer 22, the material of which is selected for good adhesion to the electrical pads 84 and 86 and insulating material 89 on which it is formed. Examples of suitable materials for adhesion layer 22 include but are not limited to Ti, W, and alloys such as TiW. A seed layer 24 is formed over adhesion layer 22. Seed layer 24 may be any suitable material on which the thick metal layers can be deposited. For example, if the thick metal regions are copper formed by plating, seed layer 24 may be copper. Adhesion layer 22 and seed layer 24 may be formed by any suitable technique including, for example, sputtering. Adhesion layer 22 and seed layer 24 need not be formed by the same technique. Adhesion layer 22 and seed layer 24 may be formed to cover the entire surface of the wafer of semiconductor devices.
[0025] In Fig. 3, a photoresist layer is formed over seed layer 24. Photoresist layer is then patterned such that the only remaining photoresist 26 overlies the region of the insulating material 89 between electrical pads 84 and 86 and regions between adjacent devices (not shown in Fig. 3). Photoresist 26 defines a region that will electrically isolate thick metal layers formed in electrical connection with electrical pads 84 and 86. Photoresist layer 26 is formed and patterned using materials and techniques that are known in the art.
[0026] In Fig. 4, thick metal layers 28 and 30 are formed over electrical pads 86 and 84, respectively. Thick metal layers 28 and 30 may be any suitable metal such as, for example, copper, nickel, gold, palladium, nickel-copper alloy, or other alloys. Thick metal layers 28 and 30 may be between 20 μηι and 500 μηι in some embodiments, between 30 μηι and 200 μηι in some embodiments, and between 50 μηι and 100 μηι in some embodiments. Thick metal layers 28 and 30 support the semiconductor structure during later processing steps, in particular removal of the growth substrate, and provide a thermal pathway to conduct heat away from the semiconductor structure, which may improve the efficiency of the device.
[0027] In Fig. 5, photoresist 26 and the portion of adhesion layer 22 and seed layer 24 underlying photoresist layer 26 are removed by conventional photoresist stripping and etching techniques. The two thick metal layers 28 and 30 are electrically isolated from each other by the gap 32 left by stripping resist 26 and removing portions of adhesion layer 22 and seed layer 24.
[0028] In Fig. 6, an electrically insulating material 33 is formed over the wafer. The electrically insulating materials fills gaps 32 (portion 34 of electrically insulating material 33), the spaces between neighboring devices (portion 37 of electrically insulating material 33), and is optionally disposed over the tops of thick metal layers 28 and 30 (portion 35 of electrically insulating material 33). Electrically insulating material 33 is selected to electrically isolate metal layers 28 and 30 and to have a coefficient of thermal expansion that is matched or is relatively close to that of the metal in thick metal layers 28 and 30. For example, electrically insulating material 33 may be epoxy or silicone in some embodiments. Electrically insulating material 33 may be formed by any suitable technique, including, for example, spinning on or molding. [0029] Fig. 7 illustrates an optional processing step, where any electrically insulating material 33 overlying thick metal layers 28 and 30 is removed. Electrically insulating material 33 may be removed by any suitable technique, including, for example, microbead blasting, fly cutting, cutting with a blade, or chemical mechanical polishing. The electrically insulating material 34 between thick metal layers 28 and 30 and between neighboring devices is not removed.
[0030] In Fig. 8, metal contact pads 36 and 38 are formed on thick metal layers 28 and 30, respectively. In some embodiments, metal contact pads 36 and 38 are suitable for connection to a structure such as a PC board, for example by refiow-soldering. Contact pads 36 and 38 may be, for example, gold microbumps or solder. Contact pads 36 and 38 may be formed by any suitable technique, including, for example, plating or screen printing.
[0031] In some embodiments, the growth substrate 40 shown in Fig. 1 is removed by any suitable technique. For example, the growth substrate may be removed by laser lift-off, etching, mechanical techniques such as grinding, or a combination of techniques. In some embodiments, the growth substrate is sapphire and is removed by wafer-scale laser lift off. Since the sapphire substrate does not need to be thinned before removal and has not been diced, it can be reused as a growth substrate. The surface of the semiconductor structure exposed by removing the growth substrate, typically a surface of n-type region 46, may be optionally thinned and roughened, for example by photoelectrochemical etching. In some embodiments, all or part of the growth substrate remains part of the final device structure.
[0032] The wafer of devices is then diced into individual or groups of LEDs. The wafer is diced in an area between devices, which is filled with insulating material 33 as described in Fig. 6. Accordingly, the sidewall of a device after dicing is a substantially vertical sidewall of insulating material 33, as illustrated in Fig. 8. Insulating material 33 surrounds each device in some embodiments.
[0033] One or more optional structures such as filters, lenses, dichroic materials, or wavelength converting materials may be formed over the LEDs, before or after dicing. A wavelength converting material may be formed such that all or only a portion of the light emitted by the light emitting device and incident on the wavelength converting material may be converted by the wavelength converting material. Unconverted light emitted by the light emitting device may be part of the final spectrum of light, though it need not be. Examples of common combinations include a blue-emitting LED combined with a yellow-emitting wavelength converting material, a blue-emitting LED combined with green- and red-emitting wavelength converting materials, a UV-emitting LED combined with blue- and yellow-emitting wavelength converting material, and a UV-emitting LED combined with blue-, green-, and red- emitting wavelength converting materials. Wavelength converting materials emitting other colors of light may be added to tailor the spectrum of light emitted from the device. The wavelength converting material may be conventional phosphor particles, organic
semiconductors, II- VI or III-V semiconductors, II- VI or III-V semiconductor quantum dots or nanocrystals, dyes, polymers, or materials such as GaN that luminesce. Any suitable phosphor may be used, including but not limited to garnet-based phosphors such as Y3Al50i2:Ce (YAG), Lu3Al50i2:Ce (LuAG), Y3Al5_xGaxOi2:Ce (YAlGaG), (Bai_xSrx)Si03:Eu (BOSE), and nitride- based phosphors such as (Ca,Sr)AlSiN3:Eu and (Ca,Sr,Ba)2Si5 8:Eu.
[0034] The thick metal layers 28 and 30 provide mechanical support to the semiconductor structure, such that an additional mount such as a silicon or ceramic mount is not required.
Eliminating the mount may reduce the cost of the device and may simplify the processing required to form the device.
[0035] Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.

Claims

CLAIMS What is being claimed is:
1. A method comprising:
providing a wafer of semiconductor devices, the wafer comprising:
a growth substrate;
a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region; and
first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region; and
forming first and second metal layers on the first and second metal contacts of each semiconductor device, respectively, wherein the first and second metal layers are sufficiently thick to support the semiconductor structure during later processing.
2. The method of claim 1 wherein forming first and second metal layers comprises plating first and second metal layers on the wafer.
3. The method of claim 1 wherein the first and second metal layers are thicker than
50 μιη.
4. The method of claim 1 wherein forming the first and second metal layers comprises:
forming a metal seed layer over the first and second metal contacts of each semiconductor device;
forming a photoresist layer over the metal seed layer;
patterning the photoresist to remove photoresist from regions overlying at least portions of the first and second metal contacts of each semiconductor device and to leave photoresist in a region between the first and second metal contacts of each semiconductor device;
plating the first and second metal layers; and
after plating the first and second metal layers, removing the photoresist and a portion of the seed layer underlying the photoresist after patterning the photoresist.
5. The method of claim 4 further comprising:
disposing an electrically insulating material over the wafer; and removing electrically insulating material overlying the first and second metal layers such that electrically insulating material is disposed between the first and second metal layers and between devices.
6. The method of claim 1 further comprising removing the growth substrate after forming the first and second metal layers.
7. The method of claim 1 further comprising dicing the wafer into individual or groups of semiconductor devices after forming the first and second metal layers.
8. A method comprising:
providing a wafer of semiconductor devices, the wafer comprising:
a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region; and
first and second metal contacts for each semiconductor device, wherein each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region; and
forming first and second metal layers on the first and second metal contacts of each semiconductor device, respectively, wherein the first and second metal layers are thicker than 50 μηι.
9. The method of claim 8 wherein forming first and second metal layers comprises plating copper layers on the wafer.
10. The method of claim 8 wherein forming the first and second metal layers comprises:
forming a metal adhesion layer over the first and second metal contacts of each semiconductor device;
forming metal seed layer over the metal adhesion layer;
forming a photoresist layer over the metal seed layer;
patterning the photoresist to remove photoresist from regions overlying at least portions of the first and second metal contacts of each semiconductor device and to leave photoresist in a region between the first and second metal contacts of each semiconductor device;
plating the first and second metal layers; and
after plating the first and second metal layers, removing the photoresist and portions of the adhesion layer and seed layer underlying the photoresist after patterning the photoresist.
1 1. The method of claim 10 further comprising:
disposing an electrically insulating material over the wafer; and
removing electrically insulating material overlying the first and second metal layers such that electrically insulating material is disposed between the first and second metal layers and between devices.
12. The method of claim 10 wherein the adhesion layer is TiW and the seed layer is
Cu.
13. The method of claim 8 wherein the semiconductor structure is grown on a growth substrate, the method further comprising removing the growth substrate after forming the first and second metal layers.
14. The method of claim 13 further comprising dicing the wafer into individual or groups of semiconductor devices after removing the growth substrate.
15. An apparatus comprising:
a semiconductor structure comprising a light emitting layer sandwiched between an n- type region and a p-type region;
a first metal contact in direct contact with the n-type region and a second metal contact in direct contact with the p-type region; and
a support comprising:
first and second copper layers disposed on the first and second metal contacts; and an electrically insulating material disposed between the first and second copper layers;
wherein:
the electrically insulating material surrounds the semiconductor structure; and the electrically insulating material surrounding the semiconductor structure has substantially vertical sidewalls.
16. The apparatus of claim 15 wherein the apparatus is mechanically self-supporting.
17. The apparatus of claim 15 wherein proximate an edge of the apparatus, the electrically insulating material is disposed adjacent both a sidewall of the semiconductor structure and a sidewall of one of the first and second copper layers.
18. The apparatus of claim 15 wherein the electrically insulating material is epoxy.
PCT/IB2012/056969 2011-12-08 2012-12-05 Forming thick metal layers on a semiconductor light emitting device WO2013084155A1 (en)

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