TWI485852B - 帶有很高的基體-閘極擊穿和嵌入式雪崩箝位二極體的橫向超級接面元件 - Google Patents

帶有很高的基體-閘極擊穿和嵌入式雪崩箝位二極體的橫向超級接面元件 Download PDF

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TWI485852B
TWI485852B TW099141442A TW99141442A TWI485852B TW I485852 B TWI485852 B TW I485852B TW 099141442 A TW099141442 A TW 099141442A TW 99141442 A TW99141442 A TW 99141442A TW I485852 B TWI485852 B TW I485852B
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source
pillar
gate
super junction
junction structure
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TW099141442A
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TW201123454A (en
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Madhur Bobde
Lingpeng Guan
Anup Bhalla
Hamza Yilmaz
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Alpha & Omega Semiconductor
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Priority claimed from US12/592,619 external-priority patent/US8575695B2/en
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Publication of TW201123454A publication Critical patent/TW201123454A/zh
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Description

帶有很高的基體-閘極擊穿和嵌入式雪崩箝位二極體的橫向超級接面元件
本發明主要關於半導體功率元件。更確切地說，本發明是關於製備橫向功率元件的結構和方法，該元件含有一個超級接面結構，帶有形成在汲極基體和閘極之間的雪崩箝位二極體。這種橫向超級接面結構降低了導通電阻，同時結構上的改進提高了基體和汲極之間的擊穿電壓，改善了非箝位元感應開關(UIS)功能。
MOSFET功率元件等傳統的帶有超級接面結構的半導體功率元件，可以在維持高擊穿電壓的同時，顯著降低導通電阻，從而獲得性能上的提高。但是，要在MOSFET元件中製備超級接面結構的製備技術和元件結構，仍然面臨許多製備能力上的難題。用於高壓應用的帶有超級接面結構的傳統的垂直功率元件，由於它們的結構特點需要許多費時、複雜和昂貴的製備技術，在製備能力和成本上仍然有所侷限。按照目前方法的製備技術要製成垂直結構，包括很多連續的掩膜、植入和外延生長過程。由於製備高密度的交替摻雜立柱會直接增加製備步驟，因此不可能完成。要製備高密度的這種立柱，太多的因素會影響相鄰的交替摻雜立柱之間的電 荷平衡的準確性，導致很窄的技術範圍。Tatsuhiko Fujihira在《日本應用物理學雜誌36(1997)》6254-6262頁發表的題為“半導體超級接面元件的理論”的論文中揭露，第1A圖表示MOSFET垂直超級接面元件的一種典型設計。要製備第1A圖所示的垂直電荷平衡的交替摻雜立柱，不僅困難而且成本昂貴，高密度時尤其如此。
基於上述原因，帶有超級接面結構的橫向JFET功率元件，伴有交替摻雜導電類型的堆積式水準層形成，克服了這些困難。這種元件可以與低壓MOSFET配置級聯，實現了傳統元件的常閉操作。Coe在專利US 4,754,310中，提出了帶有電荷平衡的超級接面結構的橫向功率元件，配置交替導電類型的堆積式水準層延伸到源極和汲極立柱之間。有效地製備堆積式水準層的這種結構無需使用掩模。但是，如第1B圖所示的典型元件配置受到汲極-基體擊穿電壓的限制，以及來自難以提高非箝位元感應開關(UIS)的進一步限制。第1C圖表示Tatsuhiko Fujihira在上述《半導體超級接面元件的理論》一文中提出的另一種橫向超級接面元件的示例。這種元件將電流分佈到堆積式n-型導電路徑中時，要承載過多的通道電阻。
因此，在功率半導體元件的設計和製備技術中，仍然有必要提出形成橫向功率元件的新穎的元件結構和製備方法，從而使上述困難與侷限得以解決。
因此，本發明的一個方面是提出了一種在P-外延層上形成接面場效電晶體(JFET)和MOSFET功率元件的新型的、改良的元件結構 和製備方法，P-外延層蝕刻中間半導體層，在N基體上方，構成帶有在N型深立柱之間延伸的橫向超級接面結構的底部半導體層，起源極和汲極立柱的作用，P+深立柱蝕刻JFET閘極。在這個結構中，將汲極端移動到基體，以便將兩個高電流端分開，將兩個平面分開，更佳的分佈電流。可以藉由使汲極溝槽的深度比源極和閘極更深，實現上述目的，從而使汲極端穿過P外延區，觸及N+基體。這種結構還會產生凹的或鞍狀的N+汲極基體-P-外延N+汲極立柱接面，獲得高基體閉鎖電壓。另外，從N+汲極基體到P-外延層，一直到P+閘極立柱，所形成的N+-P-P+閘極-汲極雪崩箝位二極體，蝕刻強大的高壓二極體，將雪崩電流轉移出該元件的超級接面層。
本發明的另一方面在於，提出了一種帶有低壓MOSFET與超級接面JFET整合結構的常閉的半導體功率元件的新型的、改良的元件結構和製備方法。低壓MOSFET設置在元件表面附近，具有可以獲得製備常閉開關所需的級聯連接的結構。
閱讀以下較佳實施例的詳細說明並參照附圖之後，本發明的這些和其他的特點和優勢，對於本領域的技術人員而言，無疑將顯而易見。
100‧‧‧JFET元件
105、505、705‧‧‧N+基體
106‧‧‧N緩衝區
107、475、723‧‧‧氧化物
110‧‧‧汲極金屬電極
115、215、415、515、715‧‧‧P-外延層
120-D‧‧‧N汲極立柱
120-S‧‧‧N源極立柱
120-S-M、270-S、488、521、580、580’、780‧‧‧源極金屬
121、421、521’‧‧‧雪崩二極體
125‧‧‧N+摻雜區
130‧‧‧P+摻雜立柱
130-M‧‧‧閘極金屬
135、165‧‧‧P+摻雜區
140‧‧‧摻雜層
150‧‧‧N摻雜層
205‧‧‧P+基體
222‧‧‧第一氧化層
222‧‧‧硬掩膜層
222’‧‧‧第二氧化層
240、250‧‧‧P和N摻雜層
223、489‧‧‧開口
225、725‧‧‧閘極溝槽
235‧‧‧多晶矽襯裏層
241‧‧‧氧化層
224‧‧‧溝槽開口
245-S、745-S‧‧‧源極溝槽
255、255-1‧‧‧N+區
265、565‧‧‧P+區
251‧‧‧金屬層
260、261、260-1‧‧‧Ti/TiN層
245-D、745-D、781‧‧‧汲極溝槽
251-1、783、782‧‧‧金屬
230‧‧‧閘極
280‧‧‧鈍化層
290‧‧‧汲極金屬層
215’‧‧‧P-型基體
205’‧‧‧N+汲極
390A‧‧‧半導體晶片
391A‧‧‧超級接面JFET
392A‧‧‧低壓MOSFET區
392B‧‧‧MOSFET區
390B、390C‧‧‧晶片
392C、470‧‧‧MOSFET
391C、500、500-3、500’‧‧‧JFET
400‧‧‧高壓橫向超級接面JFET
420-D、420-S、430‧‧‧N和P摻雜立柱
471‧‧‧N+源極區
472‧‧‧P本體區
473‧‧‧平面閘極
420-S‧‧‧N+源極立柱
440、540‧‧‧P層
450、550‧‧‧N層
405‧‧‧N+汲極基體
410、510‧‧‧汲極金屬
430‧‧‧JFET P+閘極立柱
473‧‧‧MOS閘極
477‧‧‧多晶矽閘極澆道
520-S、520’-S‧‧‧N+JFET源極立柱
530、530’‧‧‧P+JFET閘極立柱
520-D‧‧‧N+JFET汲極立柱
573、573’‧‧‧MOS閘極電極
571、571’‧‧‧N+MOS源極
575、575’‧‧‧N+MOS汲極
572、572’‧‧‧P MOS本體區
574、574’‧‧‧薄閘極電介質
544、576‧‧‧厚介質層
575‧‧‧MOS汲極
520’-D‧‧‧N+JFET閘極立柱
576’‧‧‧厚電介質
740‧‧‧P型層
750‧‧‧N型層
722‧‧‧硬掩膜
705‧‧‧N基體
719‧‧‧閉鎖掩膜
730‧‧‧P+閘極立柱
726‧‧‧第二硬掩膜
727‧‧‧氧化物填充
720-S‧‧‧N型源極立柱
720-D‧‧‧N型汲極立柱
752‧‧‧N+多晶矽墊片
753‧‧‧N+多晶矽填充物
765‧‧‧P+區
771‧‧‧N+MOS源極區
772‧‧‧P-本體區
773‧‧‧閘極多晶矽
774‧‧‧薄閘極氧化物
775‧‧‧N+MOS汲極區
776‧‧‧絕緣材料
777‧‧‧接觸孔
778‧‧‧P+本體接觸區
790‧‧‧底部汲極金屬
第1A圖表示一種垂直超級接面功率元件的傳統結構的橫截面視圖；第1B圖表示傳統的橫向功率元件的橫截面視圖；第1C圖表示傳統的橫向超級接面功率元件的橫截面視圖；第2圖表示本發明所述的橫向超級接面功率元件的橫截面視圖； 第3A圖至第3N圖表示本發明所述的橫向超級接面功率元件的製備方法的一系列橫截面視圖；第3A-1圖至第3C-1圖表示製備本發明所述的橫向超級接面功率元件的可選方法的一系列橫截面視圖；第4A圖至第4C圖表示本發明所述的整合橫向超級接面結構的MOSFET的可能佈局的俯視圖；第5A圖至第5B圖表示本發明所述的整合橫向超級接面結構的MOSFET的透視圖的橫截面；第5C圖表示第5A圖和第5B圖所示元件的俯視圖；第5D圖至第5F圖表示沿第5B圖的A-A、B-B和C-C截面線的橫截面視圖；第6A圖表示本發明所述的橫向超級接面JFET的條紋結構的俯視圖；第6A-1圖至第6A-3圖表示沿第6A圖所示的D-D和E-E截面線的橫截面視圖；第6B圖和第6C圖表示第6A圖所示的MOSFET與JFET的整合方式的俯視圖；第6C-1圖表示沿第6C圖所示的F-F截面線的橫截面視圖；第6D圖表示條紋結構中的JFET的多行俯視圖；第7A圖表示本發明所述的橫向超級接面JFET的封閉元件結構的俯視圖；第7A-1圖表示沿第7A圖所示的G-G截面線的橫截面視圖；第7B圖和第7C圖表示第7A圖所示的MOSFET與JFET的整合方式的俯視圖；第7C-1圖表示沿第7C圖所示的H-H截面線的橫截面視圖；以及 第8A圖至第8Q圖表示MOSFET與本發明所述的橫向超級接面JFET的整合方式的一系列橫截面視圖。
參照第2圖表示本發明所述的具有底部汲極基體的橫向超級接面高壓(HV)JFET元件100的橫截面視圖。該橫向JFET元件100支撐於作為汲極的N+基體105上的P-外延層115，以及可選的N+基體105上的N緩衝區106。橫向JFET元件100含有一個設置在基體105底部上的汲極金屬電極110。橫向功率元件100還包括一個N源極立柱120-S和N汲極立柱120-D，分別作為第一和第二導電立柱，設置在第一溝槽和第二溝槽中，並且分別位於基體的兩個相對邊上。在本實施例中，這些源極和汲極溝槽都包括被N+摻雜區125包圍著的溝槽中的導電材料(例如金屬填充物或多晶矽)。當然，也可以使用其他方法製備N+汲極和源極立柱120-D和120-S。N+源極立柱120-S通過氧化物107的開口，接觸頂面上的源極金屬120-S-M。設置在溝槽中的汲極120-D，向下延伸接觸N+汲極基體層105。源極溝槽向下蝕刻到P外延層115中。P+摻雜區165設置在源極120-S下方，以便抑制寄生NPN雙極電晶體的啟動，該寄生電晶體從N+源極立柱120-S到P-外延層115，一直到N+基體105。P-外延層115中重摻雜的P+區165，大幅降低了少數載流子的壽命，從而抑制了寄生NPN電晶體。
橫向JFET元件100還包括一個P+摻雜立柱130，設置在另一個溝槽中，當作該橫向功率元件的閘極。與N+源極和汲極立柱120-S和120-D類似，P+閘極立柱130也是由被P+摻雜區135包圍著的溝槽構成，該溝槽由金屬或多晶矽填充。進一步設計P+閘極立柱130 和P-外延層115，以及可選的N-緩衝區106，製成雪崩二極體121，以便箝制擊穿電壓。超級接面元件通常難以抵禦雪崩擊穿帶來的損害。如果雪崩擊穿發生在電荷平衡區中，雪崩電流會在起始的小區域內聚集並放大，對該區域造成永久性地損壞。雪崩二極體121將雪崩電流路徑轉移出電荷平衡的超級接面區域，使它改道流經P+閘極立柱130和N+汲極層105之間，從而提高了元件的穩健性。P+閘極立柱130連接到頂面上的閘極金屬130-M。源極和汲極120-S和120-D也可以由N+摻雜的多晶矽構成，多晶矽填充在溝槽中，或者由金屬插頭構成，金屬插頭填充在帶有N+摻雜側壁的溝槽中。也可選擇，藉由外延生長填充溝槽，或者藉由其他方法製備溝槽。關鍵是要用N+摻雜的半導體材料構成溝槽的側壁。
橫向功率元件具有一個超級接面結構，由多層相互交替的水準的摻雜層140和N摻雜層150形成。這些相互交替的P摻雜層和N摻雜層，在源極120-S和汲極120-D之間，提供多個電荷平衡的導電通道。電流沿著橫向傳導，閘極130控制、導通/關閉功率元件。第1圖中的閘極130設置在與源極和汲極不同的平面，因此不會切斷在超級接面結構中伴隨有相互交替的N和P摻雜層所形成的橫向通道。閘極立柱130和源極立柱120-S應該比超級接面結構還深，以便接觸P外延層115。閘極立柱130的深度可以與源極立柱120-S相同，或者比源極立柱120-S還深。形成閘極立柱130的深度大於源極立柱120-S的話，有助於將雪崩電流引導到閘極立柱130和雪崩二極體121上，而不是傳輸到源極立柱120-S下面的寄生NPN電晶體上。橫向超級接面JFET元件100的電路圖，表示出了元件終端的汲極金屬110、源極金屬120-S-M以及閘極金屬130-M。雪崩二 極體121形成在閘極和汲極之間。
參照第3A圖至第3N圖表示本發明所述的橫向超級接面的JFET元件的製備過程的一系列橫截面視圖。第3A圖表示P-外延層215支撐於P+基體205上，P-外延層215的摻雜濃度和層厚能夠阻擋600伏的電壓。例如可以藉由利用美國申請案12/592,619中的第10圖至第12圖所示的一個技術，使交替的P和N摻雜層240和250分別形成在P-外延層215的上方，形成電荷平衡層。在第3B圖中，形成硬掩膜層222，例如可以藉由熱氧化過程，生長一層厚約205埃的氧化層，然後藉由沉積氧化物，形成厚氧化層，作為硬掩膜層222。利用光致抗蝕劑掩膜，蝕刻穿過硬掩膜222形成開口223。在第3C圖中，利用矽蝕刻技術，打開閘極溝槽225，閘極溝槽225垂直穿過交替的P和N摻雜層240和250的超級接面結構，延伸到P-外延層215，閘極溝槽225的深度約為60微米，寬度約為10微米。為了便於製備該元件，閘極溝槽225可以帶有88度的輕微斜度。在第3D圖中，將帶有硼離子的P+植入到閘極溝槽中，形成P+區230，包圍著閘極溝槽225。僅作示例，硼植入物的植入能量可約為40keV，濃度約為5E15cm-2，傾斜角約為7度，作四次90度旋轉，然後用相同的離子流量進行垂直的硼離子植入。在第3E圖中，首先在閘極溝槽225的側壁和底面上，形成多晶矽襯裏層235，然後將氧化層241填充到閘極溝槽中。還可以向多晶矽層中摻雜P+，以降低閘極溝槽的電阻。然後，藉由多晶矽和氧化物回刻，除去頂面上方的多晶矽和氧化物。雖然多晶矽層235是任選的，但是在回刻或化學機械拋光(CMP)氧化層241時，它可以蝕刻一個合適的終點。也可以非摻雜地沉積多晶矽235，然後用來自P+層230 的P型摻雜物擴散到多晶矽235中。
參照第3F圖中，第二氧化層222’沉積在作為硬掩膜的第一氧化層222上方。在圖3G中，利用源極掩膜，通過氧化層222和222’打開溝槽開口224。在第3H圖中，藉由超級接面結構，將源極溝槽245-S蝕刻到能夠觸及P-外延層215的深度。在一個實施例中，溝槽的深度約在40至44微米之間，寬度約為10微米。無論如何，源極溝槽245-S都應在P-外延層215中終結。然後，製備技術繼續進行，藉由帶角度的N+植入(大約7度傾斜角)以及垂直N+植入，形成N+區255，包圍著溝槽245-S的側壁和底部。在第3I圖中，利用垂直P+植入，在溝槽245-S的底部形成P+區265。在第3J圖中，首先沉積Ti/TiN層260覆蓋側壁、溝槽的底面以及氧化物222’的頂面上方。然後，沉積一個6-8微米的厚金屬層251，填充溝槽245-S。藉由化學機械拋光(CMP)技術，除去金屬層251和Ti/TiN層260的頂部，以便形成平整的頂面。在第3K圖中，利用汲極溝槽掩膜，在半導體材料中蝕刻汲極溝槽245-D，例如藉由氧化物蝕刻和矽蝕刻。汲極溝槽245-D向下穿過超級接面結構和P-外延層215，到達N+基體205。N+區255-1沿著汲極溝槽245-D的側壁形成。另一個Ti/TiN層260-1形成在溝槽的側壁上，如果形成了金屬251-1，那麼就將其置於Ti/TiN層260-1上。如第3L圖所示，可以在金屬251-1上方進行化學機械拋光。第二金屬層沉積在頂面上方，覆蓋著Ti/TiN層260的上方。在沉積金屬層(圖中未示)之前，可以選擇沉積另一個Ti/TiN層261。如第3M圖所示，利用金屬掩膜，將金屬層形成源極金屬270-S、閘極金屬(圖中沒有表示出)或有頂部汲極金屬(圖中沒有表示出)的圖案 。閘極230可以在第三個維度上，連接到閘極金屬(圖中沒有表示出)上。在第3N圖中，例如由標準的二氧化矽/氮化物/聚醯亞胺堆積構成的鈍化層280，然後利用鈍化掩膜形成鈍化層280的圖案，使源極金屬270-S裸露出來。藉由背部研磨操作，以及背部金屬化技術，在P+基體205的底面上形成一個底部汲極金屬層290，完成整個製備過程。
對於熟練本技術的人而言，本發明所述的橫向超級接面JFET的形成顯然還有很多可選方法。例如，有許多製備閘極、汲極和源極立柱的方法。
一種可選方法從第3A-1圖開始，首先在單一的P-型基體215’上形成超級接面結構--P型基體215’與第3A圖所示的P-外延層215類似，但不包含N+基體205。一直到背部研磨之前的所有製備過程都與之相同。此時，如第3B-1圖所示，P-型基體215’的背面研磨到或接近汲極溝槽245-D的底部。可以藉由將N+摻雜離子植入到元件的背面，形成N+汲極205’，N+汲極205’連接到汲極溝槽245-D上，可以形成背部汲極金屬290。其他可選技術將在本說明書中稍後進行說明。
JFET是一種常態導通元件。在許多應用中，人們更願意選擇常態斷路功率開關，而不是常態導通功率開關，其原因包括元件在電路啟動時是關閉的、與已有的設計相容、更加熟悉等。第4A圖至第4C圖表示本發明所述的將低壓MOSFET與高壓橫向超級接面JFET一起整合在一個單一的半導體晶片上的三種可能的佈局。MOSFET可以在級聯結構中，與JFET排列在一起，就像第4A圖中所示的電路那樣，以便構成一個常態導通的功率開關元件。在第4A圖中， 半導體晶片390A含有本發明所述的高壓橫向超級接面JFET 391A以及低壓MOSFET區392A。在第4B圖中，三個MOSFET區392B分佈在整個單一的大型JFET區391B上，以降低晶片390B中的封裝電阻和電感。在第4C圖中，MOSFET 392C整合在晶片390C中的JFET 391C的元件元件等級上。如第4C圖所示，MOSFET 392C與JFET 391C的每個元件整合。MOSFET和JFET可以在級聯結構中，內部和/或外部互聯。低壓MOSFET是本領域中被人們所熟知的元件，可以轉化成任何形式，包括橫向MOSFET、垂直MOSFET、溝槽閘極、平面閘極等等，而且在級聯電路結構中，將MOSFET連接到JFET上也有很多不同的封裝方式。
當然，MOSFET也可以與本發明所述的橫向超級接面JFET共同封裝在一個具有分立的MOSFET和超級接面JFET半導體晶片的單一封裝中。該半導體晶片可以並排共同封裝，或在一個堆積式結構中共同封裝。
參照第5A圖表示本發明所述的MOSFET 470與高壓橫向超級接面JFET 400整合的透視圖的橫截面。在本實施例中，MOSFET 470整合在每個JFET 400元件中，就像第4C圖所示的佈局中那樣。在本佈局中，橫向低壓MOSFET 470位於第三維度上，垂直於橫向超級接面JFET 400的平面通道方向。JFET 400的結構與第2圖所示的橫向超級接面JFET 100的結構類似。在這些圖中，JFET N+汲極立柱420-D和源極立柱420-S以及JFET P+閘極立柱430分別用簡單的N和P摻雜立柱表示。摻雜立柱420-D、420-S和430的工作方式與JFET 100的N和P立柱的工作方式相同。在本實施例中，MOSFET 470是由P本體區472中的N+源極區471構成。MOSFET N+源極471 也兼任級聯電路的總源極。MOSFET 470還包括氧化物475中的平面閘極473，平面閘極473兼任級聯電路的總閘極。MOSFET 470的N+汲極也兼任JFET 400的N+源極立柱420-S。JFET 400的橫向超級接面結構包括電荷平衡的交替堆積式P層440和N層450，構成橫向超級接面漂流區，從JFET N+源極立柱420-S延伸到JFET N+汲極立柱420-D。超級接面結構位於N+汲極基體405上方的P外延層415上。汲極立柱420-D向下延伸到N+汲極基體405。汲極金屬410可以位於N+汲極基體405下方。JFET N+汲極立柱420-D(和N+汲極基體405以及汲極金屬410)兼任級聯電路的總汲極。JFET 400由JFET P+閘極立柱430控制，JFET P+閘極立柱430穿過超級接面P和N層440和450，向下延伸到P-外延層415。按照該級聯電路，JFET P+閘極立柱430通過源極金屬488，短接到MOSFET N+源極區471上。依據本發明，所形成的雪崩二極體421，從JFET P+閘極立柱430穿過P-外延層415到N+汲極基體405。雪崩二極體421將雪崩電流轉移遠離由電荷平衡交替堆積的N和P層450和440構成的超級接面結構。
正如電路圖中所示的那樣，MOSFET(MOS)470在級聯結構中連接到超級接面JFET 400上。MOS 470的汲極與JFET源極420-S相連。JFET閘極430連接到MOS源極471上。依據本發明，橫向超級接面JFET 400還包括一個位於其閘極430和汲極420-D之間的雪崩二極體421。
儘管第5B圖與第5A圖相同，但它標示出第5D圖至第5F圖所示的垂直橫截面的位置。第5D圖表示A-A橫截面，源極金屬488連接到MOS N+源極471和JFET P+閘極立柱430上。源極金屬488在第三 維度上還連接MOS P本體472。第5E圖表示B-B橫截面，N+JFET源極立柱420-S以及N+JFET汲極立柱420-D。儘管P+JFET閘極立柱430是在第三維度上，但是橫截面B-B表示出了橫向超級接面JFET 400。在N+JFET源極立柱420-S下面形成P+植入物，以抑制從N+源極立柱420-S到P-外延層415，一直到N+汲極基體405所產生的寄生NPN電晶體。第5F圖表示C-C橫截面，示出低壓MOSFET 470。MOSFET是被人們所熟知的元件，顯然，也可形成其他等效的元件結構將MOSFET與本發明所述的橫向超級接面JFET整合起來。
參照第5C圖表示第5A圖和第5B圖所示的橫向超級接面JFET 400與MOSFET 470整合起來的俯視圖。為清晰起見，圖中沒有表示出頂部絕緣層。源極金屬488的輪廓由虛點線表示。虛線表示接觸開口489的輪廓，用於使源極通過氧化物475(圖中沒有表示出)，接觸N+MOS源極區471和P+JFET閘極立柱430。MOS閘極473使通道形成在下方的本體區472(圖中沒有表示出)中，從N+MOS源極區471到N+MOS汲極區/JFET源極立柱420-S。多晶矽閘極澆道477將閘極473連接在一起。電流可以從N+JFET源極立柱420-S開始，穿過超級接面結構(頂部P層440下方的N層450)，到達N+JFET汲極立柱420-S。根據級聯結構，JFET P+閘極立柱430在接觸開口489處，短接到MOS N+源極區471上，當MOS閘極473關閉時，為元件提供高壓閉鎖。
參照第6A圖表示本發明所述的底部汲極橫向超級接面JFET 500的俯視圖。第6A圖表示的是條紋結構中的JFET 500。它具有N+JFET源極立柱520-S，形成一個條紋。P+JFET閘極立柱530沿著N+ JFET源極立柱520-S條紋斷斷續續地形成，就像一個虛條紋。P+ JFET閘極立柱530相互錯開，使得從N+JFET源極立柱520-S到N+ JFET汲極立柱520-D的電流路徑可導通。第6A圖的D-D橫截面由第6A-1圖表示。P-外延層515位於N+基體505上。P-外延層上方，交替堆積的P層540和N層550構成橫向超級接面結構。為P層540和N層550選擇合適的摻雜濃度和厚度，使它們達到電荷平衡。N層550形成從N+JFET源極立柱520-S到N+JFET汲極立柱520-D的橫向通路。斷路時P+JFET閘極立柱530夾斷電流。N+JFET汲極立柱520-D向下延伸到N+汲極基體505，形成底部汲極元件。P+區565可以形成在N+JFET源極立柱520-S的下方，以抑制從N+源極立柱520-S到P-外延層515，一直到N+基體505，所形成的寄生NPN雙極電晶體。依據本發明，從P+閘極立柱530到N+基體(經由P-外延層515)，也可以形成雪崩二極體521。
參照第6A-2圖的E-E橫截面所示，獨立的閘極立柱530也可以同淺P+表面植入物541連接在一起。也可選用金屬條紋將P+閘極530連接到頂部。第6A-3圖表示一個完整的JFET 500-3，從第6A圖的D-D橫截面來看，源極金屬和閘極金屬在上面，汲極金屬在底部。源極金屬521連接N+JFET源極立柱520-S，閘極金屬531通過厚介質層544(例如氧化物或含有硼磷的矽玻璃BPSG)中的開口，連接P+JFET閘極立柱530。汲極金屬510形成在N+基體505的底部。
低壓MOSFET也可以與橫向超級接面JFET 500整合，以便與超級接面JFET在同一平面上。MOSFET可以在級聯電路中連接到JFET 500上，使整個元件成為一個常態斷路元件。第6B圖表示第6A圖之後製備MOSFET的下一步--在元件上方製備MOS閘極電極573(例如 多晶矽)。薄閘極氧化物(第6B圖中沒有表示出)使MOS閘極573與半導體表面絕緣。
然後，在元件上方植入N+MOS源極571以及N+MOS汲極575區，並且自對準到MOS閘極573。如圖6C的俯視圖所示，形成P MOS本體區572，自對準到MOS閘極573。P+JFET閘極立柱530和N+JFET源極立柱520-S如圖中虛線所示。
參照第6C-1圖表示第6C圖的F-F橫截面。N+MOS源極571位於P MOS本體區572中，它們都自對準到MOS閘極573。薄閘極電介質574(例如閘極氧化物)將MOS閘極573與半導體表面分開。在MOS閘極573的另一側，所形成的N+MOS汲極575也自對準到MOS閘極573。依據級聯電路結構，N+MOS汲極575連接到N+JFET源極立柱520-S上。源極金屬580，通過厚介質層576中的開口，連接N+MOS源極571和MOS P本體572。MOS P本體572連接P+JFET閘極立柱530，因此，依據級聯電路結構，MOS的源極和JFET的閘極也連接在一起。於是，電流受MOS閘極573的控制，從N+MOS源極571，流至N+ MOS汲極575。電流可以從N+MOS汲極575，繼續穿過N+JFET源極立柱520-S，到超級接面N層550，橫向流至N+JFET汲極520-D。在級聯結構中，P+JFET閘極530短接到N+源極571上，因此當MOSFET導通時，JFET閘極530的電勢與JFET源極520-S(以及MOS汲極575)的電勢基本相同，從而使電流流經N層550。電流可以向下通過N+JFET汲極立柱520-D，流至N+汲極基體505，並到達汲極金屬510下面。當MOSFET斷路時，JFET閘極530的電勢低於JFET源極520-S/MOS汲極575，從而切斷電流，下文還將詳細說明。除去MOS閘極573偏壓，可斷開低壓MOSFET。在這種情況下，給 汲極終端510載入正向偏壓，將在N層550上產生正向偏壓，在JFET P閘極530上產生相應的反向偏壓，導致超級接面N層550和P層540以及P-外延層515耗盡。在一定的汲極偏壓下，相鄰的P層540的耗盡區會合併，夾斷JFET源極立柱520-S，不受多餘的汲極電壓的影響。這使得元件漏電流很低，可以閉鎖高壓。而且由於JFET夾斷後可以承受額外電壓，則可以在級聯電路中，使用低壓MOSFET。當P外延區515在高汲極偏壓下耗盡時，它所產生的電荷降低了P+閘極530下方的峰值電場，使元件結構具有很高的基體擊穿電壓。儘管本文沒有闡述，但是MOS閘極573也可以連接到位於半導體晶片的另一部分上的閘極金屬端上。
參照第6D圖所示，源極和汲極條紋結構和佈局可以在整個半導體晶片上重複。
參照第7A圖表示封閉元件結構的一種可選佈局的俯視圖。更確切地說，它表示的是六邊形封閉元件結構。基本的橫向超級接面JFET 500’結構的俯視圖如圖7A所示，橫截面視圖如第7A-1圖所示。N+JFET源極立柱520’-S位於一個互聯的六邊形網路中。在N+JFET源極立柱520’-S旁邊的是P+JFET閘極立柱530’。P+JFET閘極立柱530’相互錯開，使電流流經它們之間。每個六邊形的中心是N+JFET閘極立柱520’-D。如第7A-1圖的橫截面視圖所示，JFET元件位於電荷平衡的堆積式P層540和N層550的超級接面結構中，P層540和N層550位於N+基體505上方的P-外延層515上方。在每個六邊形封閉元件中，電流從六邊形邊緣處的N+JFET源極立柱520’-S開始，橫向穿過超級接面N層520，流至六邊形中心處的N+JFET汲極立柱520’-D。然後，電流向下穿過N+汲極立柱 520’-D到達N+基體505。在N+JFET源極立柱520’-S下方形成一個NPN抑制P+區565’，並從P+JFET閘極立柱530’到N+基體505，形成一個雪崩二極體521’。
類似第6A圖至第6D圖所示的條紋結構，可以在級聯電路結構中，輕鬆地將MOSFET與第7A圖所示的JFET 500’整合起來，如第7B圖至第7C圖所示。在7B所示的俯視圖中，可見一個單一的六邊形封閉元件的全貌，MOS閘極電極573’的網路形成在晶片頂部上方。MOS閘極573’在N+JFET源極立柱520’-S的旁邊。
參照第7C圖所示的俯視圖中，所形成的N+MOS源極571’和N+MOS汲極575’區自對準到MOS閘極573’。形成P MOS本體區572’，自對準到MOS閘極573’，包圍著N+MOS源極區571’。N+JFET源極立柱520’-S和P+JFET閘極立柱530’的輪廓如圖中虛線所示。如第7C-1圖的H-H橫截面所示，源極金屬580’通過厚電介質576，中的開口，接觸N+MOS源極571’和P MOS本體572’。依據級聯電路，源極金屬580’也通過P MOS本體572’，連接到P+JFET閘極立柱530’上。N+MOS汲極575’形成在MOS閘極573’的另一邊。薄閘極電介質574’將MOS閘極573’與半導體表面絕緣。依據級聯電路結構，N+MOS汲極575’連接到N+JFET立柱520’-S上。
參照第8A圖至第8Q圖表示MOSFET與本發明所述的橫向超級接面JFET的整合在一起的製備方法的一系列橫截面視圖。製備過程從第8A圖開始，製備一個由交替堆積的電荷平衡的P型層740和N型層750製成的橫向超級接面結構。該橫向超級接面結構形成在P-外延層715上方，P-外延層715形成在N+基體705上方。
然後，在最上層P型層740-1上方製備一個硬掩膜722(例如氧化物)並形成圖案。如第8B圖所示，在半導體材料中蝕刻閘極溝槽725。閘極構成725向下穿過橫向超級接面結構，延伸到P-外延層715。在第8C圖中，閘極溝槽725內襯有P+植入(例如藉由帶角度的植入)，形成P+閘極立柱730。在第8D圖中，形成第二硬掩膜726，並形成圖案。第二硬掩膜材料也可以填充在閘極溝槽725中(例如藉由氧化物填充727)。源極溝槽745-S和中間的汲極溝槽745-D蝕刻到半導體材料中，穿過P層740和N層750的橫向超級接面結構，到達P-外延層715。中間的汲極溝槽745-D比源極溝槽745-S窄得多。將源極溝槽745-S的側壁和中間的汲極溝槽745-D植入N型，構成N型源極立柱720-S和中間的N型汲極立柱720-D。在第8E圖中，沿源極溝槽745-S的側壁，形成的N+多晶矽墊片752。僅作示例，多晶矽墊片752的製備，可以藉由沉積一層多晶矽，然後各向異性地蝕刻多晶矽層，在源極溝槽745-S中留下多晶矽墊片752。製備多晶矽墊片752的過程，還包括將N+多晶矽填充物753填充在較窄的中間汲極溝槽745-D中。在第8F圖中，利用垂直P+植入，在源極溝槽745-S底部的P-外延層715中，形成P+區765。P+區765抑制了從N源極立柱720-S到P-外延層，一直到N基體705，所形成的寄生NPN電晶體。
參照第8G圖中，在元件上方沉積氧化物723，並使其平整。再將氧化物填充到源極溝槽745-S的剩餘空間中。利用第三掩膜，形成氧化物723的圖案，在將要形成MOSFET的區域中，將氧化物723向下蝕刻到半導體材料的平面。在裸露的半導體材料上形成薄閘極氧化物774，然後形成閘極多晶矽773，並用第四掩膜在閘極氧 化物774上方形成圖案，如第8H圖所示。在第8I圖中，將第五掩膜用作本體閉鎖掩膜。將本體閉鎖掩膜719、閘極多晶矽773和氧化物723蝕刻掩膜，藉由P本體植入形成P-本體區772。本體區772自對準到閘極多晶矽773。如圖閘極多晶矽773足夠長，例如閘極多晶矽773延伸到N源極立柱720-S，那麼可能並不需要本體阻擋掩膜719。
然後，在第8J圖中，藉由無掩膜的N+植入，在閘極多晶矽773的對邊上形成N+MOS源極區771以及N+MOS汲極區775。閘極多晶矽773在MOS源極771和MOS汲極775之間，形成一個平面閘極，MOS源極771和MOS汲極775自對準到閘極多晶矽773。N+MOS汲極775連接到N JFET源極立柱720-S，P-本體區772連接到P+JFET閘極立柱730。
參照第8K圖所示，BPSG(含有硼磷的矽玻璃)等絕緣材料776形成在上方，隔絕元件的頂面。在第8L圖中，利用第六掩膜，藉由穿過BPSG 776蝕刻到半導體材料中，形成接觸孔777。接觸孔777應穿過N+MOS源極771，蝕刻到P-本體772。可以在接觸孔777的底部，例如藉由垂直植入，形成P+本體接觸區778。如第8M圖所示，沉積源極金屬780並形成圖案，使得源極金屬780填充到接觸孔777中，並接觸N+MOS源極771和P-本體772(通過P+本體接觸區778)。依據級聯電路結構，源極金屬780也通過P本體772，連接到P JFET閘極立柱730。在第三維度上，也可以形成閘極墊(圖中沒有表示出)，用於到MOS閘極多晶矽773的外部連接。僅作示例，源極金屬780可以是鋁。
參照第8N圖中，利用第八掩膜，在中間的JFET汲極立柱720-D處 ，形成汲極溝槽781。藉由中間的JFET汲極立柱720-D蝕刻汲極溝槽781。向下穿過P-外延層715，到N+基體705中。在第80圖中，例如藉由製備N+多晶矽墊片、N+外延生長或通過溝槽裸露的側壁，將N型區779襯在汲極溝槽781內側。如第8P圖所示，在汲極溝槽781中形成金屬783。蝕刻示例，金屬783可以是鍍銅，在汲極溝槽中蝕刻金屬783，在源極金屬780上方，蝕刻金屬782。最後，在第8Q圖中，將晶片/N+基體705的背部減薄，在底部形成底部汲極金屬790。
綜上所述，有許多製備JFET源極、閘極和汲極立柱的方法，包括摻雜半導體、蝕刻溝槽然後填充摻雜的多晶矽、蝕刻溝槽然後內襯植入的摻雜物或摻雜的多晶矽並用導電材料或氧化物填充剩餘溝槽，等等。更多的可選方法包括蝕刻溝槽，藉由外延生長形成摻雜的側壁，從頂面植入，植入的同時製備外延層和超級接面層，等等。
儘管上述實施例是以矽為例做的說明，但是業內人員應理解，該技術也可用於碳化矽(SiC)、鍺(Ge)、金剛石、砷化鎵(GaAs)或氮化鎵(GaN)等任一種半導體材料。而且應理解，N+和P+立柱含有源極、汲極和閘極立柱，可以由多種不同的方式製成。雖然本發明闡述的是一種N-通道JFET，但是藉由轉換P型和N型半導體區域的導電類型，本發明也可用於P-通道JFET。
儘管已經就現有的較佳實施例對本發明做了說明，但應理解這些內容並不應蝕刻侷限。閱讀上述說明後，各種變化和修正對於本領域的技術人員而言無疑將顯而易見。因此，所附的權利要求書應看作是涵蓋本發明真實意圖和範圍內的全部變化和修正。
100‧‧‧JFET元件
105‧‧‧N+基體
106‧‧‧N緩衝區
107‧‧‧氧化物
110‧‧‧汲極金屬電極
115‧‧‧P-外延層
120-D‧‧‧N汲極立柱
120-S‧‧‧N源極立柱
120-S-M‧‧‧源極金屬
121‧‧‧雪崩二極體
125‧‧‧N+摻雜區
130‧‧‧P+摻雜立柱
130-M‧‧‧閘極金屬
135‧‧‧P+摻雜區
140‧‧‧摻雜層
150‧‧‧N摻雜層
165‧‧‧P+摻雜區

Claims (27)

  1. 一種半導體功率元件，包括：一含有超級接面結構的半導體基體，該超級接面結構設置在該半導體基體的頂面附近，其中該超級接面結構是由複數個第一和第二導電類型交替的橫向堆積層構成的，從一源極立柱橫向延伸到一汲極立柱，其中該源極立柱和該汲極立柱為一第一導電類型，向下延伸穿過該超級接面結構；一第二導電類型的一閘極立柱，向下延伸穿過該超級接面結構，以便在該超級接面結構上載入電壓，以控制在該源極和該汲極立柱之間，橫向穿過該超級接面結構的電流；以及該半導體基體更包括一第一導電類型的底部半導體層，其中該汲極立柱向下延伸，連接到該底部半導體層；該半導體基體更包括：一第二導電類型的中間半導體層，該中間半導體層設置在該超級接面結構下方，以及在該底部半導體層上方；其中，該閘極立柱向下延伸到該中間半導體層中，構成一個由從該底部半導體層，穿過該中間半導體層，到達該閘極立柱的組合所形成的嵌入式閘極-汲極雪崩箝位二極體。
  2. 如申請專利範圍第1項所述之半導體功率元件，其中，該閘極立柱延伸深度大於該源極立柱。
  3. 如申請專利範圍第1項所述之半導體功率元件，其中，該源極、該汲極和該閘極立柱構成一JFET，該半導體功率元件更包括： 與該JFET一起連接成級聯電路結構的一MOSFET。
  4. 如申請專利範圍第3項所述之半導體功率元件，其中，該MOSFET更包括一源極區和一閘極，配置該MOSFET之該閘極，以便在該MOSFET之該源極區和該源極立柱之間，構成一反轉通道。
  5. 如申請專利範圍第1項所述之半導體功率元件，其中，該源極、該汲極和該閘極立柱設置成條紋，穿過該半導體基體水準延伸。
  6. 如申請專利範圍第1項所述之半導體功率元件，其中，將該源極、該汲極和該閘極立柱構成一封閉元件佈局結構，穿過該半導體基體的水準方向。
  7. 一種半導體功率元件，包括：一含有超級接面結構的半導體基體，該超級接面結構設置在該半導體基體的頂面附近，其中該超級接面結構是由複數個第一和第二導電類型交替的橫向堆積層構成的，從一源極立柱橫向延伸到一汲極立柱，其中該源極立柱和該汲極立柱為一第一導電類型，向下延伸穿過該超級接面結構；一第二導電類型的一閘極立柱，向下延伸穿過該超級接面結構，以便在該超級接面結構上載入電壓，以控制在該源極和該汲極立柱之間，橫向穿過該超級接面結構的電流；以及該半導體基體更包括一第一導電類型的底部半導體層，其中該汲極立柱向下延伸，連接到該底部半導體層；該半導體基體更包括：一第二導電類型的中間半導體層，該中間半導體層設置在該超級接面結構下方，以及在該底部半導體層上方；其中，該源極立柱延伸到該中間半導體層中，該源極立柱更包括： 一在中間半導體層中的雙極抑制區，位於該源極立柱底部；以及該雙極抑制區摻雜了該第二導電類型。
  8. 如申請專利範圍第7項所述之半導體功率元件，其中，該閘極立柱延伸深度大於該源極立柱。
  9. 如申請專利範圍第7項所述之半導體功率元件，其中，該源極、該汲極和該閘極立柱構成一JFET，該半導體功率元件更包括：與該JFET一起連接成級聯電路結構的一MOSFET。
  10. 如申請專利範圍第9項所述之半導體功率元件，其中，該MOSFET更包括：一源極區和一閘極；配置該MOSFET之該閘極，以便在該MOSFET之該源極區和該源極立柱之間，構成一反轉通道。
  11. 如申請專利範圍第7項所述之半導體功率元件，其中，該源極、該汲極和該閘極立柱設置成條紋，穿過該半導體基體水準延伸。
  12. 如申請專利範圍第7項所述之半導體功率元件，其中，將該源極、該汲極和該閘極立柱構成一封閉元件佈局結構，穿過該半導體基體的水準方向。
  13. 一種半導體功率元件，包括：一含有超級接面結構的半導體基體，該超級接面結構設置在該半導體基體的頂面附近，其中該超級接面結構是由複數個第一和第二導電類型交替的橫向堆積層構成的，從一源極立柱橫向延伸到一汲極立柱，其中該源極立柱和該汲極立柱為一第一導電類型，向下延伸穿過該超級接面結構；一第二導電類型的一閘極立柱，向下延伸穿過該超級接面結構，以便在該超級接面結構上載入電壓，以控制在該源極和該汲極立柱之間，橫向穿過該超級接面結構的電流；以及該半導體基體更包括一第一導電類型的底部半導體層，其中該汲 極立柱向下延伸，連接到該底部半導體層；該半導體基體更包括：一第二導電類型的中間半導體層，該中間半導體層設置在該超級接面結構下方，以及在該底部半導體層上方；該源極、該汲極和該閘極立柱構成一JFET，該半導體功率元件更包括：與該JFET一起連接成級聯電路結構的一MOSFET；其中，該MOSFET在元件的單元層級上與該JFET整合；其中，該MOSFET更包括：一源極區、一本體區、一閘極和一汲極區，其中該源極區沿平行於該源極立柱的方向延伸，並被設置在該源極區和該源極立柱之間的該本體區分開。
  14. 如申請專利範圍第13項所述之半導體功率元件，其中，配置該MOSFET之該閘極，以便在該MOSFET之該源極區和該源極立柱之間，構成一反轉通道。
  15. 如申請專利範圍第13項所述之半導體功率元件，其中，該源極、該汲極和該閘極立柱設置成條紋，穿過該半導體基體水準延伸。
  16. 一種半導體功率元件，包括：一含有超級接面結構的半導體基體，該超級接面結構設置在該半導體基體的頂面附近，其中該超級接面結構是由複數個第一和第二導電類型交替的橫向堆積層構成的，從一源極立柱橫向延伸到一汲極立柱，其中該源極立柱和該汲極立柱為一第一導電類型，向下延伸穿過該超級接面結構；一第二導電類型的一閘極立柱，向下延伸穿過該超級接面結構，以便在該超級接面結構上載入電壓，以控制在該源極和該汲極立 柱之間，橫向穿過該超級接面結構的電流；以及該半導體基體更包括一第一導電類型的底部半導體層，其中該汲極立柱向下延伸，連接到該底部半導體層；該半導體基體更包括：一第二導電類型的中間半導體層，該中間半導體層設置在該超級接面結構下方，以及在該底部半導體層上方；其中，將該源極、該汲極和該閘極立柱構成一封閉元件佈局結構，穿過該半導體基體的水準方向；其中，所形成的該源極立柱位於沿該封閉元件佈局結構的週邊，所形成的該汲極立柱位於每個元件的中心。
  17. 如申請專利範圍第16項所述之半導體功率元件，其中，該閘極立柱在該源極立柱的旁邊交錯設置。
  18. 一種製備一個半導體功率元件的方法，其包括：製備一第一導電類型的底部半導體層，以及在該底部半導體層上方製備一第二導電類型的中間半導體層，然後藉由製備一第一和一第二導電類型交替的橫向堆積層，在一半導體基體的頂面附近，形成一超級接面結構；製備一第二導電類型的閘極立柱，穿過該超級接面結構向下延伸；製備第一導電類型的一源極立柱和一汲極立柱，穿過該超級接面結構，該汲極立柱穿過該超級接面結構延伸，電連接到該底部半導體層；以及製備該中間半導體層、該底部半導體層和該閘極立柱，以便形成一從閘極立柱穿過該中間半導體層，到達該底部半導體層的嵌入式閘極-汲極雪崩箝位二極體。
  19. 如申請專利範圍第18項所述之方法，其中，製備該超級接面結構的步驟更包括：藉由外延生長，在該中間半導體層上方，製備該超級接面結構。
  20. 如申請專利範圍第18項所述之方法，其中，製備該源極立柱的步驟包括：製備到達該中間半導體層的該源極立柱，並在該源極立柱底部的該中間半導體層中，形成一第二導電類型的雙極抑制區。
  21. 如申請專利範圍第18項所述之方法，其中，製備該源極、該汲極或該閘極立柱的步驟包括：在該半導體基體中蝕刻溝槽，然後將溝槽的側壁內襯具有第一或第二導電類型的半導體材料。
  22. 如申請專利範圍第21項所述之方法，其中，內襯側壁的步驟更包括：摻雜在溝槽中裸露部分的該半導體基體。
  23. 如申請專利範圍第21項所述之方法，其中，內襯側壁的步驟更包括：在溝槽的側壁上，沉積預定導電類型的多晶矽。
  24. 如申請專利範圍第21項所述之方法，其更包括：用絕緣材料或導體材料填充剩餘的溝槽。
  25. 如申請專利範圍第18項所述之方法，其更包括：將該源極、該閘極和該汲極立柱配置成一JFET；以及在該半導體元件中製備一MOSFET與該JFET成級聯電路結構。
  26. 一種半導體功率元件，包括：一含有一超級接面結構的半導體基體，該超級接面結構設置在該半導體基體的頂面附近，其中，該超級接面結構是由複數個第一 和第二導電類型交替的橫向堆積層構成的，從一源極立柱橫向延伸到一汲極立柱，其中，該源極立柱和該汲極立柱為第一導電類型，向下延伸穿過該超級接面結構；一第二導電類型的閘極立柱，向下延伸穿過該超級接面結構，以便在該超級接面結構上載入電壓，以控制在該源極和該汲極立柱之間，橫向穿過該超級接面結構的電流；以及該半導體基體更包括一第一導電類型的底部半導體層和一第二導電類型的中間半導體層，該中間半導體層設置在該超級接面結構下方，以及在該底部半導體層上方；其中，該閘極立柱經由該中間半導體層與該底部半導體層形成一雪崩二極體。
  27. 如申請專利範圍第24項所述之半導體功率元件，其更包括：至少一該閘極立柱和該汲極立柱向下延伸，電連接到該底部半導體層。
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