CN103794653B - 带有很高的衬底-栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件 - Google Patents

带有很高的衬底-栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件 Download PDF

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CN103794653B
CN103794653B CN201310377546.4A CN201310377546A CN103794653B CN 103794653 B CN103794653 B CN 103794653B CN 201310377546 A CN201310377546 A CN 201310377546A CN 103794653 B CN103794653 B CN 103794653B
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jfet
column
drain
source electrode
grid
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CN103794653A (zh
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马督儿·博德
管灵鹏
安荷·叭剌
哈姆扎·依玛兹
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明公开了一种带有很高的衬底‑栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件，在位于N+衬底上的P‑外延层上方，通过堆积式交替的P型和N型半导体层，构成一个横向超级结JFET。N+漏极立柱向下延伸，穿过超级结结构和P‑外延层，连接到N+衬底，从而构成一个底部漏极器件。N+源极立柱和P+栅极立柱穿过超级结延伸，但是在P‑外延层终止。从底部P+栅极立柱开始，穿过P‑外延层，到N+漏极衬底，形成一个栅极‑漏极雪崩箝位二极管。

Description

带有很高的衬底-栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件
本案是分案申请
原案发明名称：带有很高的衬底-栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件
原案申请号：201010576533.6
原案申请日：2010年11月29日。
技术领域
本发明主要涉及半导体功率器件。更确切地说，本发明是涉及制备横向功率器件的结构和方法，该器件含有一个超级结结构，带有形成在漏极衬底和栅极之间的雪崩箝位二极管。这种横向超级结结构降低了导通电阻，同时结构上的改进提高了衬底和漏极之间的击穿电压，改善了非箝位感应开关（UIS）性能。
背景技术
MOSFET功率器件等传统的带有超级结结构的半导体功率器件，可以在维持高击穿电压的同时，显著降低导通电阻，从而获得性能上的提高。但是，要在MOSFET器件中制备超级结结构的制备技术和器件结构，仍然面临许多制备能力上的难题。用于高压应用的带有超级结结构的传统的垂直功率器件，由于它们的结构特点需要许多费时、复杂和昂贵的制备工艺，在制备能力和成本上仍然有所局限。按照目前方法的制备工艺要制成垂直结构，包括很多连续的掩膜、植入和外延生长过程。由于制备高密度的交替掺杂立柱会直接增加制备步骤，因此不可能完成。要制备高密度的这种立柱，太多的因素会影响相邻的交替掺杂立柱之间的电荷平衡的准确性，导致很窄的工艺范围。Tatsuhiko Fujihira在《日本应用物理学杂志36（1997）》6254-6262页发表的题为“半导体超级结器件的理论”的论文中揭露，图1A表示MOSFET垂直超级结器件的一种典型设计。要制备图1A所示的垂直电荷平衡的交替掺杂立柱，不仅困难而且成本昂贵，高密度时尤其如此。
基于上述原因，带有超级结结构的横向JFET功率器件，伴有交替掺杂导电类型的堆积式水平层形成，克服了这些困难。这种器件可以与低压MOSFET配置级联，实现了传统器件的常闭操作。Coe在专利US 4,754,310中，提出了带有电荷平衡的超级结结构的横向功率器件，配置交替导电类型的堆积式水平层延伸到源极和漏极立柱之间。有效地制备堆积式水平层的这种结构无需使用掩模。但是，如图1B所示的典型器件配置受到漏极-衬底击穿电压的限制，以及来自难以提高非箝位感应开关（UIS）的进一步限制。图1C表示Tatsuhiko Fujihira在上述《半导体超级结器件的理论》一文中提出的另一种横向超级结器件的示例。这种器件将电流分布到堆积式n-型导电路径中时，要承载过多的通道电阻。
因此，在功率半导体器件的设计和制备工艺中，仍然有必要提出形成横向功率器件的新颖的器件结构和制备方法，从而使上述困难与局限得以解决。
发明内容
因此，本发明的一个方面是提出了一种在P-外延层上形成结型场效应管（JFET）和MOSFET功率器件的新型的、改良的器件结构和制备方法，P-外延层蚀刻中间半导体层，在N衬底上方，构成带有在N型深立柱之间延伸的横向超级结结构的底部半导体层，起源极和漏极立柱的作用，P+深立柱蚀刻JFET栅极。在这个结构中，将漏极端移动到衬底，以便将两个高电流端分开，将两个平面分开，更好地分布电流。可以通过使漏极沟槽的深度比源极和栅极更深，实现上述目的，从而使漏极端穿过P外延区，触及N+衬底。这种结构还会产生凹的或鞍状的N+漏极衬底-P-外延N+漏极立柱结，获得高衬底闭锁电压。另外，从N＋漏极衬底到P-外延层，一直到P＋栅极立柱，所形成的N+-P-P+栅极-漏极雪崩箝位二极管，蚀刻强大的高压二极管，将雪崩电流转移出该器件的超级结层。
本发明的另一方面在于，提出了一种带有低压MOSFET与超级结JFET集成结构的常闭的半导体功率器件的新型的、改良的器件结构和制备方法。低压MOSFET设置在器件表面附近，具有可以获得制备常闭开关所需的级联连接的结构。
阅读以下较佳实施例的详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1A表示一种垂直超级结功率器件的传统结构的横截面视图。
图1B表示传统的横向功率器件的横截面视图。
图1C表示传统的横向超级结功率器件的横截面视图。
图2表示本发明所述的横向超级结功率器件的横截面视图。
图3A至3N表示本发明所述的横向超级结功率器件的制备方法的一系列横截面视图。
图3A-1至3C-1表示制备本发明所述的横向超级结功率器件的可选方法的一系列横截面视图。
图4A至4C表示本发明所述的集成横向超级结结构的MOSFET的可能布局的俯视图。
图5A至5B表示本发明所述的集成横向超级结结构的MOSFET的透视图的横截面。
图5C表示图5A和5B所示器件的俯视图。
图5D至5F表示沿图5B的A-A、B-B和C-C截面线的横截面视图。
图6A表示本发明所述的横向超级结JFET的条纹结构的俯视图。
图6A-1至6A-3表示沿图6A所示的D-D和E-E截面线的横截面视图。
图6B和图6C表示图6A所示的MOSFET 与JFET的集成方式的俯视图。
图6C-1表示沿图6C所示的F-F截面线的横截面视图。
图6D表示条纹结构中的JFET的多行俯视图。
图7A表示本发明所述的横向超级结JFET的封闭元件结构的俯视图。
图7A-1表示沿图7A所示的G-G截面线的横截面视图。
图7B和7C表示图7A所示的MOSFET 与JFET的集成方式的俯视图。
图7C-1表示沿图7C所示的H-H截面线的横截面视图。
图8A至8Q表示MOSFET 与本发明所述的横向超级结JFET的集成方式的一系列横截面视图。
具体实施方式
图2表示本发明所述的具有底部漏极衬底的横向超级结高压（HV）JFET器件100的横截面视图。该横向JFET器件100支撑于作为漏极的N＋衬底105上的P-外延层115，以及可选的N＋衬底105上的N缓冲区106。横向JFET器件100含有一个设置在衬底105底部上的漏极金属电极110。横向功率器件100还包括一个N源极立柱120-S和N漏极立柱120-D，分别作为第一和第二导电立柱，设置在第一沟槽和第二沟槽中，并且分别位于衬底的两个相对边上。在本实施例中，这些源极和漏极沟槽都包括被N＋掺杂区125包围着的沟槽中的导电材料（例如金属填充物或多晶硅）。当然，也可以使用其他方法制备N＋漏极和源极立柱120-D和120-S。N＋源极立柱120-S通过氧化物107的开口，接触顶面上的源极金属120-S-M。设置在沟槽中的漏极120-D，向下延伸接触N＋漏极衬底层105。源极沟槽向下蚀刻到P外延层115中。P＋掺杂区165设置在源极120-S下方，以便抑制寄生NPN双极晶体管的激活，该寄生晶体管从N＋源极立柱120-S到P-外延层115，一直到N＋衬底105。P-外延层115中重掺杂的P＋区165，大幅降低了少数载流子的寿命，从而抑制了寄生NPN晶体管。
横向JFET器件100还包括一个P＋掺杂立柱130，设置在另一个沟槽中，当作该横向功率器件的栅极。与N＋源极和漏极立柱120-S和120-D类似，P＋栅极立柱130也是由被P＋掺杂区135包围着的沟槽构成，该沟槽由金属或多晶硅填充。进一步设计P＋栅极立柱130和P-外延层115，以及可选的N-缓冲区106，制成雪崩二极管121，以便箝制击穿电压。超级结器件通常难以抵御雪崩击穿带来的损害。如果雪崩击穿发生在电荷平衡区中，雪崩电流会在起始的小区域内聚集并放大，对该区域造成永久性地损坏。雪崩二极管121将雪崩电流路径转移出电荷平衡的超级结区域，使它改道流经P＋栅极立柱130和N＋漏极层105之间，从而提高了器件的稳健性。P＋栅极立柱130连接到顶面上的栅极金属130-M。源极和漏极120-S和120-D也可以由N＋掺杂的多晶硅构成，多晶硅填充在沟槽中，或者由金属插头构成，金属插头填充在带有N＋掺杂侧壁的沟槽中。也可选择，通过外延生长填充沟槽，或者通过其他方法制备沟槽。关键是要用N＋掺杂的半导体材料构成沟槽的侧壁。
横向功率器件具有一个超级结结构，由多层相互交替的水平的掺杂层140和N掺杂层150形成。这些相互交替的P掺杂层和N掺杂层，在源极120-S和漏极120-D之间，提供多个电荷平衡的导电通道。电流沿着横向传导，栅极130控制、导通/关闭功率器件。图1中的栅极130设置在与源极和漏极不同的平面，因此不会切断在超级结结构中伴随有相互交替的N和P掺杂层所形成的横向通道。栅极立柱130和源极立柱120-S应该比超级结结构还深，以便接触P外延层115。栅极立柱130的深度可以与源极立柱120-S相同，或者比源极立柱120-S还深。形成栅极立柱130的深度大于源极立柱120-S的话，有助于将雪崩电流引导到栅极立柱130和雪崩二极管121上，而不是传输到源极立柱120-S下面的寄生NPN晶体管上。横向超级结JFET器件100的电路图，表示出了器件终端的漏极金属110、源极金属120-S-M以及栅极金属130-M。雪崩二极管121形成在栅极和漏极之间。
图3A至3N表示本发明所述的横向超级结的JFET器件的制备过程的一系列横截面视图。图3A表示P-外延层215支撑于P＋衬底205上，P-外延层215的掺杂浓度和层厚能够阻挡600伏的电压。例如可以通过利用美国申请案12/592,619中的图10至12所示的一个工艺，使交替的P和N掺杂层240和250分别形成在P-外延层215的上方，形成电荷平衡层。在图3B中，形成硬掩膜层222，例如可以通过热氧化过程，生长一层厚约205埃的氧化层，然后通过沉积氧化物，形成厚氧化层，作为硬掩膜层222。利用光致抗蚀剂掩膜，蚀刻穿过硬掩膜222形成开口223。在图3C中，利用硅蚀刻工艺，打开栅极沟槽225，栅极沟槽225垂直穿过交替的P和N掺杂层240和250的超级结结构，延伸到P-外延层215，栅极沟槽225的深度约为60微米，宽度约为10微米。为了便于制备该器件，栅极沟槽225可以带有88度的轻微斜度。在图3D中，将带有硼离子的P＋植入到栅极沟槽中，形成P＋区230，包围着栅极沟槽225。仅作示例，硼植入物的植入能量可约为40keV，浓度约为5E15 cm-2，倾斜角约为7度，作四次90度旋转，然后用相同的离子流量进行垂直的硼离子植入。在图3E中，首先在栅极沟槽225的侧壁和底面上，形成多晶硅衬里层235，然后将氧化层241填充到栅极沟槽中。还可以向多晶硅层中掺杂P＋，以降低栅极沟槽的电阻。然后，通过多晶硅和氧化物回刻，除去顶面上方的多晶硅和氧化物。虽然多晶硅层235是任选的，但是在回刻或化学机械抛光（CMP）氧化层241时，它可以蚀刻一个合适的终点。也可以非掺杂地沉积多晶硅235 ，然后用来自P＋层230的P型掺杂物扩散到多晶硅235中。
在图3F中，第二氧化层222’沉积在第一氧化层222上方。在图3G中，利用源极掩膜，通过氧化层222和222’打开沟槽开口224。在图3H中，通过超级结结构，将源极沟槽245-S蚀刻到能够触及P-外延层215的深度。在一个实施例中，沟槽的深度约在40至44微米之间，宽度约为10微米。无论如何，源极沟槽245-S都应在P-外延层215中终结。然后，制备工艺继续进行，通过带角度的N＋植入（大约7度倾斜角）以及垂直N＋植入，形成N＋区255，包围着沟槽245-S的侧壁和底部。在图3I中，利用垂直P＋植入，在沟槽245-S的底部形成P＋区265。在图3J中，首先沉积Ti/TiN层260覆盖侧壁、沟槽的底面以及氧化物222’的顶面上方。然后，沉积一个6-8微米的厚金属层251，填充沟槽245-S。通过化学机械抛光（CMP）工艺，除去金属层251和Ti/TiN层260的顶部，以便形成平整的顶面。在图3K中，利用漏极沟槽掩膜，在半导体材料中蚀刻漏极沟槽245-D，例如通过氧化物蚀刻和硅蚀刻。漏极沟槽245-D向下穿过超级结结构和P-外延层215，到达N＋衬底245。N＋区255-1沿着漏极沟槽245-D的侧壁形成。另一个Ti/TiN层260-1形成在沟槽的侧壁上，如果形成了金属251-1，那么就将其置于Ti/TiN层260-1上。如图2L所示，可以在金属251-1上方进行化学机械抛光。第二金属层沉积在顶面上方，覆盖着Ti/TiN层260的上方。在沉积金属层270之前，可以选择沉积另一个Ti/TiN层261。如图3M所示，利用金属掩膜，将金属层形成源极金属270-S、栅极金属（图中没有表示出）或有顶部漏极金属（图中没有表示出）的图案。栅极230可以在第三个维度上，连接到栅极金属（图中没有表示出）上。在图3N中，例如由标准的二氧化硅/氮化物/聚酰亚胺堆积构成的钝化层280，然后利用钝化掩膜形成钝化层280的图案，使源极金属270-S裸露出来。通过背部研磨操作，以及背部金属化工艺，在P＋衬底205的底面上形成一个底部漏极金属层290，完成整个制备过程。
对于熟练本技术的人而言，本发明所述的横向超级结JFET的形成显然还有很多可选方法。例如，有许多制备栅极、漏极和源极立柱的方法。
一种可选方法从图3A-1开始，首先在单一的P-型衬底215’上形成超级结结构——P型衬底215’与图3A所示的P-外延层215类似，但不包含N＋衬底205。一直到背部研磨之前的所有制备过程都与之相同。此时，如图3B-1所示，P-型衬底215’的背面研磨到或接近漏极沟槽245-D的底部。可以通过将N＋掺杂离子植入到器件的背面，形成N＋漏极205’，N+漏极205’连接到漏极沟槽245-D上，可以形成背部漏极金属290。其他可选技术将在本说明书中稍后进行说明。
JFET是一种常态导通器件。在许多应用中，人们更愿意选择常态断路功率开关，而不是常态导通功率开关，其原因包括器件在电路启动时是关闭的、与已有的设计兼容、更加熟悉等。图4A-4C表示本发明所述的将低压MOSFET与高压横向超级结JFET一起集成在一个单一的半导体晶片上的三种可能的布局。MOSFET可以在级联结构中，与JFET排列在一起，就像图4A中所示的电路那样，以便构成一个常态导通的功率开关器件。在图4A中，半导体晶片390A含有本发明所述的高压横向超级结JFET 391A以及低压MOSFET区392A。在图4B中，三个MOSFET区392B分布在整个单一的大型JFET区391A上，以降低晶片390B中的封装电阻和电感。在图4C中，MOSFET 392C集成在晶片390C中的JFET 391C的器件元件等级上。如图4C所示，MOSFET 392C与JFET 391C的每个元件集成。MOSFET和JFET可以在级联结构中，内部和/或外部互联。低压MOSFET是本领域中被人们所熟知的器件，可以转化成任何形式，包括横向MOSFET、垂直MOSFET、沟槽栅极、平面栅极等等，而且在级联电路结构中，将MOSFET连接到JFET上也有很多不同的封装方式。
当然，MOSFET也可以与本发明所述的横向超级结JFET共同封装在一个具有分立的MOSFET和超级结JFET半导体晶片的单一封装中。该半导体晶片可以并排共同封装，或在一个堆积式结构中共同封装。
图5A表示本发明所述的MOSFET 470与高压横向超级结JFET 400集成的透视图的横截面。在本实施例中，MOSFET 470集成在每个JFET 400元件中，就像图4C所示的布局中那样。在本布局中，横向低压MOSFET 470位于第三维度上，垂直于横向超级结JFET 400的平面通道方向。JFET 400的结构与图2所示的横向超级结JFET 100的结构类似。在这些图中，JFET N＋漏极和源极立柱以及JFET P＋栅极立柱分别用简单的N和P掺杂立柱（420-D、420-S、430）表示。掺杂立柱420-D、420-S和430的工作方式与JFET 100的N和P立柱的工作方式相同。在本实施例中，MOSFET 470是由P本体区472中的N＋源极区471构成。MOSFET N＋源极471也兼任级联电路的总源极。MOSFET 470还包括氧化物475中的平面栅极473，平面栅极473兼任级联电路的总栅极。MOSFET 470的N＋漏极也兼任JFET 400的N＋源极立柱420-S。JFET 400的横向超级结结构包括电荷平衡的交替堆积式P层440和N层450，构成横向超级结漂流区，从JFET N＋源极立柱420-S延伸到JFET N＋漏极立柱420-D。超级结结构位于N＋漏极衬底405上方的P外延层415上。漏极立柱420-D向下延伸到N＋漏极衬底405。漏极金属410可以位于N＋漏极衬底405下方。JFET N＋漏极立柱420-D（和N＋漏极衬底405以及漏极金属410）兼任级联电路的总漏极。JFET 400由JFET P＋栅极立柱430控制，JFET P＋栅极立柱430穿过超级结P和N层440和450，向下延伸到P-外延层415。按照该级联电路，JFET P＋栅极立柱430通过源极金属488，短接到MOSFET N＋源极区471上。依据本发明，所形成的雪崩二极管421，从JFET P＋栅极立柱430穿过P-外延层415到N＋漏极衬底405。雪崩二极管421将雪崩电流转移远离由电荷平衡交替堆积的N和P层450和440构成的超级结结构。
正如电路图中所示的那样，MOSFET （MOS） 470在级联结构中连接到超级结JFET 400上。MOS 470的漏极与JFET源极420-S相连。JFET 栅极430连接到MOS源极471上。依据本发明，横向超级结JFET 400还包括一个位于其栅极430和漏极420-D之间的雪崩二极管421。
尽管图5B与图5A相同，但它标示出图5D-5F所示的垂直横截面的位置。图5D表示A-A横截面，源极金属488连接到MOS N＋源极471和JFET P＋栅极立柱430上。源极金属488在第三维度上还连接MOS P本体472。图5E表示B-B横截面，N＋ JFET源极立柱420-S以及N＋ JFET漏极立柱420-D。尽管P＋ JFET栅极立柱430是在第三维度上，但是横截面B-B表示出了横向超级结JFET 400。在N＋ JFET源极立柱420-S下面形成P＋植入物，以抑制从N＋源极立柱420-S到P-外延层415，一直到N＋漏极衬底405所产生的寄生NPN晶体管。图5F表示C-C横截面，示出低压MOSFET 470。MOSFET是被人们所熟知的器件，显然，也可形成其他等效的器件结构将MOSFET与本发明所述的横向超级结JFET集成起来。
图5C表示图5A和5B所示的横向超级结JFET 400与MOSFET 470集成起来的俯视图。为清晰起见，图中没有表示出顶部绝缘层。源极金属488的轮廓由虚点线表示。虚线表示接触开口489的轮廓，用于使源极通过氧化物475（图中没有表示出），接触N＋ MOS源极区471和P＋ JFET栅极立柱430。MOS栅极473使通道形成在下方的本体区472（图中没有表示出）中，从N＋ MOS源极区471到N＋ MOS漏极区/JFET源极立柱420-S。多晶硅栅极浇道477将栅极473连接在一起。电流可以从N＋ JFET源极立柱420-S开始，穿过超级结结构（顶部P层440下方的N层450），到达N＋ JFET漏极立柱420-S。根据级联结构，JFET P＋栅极立柱430在接触开口489处，短接到MOS N＋源极区471上，当MOS栅极473关闭时，为器件提供高压闭锁。
图6A表示本发明所述的底部漏极横向超级结JFET 500的俯视图。图6A表示的是条纹结构中的JFET 500。它具有N＋ JFET源极立柱520-S，形成一个条纹。P＋ JFET栅极立柱530沿着N＋ JFET源极立柱520-S条纹断断续续地形成，就像一个虚条纹。P＋ JFET栅极立柱530相互错开，使得从N＋ JFET源极立柱520-S到N＋JFET漏极立柱520-D的电流路径可导通。图6A的D-D横截面由图6A-1表示。P-外延层515位于N＋衬底505上。P-外延层上方，交替堆积的P层540和N层550构成横向超级结结构。为P层540和N层550选择合适的掺杂浓度和厚度，使它们达到电荷平衡。N层550形成从N＋ JFET源极立柱520-S到N＋ JFET漏极立柱520-D的横向通路。断路时P＋ JFET栅极立柱530夹断电流。N＋ JFET漏极立柱520-D向下延伸到N＋漏极衬底505，形成底部漏极器件。P＋区565可以形成在N＋JFET源极立柱520-S的下方，以抑制从N＋源极立柱520-S到P-外延层515，一直到N＋衬底505，所形成的寄生NPN双极晶体管。依据本发明，从P＋栅极立柱530到N＋衬底（经由P-外延层515），也可以形成雪崩二极管521。
如图6A-2的E-E横截面所示，独立的栅极立柱530也可以同浅P＋表面植入物541连接在一起。也可选用金属条纹将P＋栅极530连接到顶部。图6A-3表示一个完整的JFET 500-3，从图6A的D-D横截面来看，源极金属和栅极金属在上面，漏极金属在底部。源极金属521连接N＋ JFET源极立柱520-S，栅极金属通过厚介质层544（例如氧化物或含有硼磷的硅玻璃BPSG）中的开口，连接P＋ JFET栅极立柱530。漏极金属510形成在N＋衬底505的底部。
低压MOSFET也可以与横向超级结JFET 500集成，以便与超级结JFET在同一平面上。MOSFET可以在级联电路中连接到JFET 500上，使整个器件成为一个常态断路器件。图6B表示图6A之后制备MOSFET的下一步——在器件上方制备MOS栅极电极573（例如多晶硅）。薄栅极氧化物（图6B中没有表示出）使MOS栅极573与半导体表面绝缘。
然后，在器件上方植入N＋ MOS源极571以及N＋ MOS漏极575区，并且自对准到MOS栅极573。如图6C的俯视图所示，形成P MOS本体区572，自对准到MOS栅极573。P＋ JFET栅极立柱530和N＋ JFET源极立柱520-S如图中虚线所示。
图6C-1表示图6C的F-F横截面。N＋ MOS源极571位于P MOS本体区572中，它们都自对准到MOS栅极573。薄栅极电介质574（例如栅极氧化物）将MOS栅极573与半导体表面分开。在MOS栅极573的另一侧，所形成的N＋ MOS漏极575也自对准到MOS栅极573。依据级联电路结构，N＋ MOS漏极575连接到N＋ JFET源极立柱520-S上。源极金属580，通过厚介质层576中的开口，连接N＋ MOS源极571和MOS P本体572。MOS P本体572连接P＋ JFET栅极立柱530，因此，依据级联电路结构，MOS的源极和JFET的栅极也连接在一起。于是，电流受MOS栅极573的控制，从N＋ MOS源极571，流至N＋ MOS漏极575。电流可以从N＋ MOS漏极575，继续穿过N＋ JFET源极立柱520-S，到超级结N层550，横向流至N＋ JFET漏极520-D。在级联结构中，P＋ JFET栅极530短接到N＋源极571上，因此当MOSFET导通时，JFET栅极530的电势与JFET源极520-S（以及MOS漏极757）的电势基本相同，从而使电流流经N层550。电流可以向下通过N＋ JFET漏极立柱520-D，流至N＋漏极衬底505，并到达漏极金属510下面。当MOSFET断路时，JFET栅极530的电势低于JFET源极520-S/MOS漏极575，从而切断电流，下文还将详细说明。除去MOS栅极573偏压，可断开低压MOSFET。在这种情况下，给漏极终端510加载正向偏压，将在N层550上产生正向偏压，在JFET P栅极530上产生相应的反向偏压，导致超级结N层550和P层540以及P-外延层515耗尽。在一定的漏极偏压下，相邻的P层540的耗尽区会合并，夹断JFET源极立柱520-S，不受多余的漏极电压的影响。这使得器件漏电流很低，可以闭锁高压。而且由于JFET夹断后可以承受额外电压，则可以在级联电路中，使用低压MOSFET。 当P外延区515在高漏极偏压下耗尽时，它所产生的电荷降低了P＋栅极530下方的峰值电场，使器件结构具有很高的衬底击穿电压。尽管本文没有阐述，但是MOS栅极573也可以连接到位于半导体芯片的另一部分上的栅极金属端上。
如图6D所示，源极和漏极条纹结构和布局可以在整个半导体晶片上重复。
图7A表示封闭元件结构的一种可选布局的俯视图。更确切地说，它表示的是六边形封闭元件结构。基本的横向超级结JFET 500’结构的俯视图如图7A所示，横截面视图如图7A-1所示。N＋ JFET源极立柱520’-S位于一个互联的六边形网络中。在N＋ JFET源极立柱520’-S旁边的是P＋ JFET栅极立柱530’。P＋ JFET栅极立柱530’相互错开，使电流流经它们之间。每个六边形的中心是N＋ JFET栅极立柱520’-D。如图7A-1的横截面视图所示，JFET元件位于电荷平衡的堆积式P层540和N层550的超级结结构中，P层540和N层550位于N＋衬底505上方的P-外延层515上方。在每个六边形封闭元件中，电流从六边形边缘处的N＋ JFET源极立柱520’-S开始，横向穿过超级结N层550，流至六边形中心处的N＋ JFET漏极立柱520’-D。然后，电流向下穿过N＋漏极立柱520’-D到达N＋衬底505。在N＋ JFET源极立柱520’-S下方形成一个NPN抑制P＋区，并从P＋ JFET栅极立柱530’到N＋衬底505，形成一个雪崩二极管521’。
类似图6A-6D所示的条纹结构，可以在级联电路结构中，轻松地将MOSFET与图7A所示的JFET 500’集成起来，如图7B-7C所示。在7B所示的俯视图中，可见一个单一的六边形封闭元件的全貌，MOS栅极电极573’的网络形成在晶片顶部上方。MOS栅极573’在N＋ JFET源极立柱520’-S的旁边。
在图7C所示的俯视图中，所形成的N＋ MOS源极571’和N＋ MOS漏极575’区自对准到MOS栅极573’。 形成P MOS本体区572’，自对准到MOS栅极573’，包围着N＋ MOS源极区571’。 N＋ JFET源极立柱520’-S和 P＋ JFET栅极立柱530’的轮廓如图中虚线所示。如图7C-1的H-H横截面所示，源极金属580’通过厚电介质576’中的开口，接触N＋ MOS源极571’和P MOS本体572’。依据级联电路，源极金属580’也通过P MOS本体572’，连接到P＋ JFET栅极立柱530’上。N＋ MOS漏极575’形成在MOS栅极573’的另一边。薄栅极电介质574’将MOS栅极573’与半导体表面绝缘。依据级联电路结构，N＋ MOS漏极575’连接到N＋ JFET立柱520’-S上。
图8A-8Q表示MOSFET与本发明所述的横向超级结JFET的集成在一起的制备方法的一系列横截面视图。制备过程从图8A开始，制备一个由交替堆积的电荷平衡的P型层740和N型层750制成的横向超级结结构。该横向超级结结构形成在P-外延层715上方，P-外延层715形成在N＋衬底705上方。
然后，在上方制备一个硬掩膜722（例如氧化物）并形成图案。如图8B所示，在半导体材料中蚀刻栅极沟槽725。栅极构成725向下穿过横向超级结结构，延伸到P-外延层715。在图8C中，栅极沟槽725内衬有P+植入（例如通过带角度的植入），形成P+栅极立柱730。在图8D中，形成第二硬掩膜726，并形成图案。第二硬掩膜材料也可以填充在栅极沟槽725中（例如通过氧化物填充727）。源极沟槽745-S和中间的漏极沟槽745-D蚀刻到半导体材料中，穿过P层740和N层750的横向超级结结构，到达P-外延层715。中间的漏极沟槽745-D比源极沟槽745-S窄得多。将源极沟槽745-S的侧壁和中间的漏极沟槽745-D植入N型，构成N型源极立柱720-S和中间的N型漏极立柱720-D。在图8E中，沿源极沟槽745-S的侧壁，形成的N+多晶硅垫片752。仅作示例，多晶硅垫片752的制备，可以通过沉积一层多晶硅，然后各向异性地蚀刻多晶硅层，在源极沟槽745-S中留下多晶硅垫片752。制备多晶硅垫片752的过程，还包括将N+多晶硅填充物753填充在较窄的中间漏极沟槽745-D中。在图8F中，利用垂直P+植入，在源极沟槽745-S底部的P-外延层715中，形成P+区765。P+区765抑制了从N源极立柱720-S到P-外延层，一直到N衬底705，所形成的寄生NPN晶体管。
在图8G中，在器件上方沉积氧化物723，并使其平整。再将氧化物填充到源极沟槽745-S的剩余空间中。利用第三掩膜，形成氧化物723的图案，在将要形成MOSFET的区域中，将氧化物723向下蚀刻到半导体材料的平面。在裸露的半导体材料上形成薄栅极氧化物774，然后形成栅极多晶硅773，并用第四掩膜在栅极氧化物774上方形成图案，如图8H所示。在图8I中，将第五掩膜用作本体闭锁掩膜。将本体闭锁掩膜719、栅极多晶硅773和氧化物723蚀刻掩膜，通过P本体植入形成P-本体区772。本体区772自对准到栅极多晶硅773。如图栅极多晶硅773足够长，例如栅极多晶硅773延伸到N源极立柱720-S，那么可能并不需要本体阻挡掩膜719。
然后，在图8J中，通过无掩膜的N+植入，在栅极多晶硅773的对边上形成N+ MOS源极区771以及N+ MOS漏极区775。栅极多晶硅773在MOS源极771和MOS漏极775之间，形成一个平面栅极，MOS源极771和MOS漏极775自对准到栅极多晶硅773。N+ MOS漏极775连接到N JFET源极立柱720-S，P-本体区772连接到P+ JFET栅极立柱730。
如图8K所示，BPSG（含有硼磷的硅玻璃）等绝缘材料776形成在上方，隔绝器件的顶面。在图8L中，利用第六掩膜，通过穿过BPSG 776蚀刻到半导体材料中，形成接触孔777。接触孔777应穿过N+ MOS源极771，蚀刻到P-本体772。可以在接触孔777的底部，例如通过垂直植入，形成P+本体接触区778。如图8M所示，沉积源极金属780并形成图案，使得源极金属780填充到接触孔777中，并接触N+ MOS源极771和P-本体772（通过P+本体接触区778）。依据级联电路结构，源极金属780也通过P本体772，连接到P JFET栅极立柱730。在第三维度上，也可以形成栅极垫（图中没有表示出），用于到MOS栅极多晶硅773的外部连接。仅作示例，源极金属780可以是铝。
在图8N中，利用第八掩膜，在中间的JFET漏极立柱720-D处，形成漏极沟槽781。通过中间的JFET漏极立柱720-D蚀刻漏极沟槽781。向下穿过P-外延层715，到N+衬底705中。在图8O中，例如通过制备N+多晶硅垫片、N+外延生长或通过沟槽裸露的侧壁，将N型区779衬在漏极沟槽781内侧。如图8P所示，在漏极沟槽781中形成金属783。蚀刻示例，金属783可以是镀铜，在漏极沟槽中蚀刻金属783，在源极金属780上方，蚀刻金属782。最后，在图8Q中，将晶片/N+衬底705的背部减薄，在底部形成底部漏极金属790。
综上所述，有许多制备JFET源极、栅极和漏极立柱的方法，包括掺杂半导体、蚀刻沟槽然后填充掺杂的多晶硅、蚀刻沟槽然后内衬植入的掺杂物或掺杂的多晶硅并用导电材料或氧化物填充剩余沟槽，等等。更多的可选方法包括蚀刻沟槽，通过外延生长形成掺杂的侧壁，从顶面植入，植入的同时制备外延层和超级结层，等等。
尽管上述实施例是以硅为例做的说明，但是业内人员应理解，该技术也可用于碳化硅（SiC）、锗（Ge）、金刚石、砷化镓（GaAs）或氮化镓（GaN）等任一种半导体材料。而且应理解，N+和P+立柱含有源极、漏极和栅极立柱，可以由多种不同的方式制成。虽然本发明阐述的是一种N-通道JFET，但是通过转换P型和N型半导体区域的导电类型，本发明也可用于P-通道JFET。
尽管已经就现有的较佳实施例对本发明做了说明，但应理解这些内容并不应蚀刻局限。阅读上述说明后，各种变化和修正对于本领域的技术人员而言无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明真实意图和范围内的全部变化和修正。

Claims (1)

1.一个半导体功率器件包括：
一个含有超级结结构的半导体衬底，所述超级结结构设置在所述的半导体衬底的顶面附近，其中，所述的超级结结构是由多个第一和第二导电类型交替的横向堆积层构成的，从源极立柱横向延伸到漏极立柱，其中，所述的源极立柱和漏极立柱为第一导电类型，向下延伸穿过所述的超级结结构；
一个第二导电类型的栅极立柱，向下延伸穿过所述的超级结结构，以便在超级结结构上加载电压，以控制在源极立柱和所述的漏极立柱之间，横向穿过所述的超级结结构的电流；以及
一个设置在超级结结构下方的底部半导体层，漏极立柱向下延伸，电连接到所述的底部半导体层，从而在栅极立柱和底部半导体层之间形成嵌入式栅极-漏极雪崩箝位二极管。
CN201310377546.4A 2009-11-30 2010-11-29 带有很高的衬底-栅极击穿和嵌入式雪崩箝位二极管的横向超级结器件 Active CN103794653B (zh)

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