TWI479500B - 在電子電路中用以增加良率之方法及裝置 - Google Patents

在電子電路中用以增加良率之方法及裝置 Download PDF

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Publication number
TWI479500B
TWI479500B TW097108209A TW97108209A TWI479500B TW I479500 B TWI479500 B TW I479500B TW 097108209 A TW097108209 A TW 097108209A TW 97108209 A TW97108209 A TW 97108209A TW I479500 B TWI479500 B TW I479500B
Authority
TW
Taiwan
Prior art keywords
circuit
voltage
memory
voltage level
weak
Prior art date
Application number
TW097108209A
Other languages
English (en)
Chinese (zh)
Other versions
TW200933642A (en
Inventor
Richard Bruce Dell
Ross A Kohler
Richard J Mcpartland
Hai Quang Pham
Wayne E Werner
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200933642A publication Critical patent/TW200933642A/zh
Application granted granted Critical
Publication of TWI479500B publication Critical patent/TWI479500B/zh

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Power Sources (AREA)
TW097108209A 2008-01-30 2008-03-07 在電子電路中用以增加良率之方法及裝置 TWI479500B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2008/052454 WO2009096957A1 (en) 2008-01-30 2008-01-30 Method and apparatus for increasing yeild in an electronic circuit

Publications (2)

Publication Number Publication Date
TW200933642A TW200933642A (en) 2009-08-01
TWI479500B true TWI479500B (zh) 2015-04-01

Family

ID=39705034

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097108209A TWI479500B (zh) 2008-01-30 2008-03-07 在電子電路中用以增加良率之方法及裝置

Country Status (7)

Country Link
US (1) US7940594B2 (https=)
EP (1) EP2240936A1 (https=)
JP (1) JP2011511395A (https=)
KR (1) KR20100121475A (https=)
CN (1) CN101874272B (https=)
TW (1) TWI479500B (https=)
WO (1) WO2009096957A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011511395A (ja) 2008-01-30 2011-04-07 アギア システムズ インコーポレーテッド 電子回路において歩留りを向上させるための方法及び装置
US8390146B2 (en) * 2008-02-27 2013-03-05 Panasonic Corporation Semiconductor integrated circuit and various devices provided with the same
DE202009007395U1 (de) * 2009-05-19 2009-08-20 Balluff Gmbh Stromversorgungs-Anschlussvorrichtung für ein parametrierbares elektrisches Gerät
CN102468650B (zh) * 2010-11-18 2015-07-08 英业达股份有限公司 多电源供电装置
TWI492471B (zh) * 2010-12-20 2015-07-11 英業達股份有限公司 多電源供電裝置
US9786385B2 (en) * 2015-03-02 2017-10-10 Oracle International Corporation Memory power selection using local voltage regulators
US10664035B2 (en) * 2017-08-31 2020-05-26 Qualcomm Incorporated Reconfigurable power delivery networks

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031778A (en) * 1997-03-19 2000-02-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US20030076729A1 (en) * 2001-10-24 2003-04-24 Fetzer Eric S. Method and apparatus for reducing average power and increasing cache performance by modulating power supplies
US20040090854A1 (en) * 2002-11-11 2004-05-13 Ho-Cheol Lee Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device
US20060268647A1 (en) * 2001-10-23 2006-11-30 Hitachi, Ltd. Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214122A (ja) * 1996-11-27 1998-08-11 Yamaha Corp 降圧回路および集積回路
US7456525B2 (en) * 2004-07-09 2008-11-25 Honeywell International Inc. Multi-output power supply device for power sequencing
JP2006228277A (ja) * 2005-02-15 2006-08-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7236396B2 (en) * 2005-06-30 2007-06-26 Texas Instruments Incorporated Area efficient implementation of small blocks in an SRAM array
ITVA20060081A1 (it) * 2006-12-22 2008-06-23 St Microelectronics Srl Riduzione del consumo da parte di un sistema elettronico integrato comprendente distinte risorse statiche ad accesso casuale di memorizzazione dati
JP2008251603A (ja) * 2007-03-29 2008-10-16 Toshiba Corp 半導体集積回路
JP2011511395A (ja) 2008-01-30 2011-04-07 アギア システムズ インコーポレーテッド 電子回路において歩留りを向上させるための方法及び装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031778A (en) * 1997-03-19 2000-02-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US20060268647A1 (en) * 2001-10-23 2006-11-30 Hitachi, Ltd. Semiconductor device
US7272068B2 (en) * 2001-10-23 2007-09-18 Hitachi, Ltd. Semiconductor device
US20030076729A1 (en) * 2001-10-24 2003-04-24 Fetzer Eric S. Method and apparatus for reducing average power and increasing cache performance by modulating power supplies
US20040090854A1 (en) * 2002-11-11 2004-05-13 Ho-Cheol Lee Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device
US6928023B2 (en) * 2002-11-11 2005-08-09 Samsung Electronics Co., Ltd. Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device

Also Published As

Publication number Publication date
CN101874272B (zh) 2013-08-14
WO2009096957A1 (en) 2009-08-06
JP2011511395A (ja) 2011-04-07
CN101874272A (zh) 2010-10-27
US7940594B2 (en) 2011-05-10
KR20100121475A (ko) 2010-11-17
TW200933642A (en) 2009-08-01
US20100238751A1 (en) 2010-09-23
EP2240936A1 (en) 2010-10-20

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