TWI475619B - 具有通孔之層疊封裝系統及其製造方法 - Google Patents

具有通孔之層疊封裝系統及其製造方法 Download PDF

Info

Publication number
TWI475619B
TWI475619B TW099104330A TW99104330A TWI475619B TW I475619 B TWI475619 B TW I475619B TW 099104330 A TW099104330 A TW 099104330A TW 99104330 A TW99104330 A TW 99104330A TW I475619 B TWI475619 B TW I475619B
Authority
TW
Taiwan
Prior art keywords
package
substrate
package substrate
exposed surface
semiconductor die
Prior art date
Application number
TW099104330A
Other languages
English (en)
Other versions
TW201037774A (en
Inventor
Dongsam Park
Joungin Yang
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW201037774A publication Critical patent/TW201037774A/zh
Application granted granted Critical
Publication of TWI475619B publication Critical patent/TWI475619B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

具有通孔之層疊封裝系統及其製造方法
本發明大致係關於半導體封裝系統，且詳而言之，係用於多晶片模組的可堆疊的層疊封裝系統。
隨著新一代的電子消費產品的發展，存在一種對於改善半導體封裝件的功能性、效能、可靠度、與製造強健性的成長需求。此外，例如行動電話與新型膝上型電腦的新手持式消費電子裝置的設計愈來愈呈薄型(low-profile)。此種設計趨勢在個別電子組件的厚度上強加嚴格的限制。
用於消費電子的系統需求已經激發了合併許多半導體晶粒或「晶片」的積體電路封裝件的實作。此種多晶片封裝件可藉由在單一封裝基板上連接複數個半導體晶粒來實現。
或者，用以封裝多晶片模組的封裝體內封裝(Package-in-Package，簡稱PiP)方法包含在封裝基板上先設置半導體晶粒並互相連接，而形成內部堆疊模組(Internal Stacking Module，簡稱ISM)。此封裝模組可在組合成為多晶片封裝件之前個別地測試。因此該PiP方法提供一種預先測試封裝子組合件(也就是內部堆疊模組)的手段，使得複雜之多晶片封裝件的組合件能使用「已知良好封裝件(known good package)」。此用於組合多晶片封裝件的模組方法減低整體良率損失(yield loss)。
然而另一多晶片封裝件的實作是稱為「層疊封裝(Package-on-Package)」(PoP)。在此方法中，是將一個單晶封裝件堆疊在另一封裝件的頂部上並在該兩個封裝件之間使用用來路由(route)訊號的標準互相連接。
現有PiP或PoP封裝件的一個缺點是它們並不提供用以將較大的多晶片封裝件整合成一體的足夠多元性(versatility)與可靠度。因此，仍依舊需要具有增加的互相連接能力與減低的整體厚度且同時改善其可靠度的內部堆疊模組及/或層疊封裝系統。
更具體地說，有降低PiP與PoP系統的成本以及在促使整合成較大的多晶片封裝模組的製造期間減低該模組的翹曲(warp)的需求。鑑於由封裝件翹曲所造成的良率損失，找到這些問題的答案是愈來愈關鍵。
鑑於持續增加的商業競爭壓力，以及增加的消費者期望與在市場中減少有意義的產品差異性的機會，找到這些問題的答案是愈來愈關鍵。此外，減低成本、改善效率與效能、以及對抗競爭壓力的需求更大大地增進對於尋找這些問題的答案的關鍵必要性的迫切性。
已經長期思考過這些問題的解決方案，但是先前的發展並未教示或建議任何解決方案，而因此這些問題的解決方案已經長期困擾本發明所屬技術領域中具有通常知識者。
本發明提供一種層疊封裝系統的製造方法，係包含：設置封裝基板；將半導體晶粒附接至該封裝基板；形成圍繞該半導體晶粒的封裝材料，該封裝材料具有與該封裝基板的底部表面共平面的底部外露表面並具有頂部外露表面、且具有從頂部外露表面延伸通過至底部外露表面的貫穿開口；以及，藉由將焊料(solder)敷設至該貫穿開口中以產生通孔。
再者，本發明提供一種層疊封裝系統，係包含：封裝基板；半導體晶粒，係附接至該封裝基板；封裝材料，係圍繞該封裝基板與該半導體晶粒的至少部分，該封裝材料具有與該封裝基板的底部表面共平面的底部外露表面並具有頂部外露表面；以及，通孔，係從該封裝材料的頂部外露表面延伸至底部外露表面。
本發明的一些實施例具有除上述提及的那些之外或代替上述提及的那些的其他步驟或元件。對於本發明所屬技術領域中具有通常知識者而言，在閱讀下列實施方式並參照所附圖式後，該等步驟或元件將變得顯而易見。
為了使本發明所屬技術領域中具有通常知識者能夠製造與使用本發明，下列實施例是以足夠的細節來描述。應了解，基於本揭露內容，其他實施例將是顯而易見的，且在不背離本發明的範圍下，可進行系統、製程、或機構的改變。
在下列描述中，將提供許多具體細節，以徹底了解本發明。然而，應明白，可不需這些具體細節而實施本發明。為了避免模糊本發明，一些習知的電路、系統組構、與製程步驟將不詳細揭露。
顯示系統實施例的圖式是半概略的輪廓而非按照比例，特別是一些尺寸係為了清楚表示而在圖式中誇大顯示。相似地，雖然圖式中的視圖為了描述方便而一般顯示為相似的方向，但是圖式中的表示大部分是沒有限定的。一般來說，本發明可操作在任意方向上。
在所有圖式中使用相同的元件符號來連結相同的元件。為了描述方便，實施例已經被標號成第一實施例、第二實施例等，而並非意欲有任何其他意義或用以限制本發明。
為了解說的目的，在此使用的用語「水平(horizontal)」是定義成平行於半導體晶粒的平面或表面的平面，而不論其方向。用語「垂直(vertical)」是關於垂直於剛才定義的該水平的方向。例如「上方(above)」、「下方(below)」、「底部(bottom)」、「頂部(top)」、「側邊(side)」(如「側壁(sidewall)」)、「較高(higher)」、「較低(lower)」、「上面的(upper)」、「在…上方(over)」、與「在…之下(under)」的用語是相對該水平面來定義，如圖所示。用語「在…上(on)」意指在元件之中有直接接觸。
在此使用的用語「加工(processing)」包含形成所述結構所需的材料或光阻的沉積、圖案化、曝光、顯影、蝕刻、清潔、及/或該材料或光阻的移除。
現在參照第1圖，其顯示本發明的一個實施例中的層疊封裝系統100的仰視圖。該層疊封裝系統100包含兩種類型的外部連接102：基板連接104與通孔106。
該基板連接104提供通過封裝基板108的電性路徑(electrical path)。該通孔106是完全位在封裝材料(encapsulant)110內，並提供通過該層疊封裝系統100的電性連接。
該封裝基板108包含延伸至該層疊封裝系統100的邊緣(edge)114的連結桿(tie bar)112。在本發明的一個實施例中，將一些該連結桿112組構成彼此間具有偏移(offset)116。
現在參照第2圖，其顯示本發明的另一實施例中的層疊封裝系統200的仰視圖。與該層疊封裝系統100相似地，該層疊封裝系統200包含兩種類型的外部連接202：基板連接204與通孔206。
該基板連接204提供通過封裝基板208的電性路徑。該封裝基板208具有從該層疊封裝系統200的末邊緣212延伸至相對邊緣214的矩形形狀。封裝材料210包圍該封裝基板208的部分。
現在參照第3圖，其顯示沿第1圖所示的線3--3所取的該層疊封裝系統100的剖視圖。半導體晶粒302是使用黏著劑(adhesive)304來附接至該封裝基板108。電性互連306在該半導體晶粒302與該基板連接104之間提供連線(connectivity)。該電性互連306可使用第3圖所示的結合引線(bond wire)來實作。
該通孔106垂直延伸通過該層疊封裝系統100的厚度308以通過該層疊封裝系統100提供電性連接。該封裝材料110具有與該封裝基板108的底部表面312共平面的底部外露表面310、並具有頂部外露表面314。該通孔106從該封裝材料110的頂部外露表面314延伸至該底部外露表面310。
可利用該通孔106以在設置於該層疊封裝系統100上方與下方的外部元件之間提供互連線(interconnectivity)。外部互連316提供往下一系統階層(level)的連線。
已經發現可使用最低限度是大於該半導體晶粒302的封裝基板108來實作該層疊封裝系統100，以降低該層疊封裝系統100的整體成本。
此外，該層疊封裝系統100比較不會受到由製造製程造成的翹曲所影響。所以可輕易地整合成為較大多晶片模組的一部份。該層疊封裝系統100可在整合成為較大模組之前電性測試與分類成已知良好封裝件(GKP)，而增加多晶片模組的整體可靠度。
因此，已經發現本發明的層疊封裝系統100提供用以實作低成本模組封裝件的重要與迄今未知和無法得到的解決方案、能力、與功能態樣，該低成本模組封裝件可堆疊成為多階層封裝件(multi-level package)。
現在參照第4圖，其顯示合併有第3圖的封裝基板108的封裝基板組合件400的俯視圖。該封裝基板組合件400合併藉由使用該連結桿112的框架(frame) 402以保持在一起的複數個該封裝基板108的複製品(repetition)。該封裝基板組合件400是使用在該層疊封裝系統100的製造中。
現在參照第5圖，其顯示本發明的替代實施例中的合併有該封裝基板208的封裝基板組合件500的俯視圖。該封裝基板組合件500合併藉由框架502以保持在一起的複數個該封裝基板208的複製品。該封裝基板組合件500是使用在該層疊封裝系統200的製造中。
現在參照第6圖，其顯示本發明的替代實施例中的層疊封裝系統600的仰視圖。該層疊封裝系統600包含兩種類型的外部連接602：基板連接604與通孔606。該基板連接604在外部元件(未圖示)與半導體晶粒(未圖示)之間提供電性路徑。該通孔606垂直延伸通過封裝材料608的厚度(未圖示)，以在該層疊封裝系統600的頂部表面與底部表面之間提供電性連接。
現在參照第7圖，其顯示沿第6圖所示的線7-7所取的層疊封裝系統600的剖視圖。半導體晶粒702使用黏著劑704以附接至基板連接604。電性互連706在該半導體晶粒702與該基板連接604之間提供連線。可使用如第7圖所示的結合引線來實作該電性互連706。
該封裝材料608包圍至少部分之該半導體晶粒702、該基板連接604、該電性互連706、與該通孔606。該封裝材料608具有與該基板連接604的底部表面712共平面的底部外露表面710、並具有頂部外露表面714。該通孔606從該封裝材料608的頂部外露表面714延伸至該底部外露表面710。
可利用該通孔606以在設置於該層疊封裝系統600上方與下方的外部組件之間提供互連線。外部互連716提供往下一系統階層的連線。
已經發現可使用具有最低限度大於該半導體晶粒702的佈線佔有面積(layout footprint)的基板連接604來實作該層疊封裝系統600，以減低該層疊封裝系統600的整體成本。此外，該層疊封裝系統600比較不會受到由製造製程造成的翹曲所影響。
因此，已經發現本發明的層疊封裝系統600提供用以實作低成本模組封裝件的重要與迄今未知和無法得到的解決方案、能力、與功能態樣，該低成本模組封裝件可堆疊成為多階層封裝件。
現在參照第8圖，其顯示合併有第6圖所示的該基板連接604的封裝基板組合件800的俯視圖。該封裝基板組合件800合併有複數個使用在各層疊封裝系統600中的該基板連接604的佈局的複製品。該基板連接604是由封裝載板(carrier)802所支撐。在本發明的此實施例中，該封裝載板802是例如為銅板(copper plate)的犧牲板(sacrificial plate)。
現在參照第9圖，其顯示第8圖所示的封裝基板組合件800中的封裝基板900的剖視圖。在該層疊封裝系統600的製造製程的初始階段，各封裝基板900包含該封裝載板802與基板連接604。在本發明的一個實施例中，該封裝載板802是銅板，且該基板連接604是電鍍金屬跡線(plated metal trace)。
現在參照第10圖，其顯示在本發明的另一實施例中的層疊封裝系統1000的仰視圖。該層疊封裝系統1000包含可經由其底部表面來存取的兩種類型的外部連接1002：基板連接1004與通孔1006。該基板連接1004在外部元件與半導體晶粒(未圖示)之間提供電性路徑。該通孔1006完全延伸通過該封裝材料1008，以在該層疊封裝系統1000的頂部表面與底部表面之間提供電性連接。
第10圖所示的本發明的實施例包含使用相同於該基板連接1004的材料來製作的虛擬圖案(dummy pattern)1010。該虛擬圖案1010是使用在製造製程期間以促進該基板連接1004的平坦化製程及減低該層疊封裝系統1000的翹曲的特徵。
現在參照第11圖，其顯示合併有使用在第10圖所示的層疊封裝系統1000中的該基板連接1004與該虛擬圖案1010的封裝基板1100的俯視圖。為了清楚表示，在該封裝基板1100中的封裝載板並未圖示。
現在參照第12圖，其顯示使用在該層疊封裝系統100的製造的初始階段中的模具(mold) 1200的剖視圖。在製程的此階段，該半導體晶粒302已經附接至該封裝基板108且已經使用該電性互連306來連接至該封裝基板108。該封裝基板108靠在底部模板(bottom mold plate)1202的頂部上。頂部模板1204覆蓋該封裝基板108、該半導體晶粒307、與該電性互連306。
用於該通孔106的開口(opening)是藉由銷子(pin)1206來定義，該銷子1206延伸通過由該頂部模板1204與底部模板1202所定義的模穴(molding cavity)1208。射出的該封裝材料(未圖示)通過射出通口(injection port)1210進入至該穴1208。
現在參照第13圖，其顯示模造該封裝材料110後的第3圖的層疊封裝系統100的剖視圖。顯示在第12圖中的銷子1206定義延伸通過該封裝材料110的貫穿開口(through opening)1302。該貫穿開口1302是用於通孔106(未圖示)的模具。
該封裝材料110具有與該封裝基板108的底部表面312共平面的底部外露表面310、並具有頂部外露表面314。該貫穿開口1302從該封裝材料110的頂部外露表面314延伸至該底部外露表面310。
現在參照第14圖，其顯示模造該封裝材料608後的第7圖的層疊封裝系統600的剖視圖。第12圖所示的銷子1206定義延伸通過該封裝材料608的貫穿開口1402。該貫穿開口1402是用於通孔606(未圖示)的模具。在該封裝材料608形成後，係分解(dissolve)第8圖的封裝載板802。
該封裝材料608具有與該基板連接604的底部表面712共平面的底部外露表面710、並具有頂部外露表面714。該貫穿開口1402從該封裝材料608的頂部外露表面714延伸至該底部外露表面710。
現在參照第15圖，其顯示使用來形成本發明的一個實施例中的通孔106的機械裝置1500。在該層疊封裝系統100的製造製程的此步驟中，將第13圖的結構放置在該機械裝置1500的支撐板1502與模印板(stencil plate)1504之間。先前由該封裝材料110的模造所定義的貫穿開口1302是對準(align)至該模印板1504中的開口1506。
藉由使用楔子(wedge)1510將焊料1508敷設至該貫穿開口1302中以形成該通孔106。該楔子1510上的垂直壓力確保填入該貫穿開口1302。該支撐板1502上的不沾黏材料(non-stick material)1512防止該通孔106的沾黏。
現在參照第16圖，其顯示在形成該通孔106與外部互連316之後的該製造製程的尾聲時的第3圖的層疊封裝系統100。
現在參照第17圖，其顯示在形成該通孔606與外部互連716之後的該製造製程的尾聲時的第6圖的層疊封裝系統600。
現在參照第18圖，其顯示在本發明的進一步實施例中的層疊封裝系統100的製造方法1800的流程圖。該方法1800包含：方塊1802中的設置封裝基板；方塊1804中的將半導體晶粒附接至該封裝基板；在方塊1806中的形成圍繞該半導體晶粒的封裝材料，該封裝材料具有與該封裝基板的底部表面共平面的底部外露表面並具有頂部外露表面、且具有從頂部外露表面延伸通過至底部外露表面的貫穿開口；以及，在方塊1808中的藉由將焊料敷設至該貫穿開口中以產生通孔。
所產生的方法、製程、設備、裝置、產品、及/或系統是簡單明確的、有成本效益的、不複雜的、高度多元的、準確的、敏感的、且有效的，並可藉由改造已知元件來實作，以迅速、效率高、及經濟地製造、應用、與利用。
本發明的另一重要態樣是它有益地支持並幫助降低成本、簡化系統、及增進效能的歷史趨勢。
本發明的這些與其他重要態樣因此促進該技術的狀態至至少下一階層。
雖然本發明已經連結具體最佳模式來敘述，但是應了解，許多替代、修改、與變化型式對於已按照先前的描述的本發明所屬技術領域中具有通常知識者而言將是顯而易知的。據此，本發明是要涵蓋落入所附申請專利範圍的範疇內的所有此種替代、修改、與變化型式。在此提出或在所附圖式中顯示的所有內容係解讀成說明的而非限制的意思。
100、200、600、1000．．．層疊封裝系統
102、202、602、1002．．．外部連接
104、204、604、1004．．．基板連接
106、206、606、1006．．．通孔
108、208、900、1100．．．封裝基板
110、210、608、1008．．．封裝材料
112．．．連結桿
114．．．邊緣
116．．．偏移
212．．．末邊緣
214．．．相對邊緣
302、702．．．半導體晶粒
304、704．．．黏著劑
306、706．．．電性互連
308．．．厚度
310、710．．．底部外露表面
312、712．．．底部表面
314、714．．．頂部外露表面
316、716．．．外部互連
400、500、800．．．封裝基板組合件
402、502．．．框架
802．．．封裝載板
1010．．．虛擬圖案
1200．．．模具
1202．．．底部模板
1204．．．頂部模板
1206．．．銷子
1208．．．模穴
1210．．．射出通口
1302、1402．．．貫穿開口
1500．．．機械裝置
1502．．．支撐板
1504．．．模板
1506．．．開口
1508．．．焊料
1510．．．楔子
1512．．．不沾黏材料
1800．．．方法
1802、1804、1806、1808．．．方塊
第1圖係本發明的一個實施例中的層疊封裝系統的仰視圖；
第2圖係本發明的另一實施例中的層疊封裝系統的仰視圖；
第3圖係沿第1圖所示的線3--3所取的該層疊封裝系統的剖視圖；
第4圖係合併有第3圖的封裝基板的封裝基板組合件的俯視圖；
第5圖係本發明的替代實施例中的合併有封裝基板的封裝基板組合件的俯視圖；
第6圖係本發明的替代實施例中的層疊封裝系統的仰視圖；
第7圖係沿第6圖所示的線7-7所取的層疊封裝系統的剖視圖；
第8圖係合併有第6圖所示的該基板連接的封裝基板組合件的俯視圖；
第9圖係第8圖所示的封裝基板組合件800中的封裝基板的剖視圖；
第10圖係在本發明的另一實施例中的層疊封裝系統的仰視圖；
第11圖係合併有使用在第10圖所示的層疊封裝系統中的該基板連接與該虛擬圖案的封裝基板的俯視圖；
第12圖係使用在該層疊封裝系統的製造的初始階段中的模具的剖視圖；
第13圖係模造該封裝材料後的第3圖的層疊封裝系統的剖視圖；
第14圖係模造該封裝材料後的第7圖的層疊封裝系統的剖視圖；
第15圖係使用來形成本發明的一個實施例中的通孔的機械裝置；
第16圖係在形成該通孔與外部互連之後的該製造製程的尾聲時的第3圖的層疊封裝系統；
第17圖係在形成該通孔與外部互連之後的該製造製程的尾聲時的第6圖的層疊封裝系統；以及
第18圖係在本發明的進一步實施例中的層疊封裝系統的製造方法的流程圖。
100．．．層疊封裝系統
104．．．基板連接
106．．．通孔
108．．．封裝基板
110．．．封裝材料
302．．．半導體晶粒
304．．．黏著劑
306．．．電性互連
308．．．厚度
310．．．底部外露表面
312．．．底部表面
314．．．頂部外露表面
316．．．外部互連

Claims (10)

  1. 一種層疊封裝系統的製造方法，係包括；設置封裝基板；將半導體晶粒附接至該封裝基板；形成圍繞該半導體晶粒的封裝材料，該封裝材料具有底部外露表面及頂部外露表面，其中，該底部外露表面與該封裝基板的底部表面共平面，且該頂部外露表面具有自該頂部外露表面延伸通過至該底部外露表面的貫穿開口；以及藉由將焊料敷設至該貫穿開口中以產生通孔。
  2. 如申請專利範圍第1項之方法，其中：設置該封裝基板包含形成自該層疊封裝系統的末邊緣延伸至相對邊緣的該封裝基板；以及形成封裝材料包含產生位於該封裝基板的一側上的貫穿開口。
  3. 如申請專利範圍第1項之方法，其中：設置該封裝基板包含形成合併有延伸至該層疊封裝系統的邊緣的連結桿的該封裝基板；以及形成封裝材料包含產生位於該連結桿的一側上的貫穿開口。
  4. 如申請專利範圍第1項之方法，其中，設置該封裝基板包含形成合併有封裝載板與基板連接的該封裝基板。
  5. 如申請專利範圍第1項之方法，其中，設置封裝基板包含形成合併有基板連接與虛擬圖案的該封裝基板。
  6. 一種層疊封裝系統，係包括：封裝基板；半導體晶粒，係附接至該封裝基板；封裝材料，係圍繞至少部分的該封裝基板與該半導體晶粒，該封裝材料具有與該封裝基板的底部表面共平面的底部外露表面，並具有頂部外露表面；以及通孔，係自該封裝材料的該頂部外露表面延伸至底部外露表面。
  7. 如申請專利範圍第6項之系統，其中：該封裝基板自該層疊封裝系統的末邊緣延伸至相對邊緣；以及該通孔係位於該封裝基板的一側上。
  8. 如申請專利範圍第6項之系統，其中：該封裝基板包含延伸至該層疊封裝系統的邊緣的連結桿；以及該通孔係位於該連結桿的一側上。
  9. 如申請專利範圍第6項之系統，其中，該封裝基板包含封裝載板與基板連接。
  10. 如申請專利範圍第6項之系統，其中，該封裝基板包含基板連接與虛擬圖案。
TW099104330A 2009-02-18 2010-02-11 具有通孔之層疊封裝系統及其製造方法 TWI475619B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/388,516 US7986048B2 (en) 2009-02-18 2009-02-18 Package-on-package system with through vias and method of manufacture thereof

Publications (2)

Publication Number Publication Date
TW201037774A TW201037774A (en) 2010-10-16
TWI475619B true TWI475619B (zh) 2015-03-01

Family

ID=42559183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099104330A TWI475619B (zh) 2009-02-18 2010-02-11 具有通孔之層疊封裝系統及其製造方法

Country Status (3)

Country Link
US (3) US7986048B2 (zh)
KR (1) KR101715265B1 (zh)
TW (1) TWI475619B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8476135B2 (en) 2011-05-27 2013-07-02 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US8970044B2 (en) 2011-06-23 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8525325B2 (en) 2011-12-14 2013-09-03 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
US9219029B2 (en) * 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US10177032B2 (en) 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
CN105280575A (zh) 2014-07-17 2016-01-27 联华电子股份有限公司 半导体封装结构及其制造方法
US10595411B2 (en) * 2017-05-10 2020-03-17 Power Wave Electronics Co., Ltd. Method for manufacturing chip signal elements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984880B2 (en) * 2001-02-14 2006-01-10 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US7208826B2 (en) * 2000-07-05 2007-04-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
JPH07288385A (ja) * 1994-04-19 1995-10-31 Hitachi Chem Co Ltd 多層配線板及びその製造法
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3492212B2 (ja) * 1998-08-26 2004-02-03 新光電気工業株式会社 半導体装置用パッケージ及びその製造方法
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
JP3883784B2 (ja) * 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
US20040173894A1 (en) * 2001-09-27 2004-09-09 Amkor Technology, Inc. Integrated circuit package including interconnection posts for multiple electrical connections
US6664615B1 (en) * 2001-11-20 2003-12-16 National Semiconductor Corporation Method and apparatus for lead-frame based grid array IC packaging
KR20040026530A (ko) * 2002-09-25 2004-03-31 삼성전자주식회사 반도체 패키지 및 그를 이용한 적층 패키지
JP4093018B2 (ja) * 2002-11-08 2008-05-28 沖電気工業株式会社 半導体装置及びその製造方法
JP2004228226A (ja) * 2003-01-21 2004-08-12 Gisei Rin 集積回路パッケージキャリア
KR100621555B1 (ko) * 2004-02-04 2006-09-14 삼성전자주식회사 리드 프레임, 이를 이용한 반도체 칩 패키지 및 그의 제조방법
JP2008545274A (ja) * 2005-06-30 2008-12-11 フェアチャイルド セミコンダクター コーポレイション 半導体ダイ・パッケージ及びその製造方法
TWI267967B (en) * 2005-07-14 2006-12-01 Chipmos Technologies Inc Chip package without a core and stacked chip package structure using the same
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7667338B2 (en) * 2006-08-08 2010-02-23 Lin Paul T Package with solder-filled via holes in molding layers
US7662672B2 (en) * 2006-10-13 2010-02-16 Chipmos Technologies (Bermuda) Ltd. Manufacturing process of leadframe-based BGA packages
WO2008065896A1 (fr) * 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
JP4415984B2 (ja) * 2006-12-06 2010-02-17 ソニー株式会社 半導体装置の製造方法
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
KR101391925B1 (ko) * 2007-02-28 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형
JP5280014B2 (ja) * 2007-04-27 2013-09-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7919868B2 (en) * 2007-08-15 2011-04-05 Qimonda Ag Carrier substrate and integrated circuit
KR101329355B1 (ko) * 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US20090236726A1 (en) * 2007-12-12 2009-09-24 United Test And Assembly Center Ltd. Package-on-package semiconductor structure
JP2009182202A (ja) * 2008-01-31 2009-08-13 Casio Comput Co Ltd 半導体装置の製造方法
US7863755B2 (en) * 2008-03-19 2011-01-04 Stats Chippac Ltd. Package-on-package system with via Z-interconnections
JP5043743B2 (ja) * 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208826B2 (en) * 2000-07-05 2007-04-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6984880B2 (en) * 2001-02-14 2006-01-10 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device

Also Published As

Publication number Publication date
US20110254172A1 (en) 2011-10-20
US20130075933A1 (en) 2013-03-28
TW201037774A (en) 2010-10-16
US20100207262A1 (en) 2010-08-19
US7986048B2 (en) 2011-07-26
US8334601B2 (en) 2012-12-18
KR20100094410A (ko) 2010-08-26
US8598034B2 (en) 2013-12-03
KR101715265B1 (ko) 2017-03-10

Similar Documents

Publication Publication Date Title
TWI475619B (zh) 具有通孔之層疊封裝系統及其製造方法
TWI596679B (zh) 重新分布之積體電路封裝堆疊系統及其製造方法
TWI524440B (zh) 具有貫穿之半導體通孔之積體電路封裝系統及其製造方法
US7271496B2 (en) Integrated circuit package-in-package system
US7863100B2 (en) Integrated circuit packaging system with layered packaging and method of manufacture thereof
US7863755B2 (en) Package-on-package system with via Z-interconnections
TWI499032B (zh) 積體電路層疊封裝件堆疊系統
TWI442541B (zh) 具有支撐結構之可堆疊式多晶片封裝件系統
KR101019793B1 (ko) 반도체 장치 및 그 제조 방법
US8466567B2 (en) Integrated circuit packaging system with stack interconnect and method of manufacture thereof
JP4402074B2 (ja) オフセット集積回路パッケージオンパッケージ積層システムおよびその製造方法
US7732901B2 (en) Integrated circuit package system with isloated leads
US7829990B1 (en) Stackable semiconductor package including laminate interposer
US7279785B2 (en) Stacked die package system
KR20100050750A (ko) 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
JP2006324666A5 (zh)
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
TWI446461B (zh) 具有外部互連陣列的積體電路封裝件系統
TWI538118B (zh) 重組式晶圓級封裝動態隨機存取記憶體
KR20110105159A (ko) 적층 반도체 패키지 및 그 형성방법
US9299650B1 (en) Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
US9093392B2 (en) Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US9293350B2 (en) Semiconductor package system with cavity substrate and manufacturing method therefor
TWI470703B (zh) 具高密度外部互連之積體電路封裝系統
US20120119345A1 (en) Integrated circuit packaging system with device mount and method of manufacture thereof