TWI474168B - Semiconductor device and host - Google Patents

Semiconductor device and host Download PDF

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Publication number
TWI474168B
TWI474168B TW99132498A TW99132498A TWI474168B TW I474168 B TWI474168 B TW I474168B TW 99132498 A TW99132498 A TW 99132498A TW 99132498 A TW99132498 A TW 99132498A TW I474168 B TWI474168 B TW I474168B
Authority
TW
Taiwan
Prior art keywords
packet
host
value
devices
initial value
Prior art date
Application number
TW99132498A
Other languages
English (en)
Chinese (zh)
Other versions
TW201124841A (en
Inventor
藤本曜久
Original Assignee
東芝股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝股份有限公司 filed Critical 東芝股份有限公司
Publication of TW201124841A publication Critical patent/TW201124841A/zh
Application granted granted Critical
Publication of TWI474168B publication Critical patent/TWI474168B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
TW99132498A 2009-09-24 2010-09-24 Semiconductor device and host TWI474168B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009219691 2009-09-24
JP2009221468A JP5150591B2 (ja) 2009-09-24 2009-09-25 半導体装置及びホスト機器

Publications (2)

Publication Number Publication Date
TW201124841A TW201124841A (en) 2011-07-16
TWI474168B true TWI474168B (zh) 2015-02-21

Family

ID=43795913

Family Applications (2)

Application Number Title Priority Date Filing Date
TW99132498A TWI474168B (zh) 2009-09-24 2010-09-24 Semiconductor device and host
TW104100358A TWI542996B (zh) 2009-09-24 2010-09-24 Semiconductor devices and host machines

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW104100358A TWI542996B (zh) 2009-09-24 2010-09-24 Semiconductor devices and host machines

Country Status (7)

Country Link
US (5) US9146866B2 (enExample)
EP (1) EP2482195B1 (enExample)
JP (1) JP5150591B2 (enExample)
KR (1) KR101343646B1 (enExample)
CN (2) CN102483723A (enExample)
TW (2) TWI474168B (enExample)
WO (1) WO2011037168A1 (enExample)

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JP5150591B2 (ja) * 2009-09-24 2013-02-20 株式会社東芝 半導体装置及びホスト機器
USRE48495E1 (en) 2009-12-17 2021-03-30 Toshiba Memory Corporation System, device, and method for initializing a plurality of electronic devices using a single packet
KR101996822B1 (ko) 2013-03-15 2019-07-08 삼성전자 주식회사 링 토폴로지 저장 네트워크의 멀티캐스트 명령 패킷 처리 방법 및 시스템
JP6087742B2 (ja) * 2013-06-14 2017-03-01 キヤノン株式会社 半導体装置、および、チップ識別子の設定方法
JP6067541B2 (ja) * 2013-11-08 2017-01-25 株式会社東芝 メモリシステムおよびメモリシステムのアセンブリ方法
JP6439343B2 (ja) * 2014-09-22 2018-12-19 株式会社バッファロー 通信装置、情報処理装置、通信システム、通信装置におけるアクセス方法及びプログラム
US9552327B2 (en) * 2015-01-29 2017-01-24 Knuedge Incorporated Memory controller for a network on a chip device
US10061531B2 (en) 2015-01-29 2018-08-28 Knuedge Incorporated Uniform system wide addressing for a computing system
US20170116154A1 (en) * 2015-10-23 2017-04-27 The Intellisis Corporation Register communication in a network-on-a-chip architecture
US20170141878A1 (en) * 2015-11-16 2017-05-18 Western Digital Technologies, Inc. Systems and methods for sending data from non-volatile solid state devices before error correction
US9959066B2 (en) * 2016-02-12 2018-05-01 Knuedge Incorporated Memory-attached computing resource in network on a chip architecture to perform calculations on data stored on memory external to the chip
US10027583B2 (en) 2016-03-22 2018-07-17 Knuedge Incorporated Chained packet sequences in a network on a chip architecture
US10346049B2 (en) 2016-04-29 2019-07-09 Friday Harbor Llc Distributed contiguous reads in a network on a chip architecture
JP6927766B2 (ja) * 2017-06-29 2021-09-01 矢崎総業株式会社 情報設定装置
US10866746B2 (en) 2017-12-28 2020-12-15 Silicon Motion Inc. Memory addressing methods and associated controller, memory device and host
TWI714487B (zh) 2017-12-28 2020-12-21 慧榮科技股份有限公司 記憶卡控制器以及使用於記憶卡控制器的方法
JP7423367B2 (ja) 2020-03-23 2024-01-29 キオクシア株式会社 通信システム、デバイス、及び通信方法
JP7527910B2 (ja) 2020-09-16 2024-08-05 キオクシア株式会社 通信システム、デバイス及び通信方法

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US20030128702A1 (en) * 2001-12-28 2003-07-10 Masahito Satoh Communication method and apparatus for assigning device identifier
TWI261788B (en) * 2002-08-09 2006-09-11 Carry Computer Eng Co Ltd Small-form-factor memory card interface (II) having multi-functional communication interface, formatter and format converter
US20060282549A1 (en) * 2002-12-20 2006-12-14 Thomas Vinnemann Automatic addressing on bus systems
TW200801957A (en) * 2006-05-11 2008-01-01 Samsung Electronics Co Ltd Memory device having data input and output ports and memory module and memory system including the same

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Publication number Priority date Publication date Assignee Title
US20030128702A1 (en) * 2001-12-28 2003-07-10 Masahito Satoh Communication method and apparatus for assigning device identifier
TWI261788B (en) * 2002-08-09 2006-09-11 Carry Computer Eng Co Ltd Small-form-factor memory card interface (II) having multi-functional communication interface, formatter and format converter
US20060282549A1 (en) * 2002-12-20 2006-12-14 Thomas Vinnemann Automatic addressing on bus systems
TW200801957A (en) * 2006-05-11 2008-01-01 Samsung Electronics Co Ltd Memory device having data input and output ports and memory module and memory system including the same

Also Published As

Publication number Publication date
JP2011090349A (ja) 2011-05-06
KR20120054051A (ko) 2012-05-29
EP2482195A1 (en) 2012-08-01
CN107092572B (zh) 2020-12-29
CN107092572A (zh) 2017-08-25
EP2482195A4 (en) 2014-04-23
JP5150591B2 (ja) 2013-02-20
US9146866B2 (en) 2015-09-29
EP2482195B1 (en) 2017-10-25
USRE48514E1 (en) 2021-04-13
USRE50685E1 (en) 2025-12-02
TWI542996B (zh) 2016-07-21
TW201514698A (zh) 2015-04-16
KR101343646B1 (ko) 2013-12-20
US20120177050A1 (en) 2012-07-12
TW201124841A (en) 2011-07-16
WO2011037168A1 (ja) 2011-03-31
USRE47290E1 (en) 2019-03-12
USRE49424E1 (en) 2023-02-21
CN102483723A (zh) 2012-05-30

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