TWI451530B - 為多晶圓積體電路形成矽穿孔 - Google Patents

為多晶圓積體電路形成矽穿孔 Download PDF

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TWI451530B
TWI451530B TW100117820A TW100117820A TWI451530B TW I451530 B TWI451530 B TW I451530B TW 100117820 A TW100117820 A TW 100117820A TW 100117820 A TW100117820 A TW 100117820A TW I451530 B TWI451530 B TW I451530B
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wafer
vias
germanium
wafers
semiconductor device
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TW201201323A (en
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Bin Xie
Pui Chung Simon Law
Yat Kit Tsui
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Hk Applied Science & Tech Res
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Description

為多晶圓積體電路形成矽穿孔
本發明係關於三維積體電路製備，且更特定言之，係關於其中形成通孔且隨後進行通孔金屬化之各別積體電路之接合。
隨著積體電路尺寸逐步變小，其正接近實體限度，低於該實體限度，將無法製造器件。因此，積體電路之傳統兩維模式正經歷向三維整合之轉變。發展到三維範式有許多挑戰要克服。首先，大部分積體電路製造技術依賴於以某種方式對晶圓表面進行修改來形成組件及金屬化路徑。因此，三維整合將很可能依賴於多個堆疊之晶圓，器件形成於每一個別晶圓中。
堆疊多個晶圓存在許多挑戰。為了使多個晶圓彼此黏附，晶圓必須極其平坦以確保晶圓與晶圓之接觸。另一挑戰為位於各個晶圓上之器件之間的互連。此需要垂直金屬化以整合位於不同晶圓上之器件。
美國專利第7,385,283號描述一種製備三維積體電路之方法。在此方法中，將金屬互連件對準，且在晶圓堆疊期間形成金屬與金屬接合。同時，在鄰接晶圓之間形成非金屬與非金屬接合。雖然此技術係一種垂直整合之方法，但在晶圓接合之前對通孔金屬化可能在晶圓接合製程期間產生問題。若使用熱來接合晶圓，則金屬離子可能會擴散到晶圓與晶圓接合區域；對於銅通孔金屬化，擴散之銅可能會「污染」附近器件。對於矽晶圓，銅摻雜形成深層陷阱，從而嚴重地影響整個三維堆疊之電性質。若在接合之前執行化學機械拋光，通孔中之金屬化可能不會與表面齊平，從而導致難以在鄰接晶圓通孔之間形成金屬與金屬接合，且可能導致器件級之間之「斷路」。此外，在每一個別晶圓上執行通孔金屬化隨後執行晶圓間通孔接合之需要給整個製程增加了昂貴且耗時之處理步驟。
因此，此項技術中需要一種改良之技術，以垂直地整合晶圓，從而形成多層積體電路。
本發明提供一種用於形成三維晶圓堆疊之方法，該三維晶圓堆疊具有貫通該堆疊之單一金屬化通孔(「堆疊通孔」)，該堆疊可具有可變之橫截面形狀。本方法使用至少第一矽晶圓及第二矽晶圓。每一晶圓具有在其上形成之一或多個積體電路。在每一矽晶圓中形成一或多個穿孔，接著在矽晶圓之至少上表面及下表面上形成氧化物。將晶圓對準，以使每一晶圓穿孔與鄰接堆疊晶圓中的對應穿孔對準。接合晶圓以形成具有一或多個堆疊通孔之三維晶圓堆疊，該一或多個堆疊通孔藉由對準個別晶圓通孔而形成。藉由在每一堆疊通孔中形成晶種層(視情況為銅晶種層)，接著電鍍銅以形成貫通三維晶圓堆疊之連續且同質之金屬化路徑，來執行通孔金屬化。
詳細地參照附圖，圖1A描繪根據本發明之用於形成三維接合晶圓堆疊之第一矽晶圓100。晶圓100包括各種組件、金屬化物、積體電路等(110)，其在積體電路製造技術中係已知的且可藉由任何已知技術形成。藉由諸如深反應性離子蝕刻(DRIE)之蝕刻製程產生渠溝120。在後續製程中，渠溝120將會變成通孔。
在圖1B中，利用任何已知之技術，例如電漿增強化學氣相沈積(PECVD)、濺鍍等，沈積氧化矽層130(例如，二氧化矽)。此材料亦覆蓋渠溝120之側壁，以充當通孔金屬化物與器件之間的障壁。亦可使用其他隔離材料(例如，聚合物)及沈積技術形成隔離層130。在圖1C中，移除氧化矽之一部分，以暴露元件110。在圖1D中，沈積金屬層140，以將積體電路110與渠溝/通孔120連接。在例示性實施例中，金屬為鈦鎢合金且藉由濺鍍沈積。金屬層進一步形成防止銅擴散至矽中之障壁。矽中摻雜銅導致深層陷阱之形成，從而不利地影響電器件性質。亦可使用其他金屬合金及沈積技術來形成層140。
為了使渠溝120變成穿孔，在圖1E中執行晶圓薄化，移除渠溝之底部，從而產生貫通孔。亦移除層140之一部分以隔離一晶圓中之某些鄰接穿孔之間的電連接。在圖1F中，形成另一層氧化矽層(例如，二氧化矽)。藉由習知技術生長或沈積氧化矽。
在圖1G中，移除在通孔120側壁上形成之氧化矽，從而暴露出金屬層140。因為構成多晶圓堆疊之晶圓應極其平坦，所以在圖1H中對至少頂表面之氧化矽執行拋光。拋光可藉由此項技術中已知之化學、機械或化學機械技術來進行。
在圖1I中，將其上形成有積體電路之複數個晶圓100堆疊，以使通孔120之中心對準，從而在多晶圓堆疊中形成連續通孔170。接著，可金屬化如此形成之連續通孔，以形成貫通堆疊之均勻金屬路徑，且因為此連續通孔係在晶圓堆疊中形成之連續路徑，所以其稱為「堆疊通孔」。在圖1I之例示性實施例中，描繪5個晶圓100；然而，應理解，兩個或兩個以上晶圓在本發明之實施例之預料中。因為在每一晶圓之上表面及下表面上均存在氧化物，所以每一晶圓氧化物表面接觸鄰接之晶圓氧化物表面。此組態允許晶圓藉由接合而統一為三維晶圓堆疊。在接合製程中，在鄰接層之矽與氧原子之間形成共價鍵，從而在不需要在晶圓之間添加接合劑之情況下建立統一結構。較低的高溫(低於約200℃)及/或壓力幫助接合形成，但亦可在環境溫度下執行接合，例如，在NH4 OH浸於晶圓表面上的情況下使用電漿進行預處理。每晶圓對之接合製程時間為約3至6分鐘，其小於習知接合方法之時間。有利地，因為在接合製程期間不存在銅，因此不會出現銅擴散至晶圓之非吾人所樂見區域中的問題。此外，低溫接合之使用使多晶圓結構中之殘餘應力最小化。
在接合製程之後，在多晶圓堆疊通孔170之至少一部分側壁上形成晶種層160。視情況，此晶種層可為藉由濺鍍形成之銅晶種層，但亦可使用其他晶種層材料及方法，諸如其他金屬之無電極沈積或其他常用連接材料(諸如鋁)之濺鍍。雖然層170展示為連續的，但晶種層足夠薄以致沿著通孔側壁可能存在一些中斷。若在銅晶種層中存在中斷，則可藉由各種晶種修復製程來修復此等中斷，諸如將接合之晶圓堆疊置於晶種修復溶液中，例如，該等晶種修復溶液之鈀含量為100 mg/L、鹽酸含量為2 mol/L、浴溫為約30℃且浸泡時間為約1分鐘。在圖1J中，將銅晶種層用於電鍍製程中，以用連續且同質之銅層180填充堆疊通孔170。在一較佳實施例中，銅層180具有均勻之晶格及粒度。
圖2描繪根據本發明之另一實施例之用於形成三維接合晶圓堆疊之製程。圖2A至圖2H實質上類似於圖1A至圖1H之製程，且在此處將不再進一步描述。在圖2之製程中，堆疊穿孔170之橫截面可沿著多晶圓堆疊之厚度變化。為了改變橫截面，如圖2I中所見，基於通孔中心點將具有不同通孔大小120之個別晶圓100對準，亦即，將通孔之中心對準。用此方式，可形成具有各種橫截面形狀之穿孔(在圖5中更詳細地描繪)。在圖2I中，藉由氧化物層150使晶圓100彼此接合。將例如銅之晶種層160濺鍍至堆疊通孔170側壁之一部分上。在所描繪之實施例中，僅第一晶圓接收濺鍍之銅晶種層。在圖2J中，使用電鍍來用連續且同質之銅層180填充堆疊通孔170，該銅層較佳具有均勻之晶格及粒度。因為僅第一晶圓接收濺鍍之銅晶種層，所以電鍍以「自下而上」方式進行，亦即，首先將銅沈積在具有銅晶種層之部分上，接著向上沈積直至填充整個多晶圓堆疊通孔。「自下而上」製程可幫助改良電鍍品質並達成無空隙之銅通孔。
圖3A至圖3B及圖4A至圖4B分別描繪當包含IC之層面朝上或朝下時，自多層堆疊之頂部開始及自多層堆疊之底部開始濺鍍之銅晶種層。取決於方向，晶圓120之外表面亦在氧化物層150上接收濺鍍之銅。可取決於外表面銅層之所要位置而選擇任何技術，外表面銅層可經圖案化且用作接合焊盤/電極/連接元件。或者，可在電鍍之後移除外表面上之銅層。
圖5A至圖5D描繪可根據本發明之通孔中心對準技術形成之各個橫截面組態。藉由對準通孔中心，可將具有不同橫截面厚度之通孔120之晶圓接合在一起，以取決於多晶圓堆疊之應用而形成任意形狀之整個堆疊通孔170組態。圖5A及圖5B分別對應於圖1J及圖2J。圖5A適合於低及中等縱橫比應用，而圖5B適合於低、中等及高縱橫比應用，此係因為其涉及「自下而上」電鍍製程。
圖5C描繪適於高縱橫比應用之實施例，該應用使堆疊通孔170具有「啞鈴」橫截面形狀。在圖5D中展示高縱橫比應用之另一實施例，該應用使通孔170具有「沙漏」橫截面形狀。對於圖5C及圖5D所描繪之實施例，因為中間晶圓之通孔大小小於其他晶圓之通孔大小，所以在其他晶圓之前即可用銅完全電鍍中間晶圓之通孔。接著，沿著多晶圓厚度方向同時向上及向下沈積銅。因此，高縱橫比應用之電鍍被轉換成低或中等縱橫比應用之同時電鍍。有利地，自高縱橫比應用至低或中等縱橫比應用之電鍍之轉換不僅達成更佳之電鍍品質，而且減少電鍍時間。實質上，高縱橫比應用之實施例可應用於低或中等縱橫比應用。
本發明有利地為堆疊通孔170形成通孔金屬化物180，從而產生具有實質上均勻之晶格及粒度之同質金屬層。此外，藉由在單一製程中電鍍整個通孔，可達成藉由個別晶圓通孔至個別晶圓通孔接合所不可能達成的任意通孔橫截面形狀。製程時間實質上減少，且至半導體材料或IC器件中的非吾人所樂見之銅擴散之風險亦降低。本發明之所得多晶圓堆疊超薄，此部分歸因於圖1E及圖2E之晶圓薄化。
在電鍍之後，可將多晶圓堆疊形成為個別半導體元件。如本文中所使用，術語「半導體元件」意謂半導體器件或半導體組件。當多晶圓堆疊包括複數個半導體元件時，可藉由自堆疊中分離來形成個別元件。該分離可藉由鋸切、切割、蝕刻或其他已知分離技術來執行。在一些實施例中，多晶圓堆疊形成單個半導體器件或組件。對於此等實施例，在電鍍之後實質上完成「形成」個別半導體元件，但可包括用來形成最終器件/組件之任何精整技術。
對於一般熟習此項技術者而言，本發明之其他優點及修改將係顯而易見的。諸如上述但不限於上述之修改應認為在所附申請專利範圍之範疇內。
100．．．第一矽晶圓
110．．．元件
120．．．渠溝/通孔
130．．．氧化矽層/隔離層
140．．．金屬層
150．．．氧化物層
160．．．晶種層
170．．．多晶圓堆疊通孔
180．．．銅層/通孔金屬化物
圖1A至圖1J描繪根據本發明之形成三維晶圓堆疊之製程，該三維晶圓堆疊在通孔內具有連續且同質之導電路徑；
圖2A至圖2J描繪根據本發明之另一實施例之形成三維晶圓堆疊之製程，該三維晶圓堆疊在通孔內具有連續且同質之導電路徑；
圖3A至圖3B描繪銅晶種濺鍍製程；
圖4A至圖4B描繪另一銅晶種濺鍍製程；及
圖5A至圖5D描繪可根據本發明之製程形成之各個通孔橫截面形狀。
180．．．銅層/通孔金屬化物

Claims (7)

  1. 一種半導體元件，其包括在其上製備之一或多個積體電路、一或多個穿孔以及電連接該等積體電路與通孔之一金屬層，該半導體元件自一三維晶圓堆疊形成，包含：一第一矽晶圓，包括一或多個積體電路，其具有一第一通孔直徑之第一通孔；一第二矽晶圓，其包括定位於鄰接該第一矽晶圓之一或多個積體電路，其具有一第二通孔直徑之第二通孔，該第一及第二矽晶圓經對準，以使該第一通孔之一中心與該第二通孔之一中心重疊(coincide)；該第一與該第二矽晶圓係以不需要將該第一與第二通孔之間用金屬接合之方式接合；一金屬晶種層，其定位於該經接合之第一矽晶圓與該第二矽晶圓之該第一通孔與該第二通孔之每一者之至少一部分上；一電鍍金屬層，其定位於該金屬晶種層上方，以形成貫通該經接合之該第一與第二矽晶圓之一連續且同質之金屬化路徑。
  2. 如請求項1之半導體元件，其中該第一矽晶圓通孔具有與該第二矽晶圓通孔不同之一直徑。
  3. 如請求項1之半導體元件，其中該第一矽晶圓為該三維晶圓堆疊之底部晶圓，且具有比該第二矽晶圓之該穿孔之橫截面直徑小之一穿孔，及其中僅在該底部晶圓及其穿孔上執行形成該金屬晶種層，且自該三維晶圓堆疊之 該底部晶圓至一頂部晶圓進行電鍍。
  4. 如請求項1之半導體元件，其進一步包含：個別半導體裝置，其係自該半導體元件之分離部分形成。
  5. 如請求項1之半導體元件，其中該連續且同質之金屬化路徑具有一實質上均勻之晶格結構與粒度。
  6. 如請求項1之半導體元件，其中該晶圓堆疊包含複數個具有不同寬度之穿孔之晶圓，使得於接合之後形成之一堆疊通孔具有一任意橫截面形狀。
  7. 如請求項1之半導體元件，其中該第一與第二通孔在接合之前非金屬化。
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