TW492148B - Method for maintaining the metal connection space in dual damascene structure - Google Patents

Abstract

The present invention provides a method for maintaining the metal connection space in the dual damascene structure, which includes the following steps: sequentially forming the dielectric layer, the first anti-reflection coating on a conductive plug, wherein the conductive plug is located in a semiconductor substrate; removing part of the dielectric and the first anti-reflection coating to form the via for exposing part of the conductive plug; depositing the second anti-reflection coating along the exposed surface of the conductive plug, the dielectric and the first anti-reflection coating; using the photolithography etching technique to remove part of the dielectric, the first anti-reflection coating and the second anti-reflection coating for exposing the upper surface of the conductive plug and forming the trench.

Description

492148 V. Description of the invention (1) Field of the invention: The present invention relates to a method for maintaining metal space in a semiconductor process, and in particular to a method for maintaining metal space in a double damascene structure. Background of the Invention: In the current semiconductor metal connection process, copper connections have gradually replaced traditional Shao connections. In the copper connection process technology, in order to solve the problem that copper metal cannot be engraved with gas, the damascene process method is usually used to make the copper connection. At present, the inlaying process method includes a single inlaying process or a double inlaying process. For the process technology, refer to the ff Method for manufacturing a low dielectric constant inter-level integrated circuit structure1 disclosed in US Patent No. 5 8 0 0 18. In the dual-surface-embedding process, there is a process technology in which a via hole (v i a) is formed first, and then a trench (t r e nch) is formed. However, in this dual damascene process, if the via hole formed in the adjacent metal connection space has a head to head pattern, the photoresist used in forming the metal connection space is lithographic. After the manufacturing process, a cut issue may occur.

Page 4 492148 V. Description of the invention (2) '~-Now, take the traditional double mosaic process as an example to explain the above problems and their causes. Please refer to the first step. First, an inner metal dielectric layer (with "metal dielectncs") 14 and silicon oxynitride (SiON. 16) are sequentially deposited on the conductive plug 12 in the-semiconductor substrate 10. The oxidized stone oxide (S i 〇 N) layer 16 is used as an anti-reflection coating layer. Then, the lithographic process technology known in f is used to remove part of the metal dielectric layer 14 and The silicon oxynitride layer 16 is formed to form the interlayer hole 18. Said 'Please refer to the second figure' and then deposit a photoresist layer 20 on the silicon oxynitride layer 16 and use the exposure light wave 22 to define a channel to be defined. The photoresist layer 20 at the groove pattern position is partially exposed. The material of the photoresist layer 20 used here is a positive photoresist as an example, so there is a part of the photoresist layer 20 exposed to the exposed light wave 22. , Which will be removed after the subsequent development step. It is worth noting here that 'because the interposer holes 18 in the adjacent metal connection space to be formed have a head to head pattern (that is, The openings of the two interlayer holes 丨 8 are located on the same horizontal plane), so when the exposure light wave 2 2 hits the interlayer When the edge or side wall of the hole 18 is vertical optical correction effect (vertical optical correction effeCt) 'the edge or side wall of the interlayer hole 18 will scatter the exposure light wave 22', thus making the part of the photoresist layer 20a not to be exposed (Please refer to the third figure, which shows the semiconductor after the photoresist layer 20 has been developed.

Page 5 492148 V. Description of the Invention (3) Sectional view of the body wafer. The bottom part 2 0 b is illuminated by this scattered exposure light wave 2 2, so that a part of the photoresist layer 2 0 c remaining after the subsequent development step may cause light due to the cut i ssue of the bottom part. The resistance function is ineffective (because the remaining part of the photoresist layer 20 is cut at the bottom, causing top-to-bottom collapse.) (See the third picture). In this way, the trenches formed after the subsequent steps of the metal dielectric layer 14 and the silicon oxynitride layer 16 (the parts not protected by the photoresist layer 20) in the subsequent engraved portion and the original process design No match. Among them, the simplest way to solve the photoresist function failure caused by the bottom cut issue of the photoresist layer 20c is to change the design rule to relax the extension of the metal connection to the via hole or increase the metal connection space. Space. However, this runs counter to the design rules for trenches as component sizes shrink. Therefore, without changing the design rules, how to solve the photoresist layer 2 0 c's bottom cut problem (c u t s s u e) and cause the photoresist function to fail 'has become an urgent target for the industry.

Page 6 492148 V. Description of the invention (4) The present invention proposes a method for maintaining metal connection space in a dual damascene structure, which includes the following steps: sequentially forming a dielectric layer, a first anti-reflection coating layer on a conductive layer Above the plug, wherein the conductive plug is located in a semiconductor substrate. A part of the dielectric layer and the first anti-reflection coating layer are removed to form a via hole and expose a part of the conductive plug. A second anti-reflective coating layer is deposited along the outer surfaces of the conductive plug, the dielectric layer, and the first anti-reflective coating layer. Using the lithographic etching technique, a part of the dielectric layer, the first anti-reflection coating layer and the second anti-reflection coating layer are removed to expose the upper surface of the conductive plug and form a trench. The material of the dielectric layer includes one of the groups of silicon nitride and silicon carbide. The material of the first anti-reflection coating layer and the second anti-reflection coating layer may be selected from one of the following clusters: TiW, TiN, Ti, SiON, Ta, TaN, and the like. The method for forming the first anti-reflection coating layer and the second anti-reflection coating layer includes a chemical vapor deposition method, a physical vapor deposition method, or a plating method. In addition, after forming the trench, the method further includes the steps of removing the photoresist layer and forming a metal thin film to fill the trench and the via hole. The material of the metal film includes copper. Before forming the metal thin film, a barrier layer is formed in the trench and the via hole to prevent the metal thin film from diffusing with the dielectric layer and the semiconductor substrate. In addition, after the barrier layer is formed, a seed layer (s e d i n g 1 a y e r) is further formed on the barrier layer to strengthen the adhesion of subsequent clocks. After forming the metal thin film, it further includes performing chemical mechanical polishing on the metal thin film;

492148

CMP) to form metal wires. One of the clusters formed by the above-mentioned resistance columns: Ta, TaN, TiN, and ^ layers can be selected from the following materials. The material of the seed layer includes a material that can be formed with the metal thin film ^, T, or any combination thereof. The formation steps of the barrier layer and the seed layer can be δ. Of course, see the obstacles to decide whether to implement. Detailed description of the invention: The purpose of the present invention is to provide a method for maintaining the space of the 雔 ▲ 山 connection, so as to solve the problem that when the adjacent metal ^ wire, the metal in the embedded structure has a head-to-head form, because the lithography makes the space warm The problem of the failure of the photoresistor function of the vias. According to the present invention No. 1 caused by light failure ... Please refer to the fourth figure of the present invention. Firstly, a dielectric layer 34 and a first anti-reflection cloth are sequentially formed on a conductive plugging method as follows: Layer 'two f base 30 reflection coating layer) 36. The main road of Fuzhong μ = ntl-<1〇〇> or <m> crystal orientation of the monocrystalline stone or its ^ = guide, the substrate 30 can be ... , Divided by; 66r ... layer holes 38 and exposed 36 ΐΓ ^ Γ34 and the first anti-reflective coating layer, Leyi anti-reflective coating layer 39. Yuexiang reads the fifth picture, and then deposits a photoresist layer 40 on the second anti-reflection coating.

Page 8 492148 V. Description of the invention (6) Layer 3 9 is used, and exposure light wave 4 2 is used to locally expose the photoresist layer 40 at the position where the trench pattern is to be defined. The material of the photoresist layer 40 used here is a positive photoresist as an example, so a part of the photoresist layer 40 that is exposed to the exposure light wave 4 2 will be removed after the subsequent development step. It is worth noting here that, because the second anti-reflection coating layer 39 has the function of preventing reflection of the exposure light wave 42, when the exposure light wave 42 hits the edge or sidewall of the via hole 38, the via hole 3 8 The second anti-reflection coating layer 3 9 on the edge or the side wall will prevent the exposure light wave 4 2 from scattering out. Therefore, after the subsequent development step, the remaining part of the photoresist layer 40 does not have a so-called cut issue, and there is no so-called photoresist function failure problem (because the remaining part of the photoresist layer 4 0 bottom did not cut 'so it will not collapse.). Referring to the sixth figure, a part of the photoresist layer 40 is removed by a developing step to define a trench pattern. Since the material of the photoresist layer 40 used here is an example of a positive photoresist, only a part of the photoresist layer 40 that is illuminated by the exposed light wave 42 will be removed. Then use the remaining part of the photoresist layer 40 as a mask, and use an etching technique to remove part of the dielectric layer 34, the first anti-reflective coating layer 36, and the second anti-reflective coating layer 39, and expose them. The upper surface of the conductive plug 32 forms a trench 44. Please refer to the seventh figure, first remove the photoresist layer 40, and then deposit a metal layer on the second anti-reflection coating layer 3 9 and fill the trench 4 4 and Via hole 3 8. Finally, the metal layer is polished by chemical mechanical polishing (CMP) to remove part of the metal layer and form a metal.

Page 9 492148 V. Description of the invention (7) Conductor 46, thus completing the double-inlay metal connection process. The method for forming the metal wires 46 includes a chemical vapor deposition method, a physical vapor deposition method such as a sputtering process, or a plating method, and the material of the metal wires 46 includes copper. In addition, before forming the above metal layer, a barrier layer may be formed in the trench 44 and the interlayer hole 38 to prevent the metal layer from interfering with the dielectric layer 32 and the semiconductor substrate 30. In addition, after the barrier layer is formed, a seed layer (s e d i n g 1 a y e r) can also be formed on the barrier layer to enhance the adhesion of subsequent plating. The material of the barrier layer may be selected from one of the following clusters: Ta, TiW, TaN, TiN, Ti, or any combination thereof. The material of the seed layer may be copper or a copper alloy. Of course, the above steps of forming the barrier layer and the seed layer can be implemented as appropriate. The above-mentioned dielectric layer 34 is used as an inner metal dielectric layer, and its material may include silicon nitride, silicon carbide, and the like. If the material of the dielectric layer 34 is silicon nitride, it can be formed by plasma enhanced chemical vapor deposition (PECVD). The material of the first anti-reflection coating layer 36 includes TiW, TiN, Ti, SiON, Ta, TaN, and the like. As for the material of the second anti-reflection coating layer 39, TiW, TiN, Ti, SiON, Ta, TaN, and the like are included. The method for forming the first anti-reflection coating layer 36 and the second anti-reflection coating layer 39 includes a chemical vapor deposition method, a physical vapor deposition method, or a plating method.

492148 V. Description of the invention (8) The problem of photoresist function failure caused by exposure failure during the manufacturing process. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; any equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be considered as The protection scope of the present invention. The scope of patent protection of the present invention depends on the scope of patent application and its equivalent fields.

Page 492148 Brief description of the drawings Brief description of the drawings: The following description and the following drawings can be used to better understand the content and advantages of the present invention, of which: The cross-sectional view of the first diagram of a semiconductor wafer One embodiment of the invention 'sequentially forms an inner metal dielectric layer and a silicon oxynitride layer on a semiconductor substrate having a conductive plug, and then removes part of the inner metal dielectric layer and the silicon oxynitride layer to form a via hole. Steps; The second figure is a cross-sectional view of a semiconductor wafer, showing a step of depositing a photoresist layer on a silicon oxynitride layer and partially exposing the photoresist layer using an exposure light wave according to an embodiment of the present invention; ~ third The figure is a cross-sectional view of a semiconductor wafer, showing the steps of developing a photoresist layer according to an embodiment of the present invention; the fourth figure is a cross-sectional view of a semiconductor wafer, showing a conductive plug according to an embodiment of the present invention. Step of sequentially forming a dielectric layer, a first anti-reflection coating layer and a via hole on a semiconductor substrate, and then depositing a second anti-reflection coating layer; the fifth figure is a semiconductor A cross-sectional view of a bulk wafer, showing that according to one embodiment of the present invention, a photoresist layer is deposited on the second anti-reflection coating layer, and

Page 12 492148 The diagram briefly explains the steps of partial exposure of the photoresist layer by light waves. The sixth diagram is a cross-sectional view of a semiconductor wafer, showing that according to an embodiment of the present invention, a portion of the photoresist layer is removed, and A part of the photoresist layer is a mask, a step of forming a trench by removing a part of the dielectric layer, the first anti-reflective coating layer and the second anti-reflective coating layer; and the seventh figure is a cross-sectional view of a semiconductor wafer, According to an embodiment of the present invention, the photoresist layer is removed, and then a metal layer is deposited on the second anti-reflection coating layer to fill trenches and via holes, and then the metal layer is polished to form a metal wire. step. Part number: semiconductor substrate 10; conductive plug 12; inner metal dielectric layer 14; silicon oxynitride layer 16; via 18 18; photoresist layer 20; part of photoresist layer not to be exposed 2 0 a; bottom part of the photoresist layer not to be exposed 20 b; part of the photoresist layer 20 c remaining after the developing step; exposure light wave 2 2;

Page 13 492148 Schematic description of semiconductor substrate 3 0; conductive plug 3 2; dielectric layer 34; first anti-reflective coating layer 3 6 via hole 3 8; second anti-reflective coating layer 3 9 light Resistance layer 40; exposure light wave 4 2; trench 44; metal wire 46.

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Claims (1)

492148 VI. Scope of patent application 1. A method for forming a metal connection of a dual damascene structure, the method includes at least the following steps: forming a dielectric layer on a conductive plug, wherein the conductive plug is located in a semiconductor substrate Forming a first anti-reflection coating layer on the dielectric layer; removing a portion of the dielectric layer and the first anti-reflection coating layer to form a dielectric hole and exposing a portion of the conductive plug; Depositing a second anti-reflective coating layer along the conductive plug, the dielectric layer and the outer surface of the first anti-reflective coating layer; forming a photoresist layer on the second anti-reflective coating layer; Part of the photoresist layer is used to define a trench pattern. With the remaining part of the photoresist layer as a mask, a part of the dielectric layer, the first anti-reflection coating layer and the second anti-reflection coating are removed. Lay a layer and expose it—the upper surface of the conductive plug forms a trench, removing the photoresist layer; and forming a metal film to fill the trench and the via hole. 2. The method according to item 1 of the patent application range, wherein the material of the dielectric layer includes one of the groups of silicon nitride and silicon carbide. 3. The method according to item 1 of the patent application range, wherein the material of the first anti-reflective coating layer and the second anti-reflective coating layer may be selected from one of the following clusters: TiW, TiN, Ti, SiON, Ta and TaN. Page 15 492148 VI. Application for Patent Scope 4. For the method of the first scope of patent application, wherein the method for forming the first anti-reflective coating layer and the second anti-reflective coating layer includes chemical vapor deposition, physical Vapor deposition or electroplating. 5. The method according to item 1 of the patent application range, wherein the material of the above-mentioned metal thin film includes copper. 6. The method according to item 1 of the patent application scope, wherein after forming the metal thin film, the method further comprises a step of chemical mechanical polishing (CMP) of the metal thin film to form a metal wire. 7. The method of claim 1, before forming the metal film, further comprising forming a barrier layer in the trench and the via hole. 8. The method of claim 1, wherein after the barrier layer is formed, the method further includes a step of forming a seed layer (s e d i n g 1 a y e r) on the surface of the barrier layer. 9. The method according to item 8 of the scope of patent application, wherein the material of the seed layer includes the same material as the metal thin film. 1 0. A method for maintaining metal connection space in a dual damascene structure, the method includes at least the following steps: forming a dielectric layer on a conductive plug, wherein the conductive plug is located on Page 16 492148 VI. Patent application scope-a semiconductor substrate; forming a first anti-reflective coating layer on the dielectric layer; removing part of the dielectric layer and the first anti-reflective coating layer to form a dielectric Forming a hole and exposing a part of the conductive plug; depositing a second anti-reflective coating layer along the conductive plug, the dielectric layer and the outer surface of the first anti-reflective coating layer; forming a photoresist layer on the On the second anti-reflection coating layer; removing a part of the photoresist layer to define a trench pattern; and using the remaining part of the photoresist layer as a mask, removing part of the dielectric layer, the first The anti-reflection coating layer and the second anti-reflection coating layer expose the upper surface of the conductive plug and form a trench. —— 0 11. The method according to item 10 of the scope of patent application, wherein the material of the dielectric layer includes 1 of the groups of silicon nitride and silicon carbide. 2. The method according to item 10 of the scope of patent application, wherein the first The material of the anti-reflection coating layer and the second anti-reflection coating layer may be selected from one of the following clusters: TiW, TiN, Ti, SiON, Ta, TaN, and the like. 1 3. The method according to item 10 of the scope of patent application, wherein the method for forming the first anti-reflective coating layer and the second anti-reflective coating layer includes a chemical vapor deposition method, a physical vapor deposition method, or electroplating method. 14. The method according to item 10 of the scope of patent application, wherein the trench is formed Page 17 492148 VI. After applying for a patent, it further includes: removing the photoresist layer; and forming a metal film to fill the trench and the via hole. 15. The method according to item 14 of the scope of patent application, wherein the material of the metal thin film includes copper. 16. The method according to item 14 of the scope of patent application, wherein after forming the metal film, the method further includes a step of performing chemical mechanical polishing (CMP) on the metal film to form a metal wire. 17. The method according to item 14 of the scope of patent application, wherein before forming the metal film, it further comprises forming a barrier layer in the trench and the via hole. 18. The method according to item 14 of the scope of patent application, wherein after forming the barrier layer, the method further includes a step of forming a seed layer (s e d i n g 1 a y e r) on the upper surface of the barrier layer. 19. The method according to item 18 of the scope of patent application, wherein the material of the seed layer includes the same material as the metal thin film. Page 18