TWI447899B - 隔離結構和包含隔離結構的元件結構 - Google Patents
隔離結構和包含隔離結構的元件結構 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Description
本發明是關於一種隔離結構及包含其的元件結構,此元件結構可為用於揮發或非揮發記憶裝置的記憶體結構。
典型的記憶體陣列,例如動態隨機存取記憶體或快閃記憶體陣列,包含字元線和與字元線交錯的位元線,且可應用垂直金氧半電晶體而得4F2
記憶胞。對下個世代的4F2
記憶胞而言,至少因為簡化的中間線(middle of line,MOL)製程,埋入式位元線的設計是重要的。
圖1是先前技術中埋入式位元線和對應之垂直電晶體的結構的垂直剖面圖(a)和橫剖面圖(b),其中剖面線A-A’/B-B’對應於圖1的(a)/(b)部分。
埋入式位元線102包含半導體基底100中的溝渠108中的金屬層104和其上的摻雜多晶矽層106。金屬層104以介電層110和半導體基底100相隔。多晶矽層106兩側中的半導體基底100中形成擴散區112作為源/汲極區。溝渠108形成於各自僅含一個絕緣體的兩個傳統隔離結構114之間,且以絕緣材料116填滿。字元線118配置在埋入式位元線102上方,且以閘介電質120與垂直電晶體的通道區100a相隔。垂直電晶體的另一源/汲極區122配置在通道區100a上方。在DRAM的例子中,源/汲極區122與電容器(未繪示)耦接。
由於擴散區112靠近隔離結構114,其空乏區140延伸到隔離結構114的邊界,使通道區100a變成浮置體而無法消除在操作中產生的電洞。此浮置體效應導致不必要的漏電流,而大幅降低動態隨機存取記憶胞的電荷保留性能。
有鑑於此,本發明提供一種隔離結構,其具有隔離效果,且在用來隔離垂直電晶體時可防止浮置體效應。
本發明亦提供一種含本發明之隔離結構的元件結構。
本發明的隔離結構包括:配置於半導體基底中的溝渠中且導電類型和基底相同的摻雜半導體層、介於摻雜半導體層和基底之間的閘介電層,以及以從摻雜半導體層穿過閘介電層而來的摻質擴散而形成在基底中的擴散區。
在一個實施例中,上述隔離結構更包括在溝渠中摻雜半導體層下的金屬層,且閘介電層亦介於此金屬層和基底之間。摻雜半導體層和基底的導電類型可以是p型或n型。
本發明的元件結構包含上述本發明的隔離結構,以及隔離結構旁基底中的垂直電晶體。此垂直電晶體包括位於隔離結構中的擴散區旁的第一源/汲極區,以及第一源/汲極區上方的第二源/汲極區。第一源/汲極區和第二源/汲極區的導電型和隔離結構中的摻雜半導體層不同。
在一個實施例中,第一源/汲極區與基底中另一溝渠的埋入式位元線接觸。埋入式位元線可包含另一金屬層及其上具有源/汲極區的導電類型的另一摻雜半導體層,第一源/汲極區可由該另一摻雜半導體層的摻質擴散而形成。
由於本發明在第二導電型的第一源/汲極區旁設置具有第一導電型且摻質濃度高於基底的擴散區,而較高的摻質濃度導致較窄的空乏區,故可提供介於第一源/汲極區和隔離溝渠之間的第一導電型的通道。因此,舉例來說,當電晶體是n型且第一導電型是p型時,即可消除在元件操作中產生的電洞以預防浮置體效應。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
接著以實施例及附圖進一步說明本發明,但本發明的範疇不限於此。舉例而言,雖然實施例之元件結構是DRAM結構,然而其可改變為其他類型的記憶體結構,例如是快閃記憶體,或需要隔離結構的非記憶體結構。
圖2是本發明一實施例之隔離結構和包含此隔離結構的元件結構的垂直剖面圖。
請參照圖2,隔離結構202配置在具有溝渠204的半導體基底200中,包含摻雜半導體層206及其下溝渠204中的金屬層208、溝渠204中的閘介電層210,以及在基底200中的擴散區212。金屬層208和其上的摻雜半導體層206以閘介電層210與基底200分隔。摻雜半導體層206的導電型和基底200相同。擴散區212是以從摻雜半導體層206穿過閘介電層210而來的摻質擴散而形成,因此其導電型和摻雜半導體層206及基底200相同。溝渠204通常填滿絕緣材料214,例如是以化學氣相沈積法形成的二氧化矽(CVD SiO2
)。
半導體基底200可以是單晶矽基底。金屬層208可包含氮化鈦(TiN)或氮化鉭(TaN)。閘介電層210之材質可包含SiO2
。當欲隔離的電晶體是n型,基底200及在隔離結構202中的摻雜半導體層206的導電型是p型,其中p型摻質可以是硼。當欲隔離的電晶體是p型,基底200及在隔離結構202中的摻雜半導體層206的導電型是n型。
請再參照圖2,本實施例的元件結構可以是記憶體元件,例如DRAM元件,其包含多個上述隔離結構202及多個垂直電晶體,其中一對垂直電晶體以一個隔離結構202隔開,如下文所述。
與垂直電晶體耦接的埋入式位元線220包含在基底200中溝渠226中的金屬層222及其上的摻雜半導體層224。金屬層222和半導體基底200之間隔有介電層228,其材質可以和閘介電層210相同。擴散區230藉由摻雜半導體層224的摻質擴散而形成在摻雜半導體層224旁的半導體基底200中。摻雜半導體層224之材質可包含摻雜多晶矽,其導電型不同於半導體基底200、摻雜半導體層206和在隔離結構202中的擴散區212。字元線232跨越埋入式位元線220的上方而配置,其上視圖可類似圖1所示之字元線118。
在圖2中,垂直電晶體包含作為第一源/汲極區的部份擴散區230、該部份擴散區230上方的通道區200a(或200b、200c或200d,以下記為200a/b/c/d)、通道區200a/b/c/d上的第二源/汲極區234、在通道區200a/b/c/d兩側的部份字元線232,以及介於該部分字元線232和通道區200a/b/c/d之間的閘介電層(未繪示)。字元線232、閘介電層和通道區200a/b/c/d的配置方式可以如圖1所示,其中字元線118和通道100a以閘介電層120隔開。
當上述元件結構是DRAM結構時,各個作為記憶胞的通過電晶體的垂直電晶體以第二源極/汲極區234與電容器耦接。此電容器可以是冠狀電容器,其結構為於本發明所屬技術領域中具通常知識者所熟知,故此處不再贅述。
在以上實施例中,兩條埋入式位元線220配置在基底200中的一個溝渠226中。然而在其他實施例中,形成較窄溝渠而在各個溝渠中僅配置一條埋入式位元線亦可行。
在一實施例中,隔離結構202的溝渠204的寬度W1
是(1/2)F,通道區200a/b/c/d或第二源/汲極區234的寬度W2
是1F,且形成兩條埋入式位元線220的溝渠226的寬度W3
是(3/2)F,如此各個記憶胞佔有的面積為4F2
{=[(1/2)F/2+1F+(3/2)F/2]×2F}。一個記憶胞在垂直紙面方向上的尺寸為“2F”的原因請參照圖1(b)。
在本實施例的記憶胞中,摻質濃度高於p-
或n-
摻雜基底200的p或n摻雜擴散區212配置在n+
或p+
摻雜之第一源/汲極區230的旁邊。因為較高的摻質濃度導致較窄的空乏區240,故可於第一源/汲極區230和隔離溝渠204之間提供p或n摻雜之通道。因此,舉例來說,當電晶體導電型是n型且擴散區212導電型是p型時,即可清除元件操作中產生的電洞以防止浮置體效應,如圖2所示(請見通道區200d)。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200...半導體基底
102、220...位元線
104、208、222...金屬層
106...多晶矽層
108、204、226...溝渠
110、228...介電層
110a、200a、200b、200c、200d...通道區
112、212、230...擴散區
114、202...隔離結構
116、214...絕緣材料
118、232...字元線
120、210‧‧‧閘介電層
122‧‧‧源/汲極區
140、240‧‧‧空乏區
206、224‧‧‧摻雜半導體層
234‧‧‧第二源/汲極區
圖1是先前技術中埋入式位元線與對應之垂直電晶體的結構的垂直剖面圖(a)和橫剖面圖(b),其中剖面線A-A’/B-B’對應於圖1的(a)/(b)部分。
圖2是本發明一實施例之隔離結構和包含此隔離結構的元件結構的垂直剖面圖。
200...半導體基底
200a/b/c/d...通道區
202...隔離結構
204、226...溝渠
206、224...摻雜半導體層
208、222...金屬層
210...閘介電層
212、230...擴散區
214...絕緣材料
220...位元線
228...介電層
232...字元線
234...第二源/汲極區
240...空乏區
Claims (16)
- 一種隔離結構,包括:一摻雜半導體層,位於一半導體基底的一溝渠中,且具有與該基底相同的導電型;一閘介電層,位於該摻雜半導體層和該基底之間;以及一擴散區,位於該基底中,且該擴散區配置在一源/汲極區旁,是以從該摻雜半導體層穿過該閘介電層而來的摻質擴散而形成,其中該擴散區具有第一導電類型且該源/汲極區具有第二導電類型。
- 如申請專利範圍第1項所述之隔離結構,更包括一金屬層,位於該溝渠中及該摻雜半導體層下,其中該閘介電層亦介於該金屬層及該基底之間。
- 如申請專利範圍第2項所述之隔離結構,其中該金屬層的材質包括氮化鈦(TiN)或氮化鉭(TaN)。
- 如申請專利範圍第1項所述之隔離結構,其中該第一導電類型是p型,且該第二導電類型是n型。
- 如申請專利範圍第1項所述之隔離結構,其中該第一導電類型是n型,且該第二導電類型是p型。
- 如申請專利範圍第1項所述之隔離結構,其中該摻雜半導體層的材質包括摻雜多晶矽。
- 一種元件結構,包括:一半導體基底,具有第一導電型;一隔離結構,包括:具有該第一導電型且位於該基底 的第一溝渠中的第一摻雜半導體層、介於該第一摻雜半導體層及該基底之間的一閘介電層,以及位於該基底中,以從該第一摻雜半導體層穿過該閘介電層而來的摻質擴散而形成的一擴散區;第一垂直電晶體,位於該隔離結構的第一側的該基底中,且包括該擴散區旁的第一源/汲極區及位在該第一源/汲極區上方的第二源/汲極區,該第一源/汲極區及該第二源/汲極區都具有第二導電型。
- 如申請專利範圍第7項所述之元件結構,其中該隔離結構更包括位於該第一溝渠中及該第一摻雜半導體層下的一金屬層,且該閘介電層亦介於該金屬層及該基底之間。
- 如申請專利範圍第7項所述之元件結構,其中該第一導電型是p型且該第二導電型是n型。
- 如申請專利範圍第7項所述之元件結構,其中該第一導電型是n型且該第二導電型是p型。
- 如申請專利範圍第7項所述之元件結構,其是一動態隨機存取記憶體結構,且更包括耦接到該第二源/汲極區的一電容器。
- 如申請專利範圍第11項所述之元件結構,其中該第一源/汲極區與一埋入式位元線接觸,且該埋入式位元線位於該基底中的第二溝渠中。
- 如申請專利範圍第12項所述之元件結構,其中該埋入式位元線包括:一金屬層,以及該金屬層上具有該第二導電型的第二摻雜半導體層,且該第二摻雜半導體層與 該第一源/汲極區接觸。
- 如申請專利範圍第13項所述之元件結構,其中該第一源/汲極區是以從該第二摻雜半導體層而來的摻質擴散而形成。
- 如申請專利範圍第12項所述之元件結構,其中有二埋入式位元線平行配置在該第二溝渠中。
- 如申請專利範圍第7項所述之元件結構,更包括位於該隔離結構之第二側,即該隔離結構之該第一側之相反側的第二垂直電晶體。
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US20120248518A1 (en) | 2012-10-04 |
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