TWI424489B - 半導體功率元件的製作方法 - Google Patents
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Description
本發明係有關於半導體功率元件的製作方法，特別是有關於一種可修補晶格缺陷之半導體功率元件的製作方法。
功率半導體元件常應用於電源管理的部分，例如，切換式電源供應器、電腦中心或周邊電源管理IC、背光板電源供應器或馬達控制等等用途，其種類包含有絕緣閘雙極性電晶體(insulated gate bipolar transistor，IGBT)、金氧半場效電晶體(metal-oxide-semiconductor field effect transistor，MOSFET)與雙載子接面電晶體(bipolar junction transistor，BJT)等元件。其中，由於MOSFET可節省電能且可提供較快的元件切換速度，因此被廣泛地應用各領域之中。
已知在功率元件中，基底的設計為P型磊晶層與N型磊晶層交替設置，因此在基底中會存在有多個垂直於基底表面的PN接面，且該些PN接面互相平行，此又稱為超級接面結構。在習知製作該超級接面結構的技術中，乃先於一第一導電型基材(如：N型基材)上成長一第一導電型磊晶層(如：N型磊晶層)，然後利用一第一遮罩於第一導電型磊晶層上蝕刻出複數個溝渠。接著於各溝渠內形成一第二導電型磊晶層(如：P型磊晶層)，並使第二導電型磊晶層之上表面與第一導電型磊晶層之上表面切齊，至此，各溝渠內已填滿第二導電型磊晶層並且被第一導電型磊晶層所環繞。而複數個第二導電型磊晶層與第一導電型磊晶層的接觸面即形成超級接面結構。
然而，上述先前技藝仍有問題需要進一步克服。舉例來說，由於製程上之限制，於形成第二導電型磊晶層時，在其內部往往存在有許多晶格缺陷(defects)，例如：接縫缺陷(seam defects)、空穴缺陷(void defects)以及晶格錯位(lattice dislocation)。該些缺陷會影響磊晶層之良率與導電性，進而影響功率元件在生產過程中之良率。可知，仍需一種超級接面之功率半導體元件之製作方法，以製作具有較少晶格缺陷之功率半導體元件，進而提升功率半導體元件之良率，此乃業界努力之目標。
本發明的主要目的即在於提供一種半導體功率元件之製作方法，能夠提升半導體功率之電性及良率。
根據本發明之較佳實施例，本發明披露一種半導體功率元件的製作方法。首先提供一基底，其上包含有至少一半導體層以及一墊層。接著，於墊層及半導體層內蝕刻出至少一溝槽，並於溝槽內及墊層上形成一摻質來源層，隨後，進行一熱趨入製程，將摻質來源層的摻質擴散至半導體層，接著，進行一快速高溫處理，以修補位於該摻質來源層內以及摻質來源層與半導體層接面間的缺陷，最後，進行一研磨製程，去除該墊層上的該摻質來源層。
本發明提供一快速熱處理製程(rapid thermal processing，RTP)，用以修補存在於摻質來源層內以及摻質來源層與半導體層接面間之缺陷，進而提升半導體功率元件之良率。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
請參閱第1圖至第10圖，其為依據本發明一較佳實施例所繪示的製作功率元件之方法示意圖，其中所製作之功率元件可包含溝槽式之功率電晶體，而圖式中相同的元件或部位沿用相同的符號來表示。需注意的是，圖式係以說明為目的，並未依照原尺寸作圖。
如第1圖所示，首先提供一第一導電型基底12，在本發明之較佳具體實施例中，第一導電型基底12為N型摻雜矽基底，其可作為功率電晶體之一汲極。第一導電型基底12上定義有一晶胞區(cell region) 14、一圍繞晶胞區14之週邊耐壓區(termination region)16、以及一設置在晶胞區14以及週邊耐壓區16間之過渡區(transition region)15，其中晶胞區14係用於設置具有開關功能之電晶體元件，而週邊耐壓區16係包括用於阻擋晶胞區14之高強度電場向外擴散之耐壓結構。接著，可利用磊晶製程於第一導電型基底12上形成一第一導電型半導體層18。根據本發明之最佳實施例，半導體層18可以是一N型磊晶層，例如，其可以利用一化學氣相沉積製程或其它合適方法形成，而半導體層18同時可作為所欲形成之功率元件之飄移層(drift layer)。接著，於半導體層18上形成一墊層20，此墊層20可分為上、下兩部分，上層墊層20a之組成可以為氮化矽(Si3N4)，而下層墊層20b之組成可以為矽氧層(SiO2)。
接著，仍如第1圖所示，利用微影及蝕刻製程，於墊層20以及半導體層18中形成至少一溝槽24、26，其中，溝槽24位於晶胞區域14內，而溝槽26位於週邊耐壓區16內。溝槽24、26之形成方式，舉例來說，可先於墊層20上塗佈一光阻層(圖未示)，接著利用具有溝槽圖案之光罩作為曝光遮罩對光阻層(圖未示)進行一曝光及顯影製程，再利用圖案化之光阻層作為蝕刻遮罩而對墊層20進行一非等向性蝕刻製程，將光罩上的溝槽圖案轉移至墊層20，之後去除圖案化之光阻層，再進行乾蝕刻製程，將溝槽圖案轉移至半導體層18中。當然，上述形成溝槽的方法僅為例示，溝槽24、26亦可以利用其它方法形成。本發明之溝槽的形狀、位置、深度、寬度、長度與數量等特徵不需受到第1圖之溝槽24、26所侷限，而可根據實際之產品設計需求或製程特性而調整，例如溝槽24、26之佈局可以具有條狀(strip)、六邊形(hexagonal)或螺旋狀(spiral)等圖案。
如第2圖所示，接著，形成一摻質來源層30於溝槽24、26內以及於墊層20上，其中摻質來源層30具有一第二導電型，例如P型，且摻質來源層30之材料包含磊晶矽、多晶矽或非晶矽，但不限於此。然後，進行一熱趨入製程，將摻質來源層30之摻質擴散至半導體層18中，該摻質可包含有磷。至此，溝渠24、26周圍以及底部之半導體層18內已形成具有一第二導電型基體摻質區34，其中第二導電型基體摻質區34與半導體層18之間形成垂直PN接面，亦即超級接面。
仍如第2圖所示，由於在習知技術中之製程限制，摻質來源層30內以及摻質來源層與半導體層接面間往往存在有許多晶格缺陷(defects)31、32、33，例如：接縫缺陷(seam defects)31、空穴缺陷(void defects)32以及晶格錯位(lattice dislocation)33。該些缺陷會影響摻質來源層30之良率與導電性，進而影響功率元件在生產過程中之良率。有鑑於此，根據本發明之較佳實施例，即施以一正面光源的快速高溫處理，且該快速高溫處理之溫度介於1200℃至1800℃，用以修補該摻質來源層30內的缺陷。其中，快速高溫處理可包括瞬間熱退火(spike thermal annealing)、雷射熱退火(laser thermal annealing，LTA)或雷射瞬間退火(laser spike annealing，LSA)，但不限於此。值得注意的是，透過該快速高溫處理，可有效消除或降低存在於摻質來源層30內之缺陷31、32、33，進而提升半導體功率元件之良率。
之後，如第3圖所示，進行一研磨製程，去除該墊層20上的摻質來源層30(圖未示)，直至暴露出墊層20之上表面。緊接著可以繼續進行一回蝕刻製程，移除位於溝渠24、26內的部分摻質來源層30，暴露出溝渠24、26之上半部，形成一凹陷結構27。此時，溝槽24、26內之摻質來源層30之上表面約略與半導體層18之上表面切齊。
如第4圖所示，接著，移除位於半導體層18上方之墊層20(圖未示)，暴露出半導體層18之上表面。並且於晶胞區14以及過渡區15內之半導體層18之上表面形成一閘極氧化層48，接著於週邊耐壓區16之溝槽26上方形成一場氧化層40，其中場氧化層40之組成可包含氧矽化物。
如第5圖所示，接著，全面沈積一閘極導電層50。根據本發明之較佳實施例，閘極導電層50可包含摻雜多晶矽(doped poly-silicon)。並進行一微影製程，形成一光阻圖案51，其包含複數個開口51a，暴露出部分之閘極導電層50。該光阻圖案51之用途乃用以轉移其圖形至閘極導電層50。
如第6圖所示，進行一蝕刻製程，經由開口51a(圖未示)蝕刻部分的閘極導電層50(圖未示)，形成閘極圖案50a、50b，其中閘極圖案50b位於週邊耐壓區16內之場氧化層40上方。隨後，去除光阻圖案51(圖未示)。接下來，進行一自對準離子佈植製程，於溝槽24、26旁的導體層18中形成一第二導電型離子井52，例如，P型井。接著，可繼續進行一熱趨入製程，藉以活化第二導電型離子井52內之摻質。
如第7圖所示，進行一微影製程，形成一光阻圖案53，其包括一開口53a，暴露出晶胞區14。再進行另一離子佈植製程，於晶胞區14內之第二導電型離子井52內形成一第一導電型源極摻雜區54。於此離子佈植製程中，由於過渡區15以及週邊耐壓區16受到光阻圖案53保護，因此不會產生摻雜區。隨後，去除光阻圖案53。接著，可繼續進行一熱趨入製程。
如第8圖所示，於晶胞區14、過渡區15以及週邊耐壓區16之上表面全面沈積一襯墊層56以及一絕緣層58。根據本發明之較佳實施例，此絕緣層58之組成可以包含硼磷矽玻璃(BPSG)。之後，可以繼續進行一回流(reflow)製程以及/或回蝕刻製程，使絕緣層58表面平坦化。
如第9圖所示，蝕刻晶胞區14、過渡區15以及週邊耐壓區16內之部分絕緣層58以及襯墊層56，俾使晶胞區14內之各溝渠24上方形成一接觸洞開口60，暴露出溝渠24內之摻質來源層30表面及部分之第一導電型源極摻雜區54。同時，於過渡區15以及週邊耐壓區16分別形成至少一接觸洞開口62，以暴露出部分離子井52之表面以及部分閘極圖案50b之表面。接下來，進行一離子佈植製程，於晶胞區14內之摻質來源層30表面形成一第二導電型摻雜區66，同時於過渡區15內之部分離子井52表面形成一第二導電型摻雜區66。經由該離子佈植製程，可增加半導體層18於後續製程中與金屬之導電性。
如第10圖所示，之後，全面形成一導電層(圖未示)，導電層可包含金屬材料，例如鈦、鋁等，該導電層覆蓋於絕緣層58上方並且填入接觸洞開口60、62內，且填入金屬材料之前可於接觸洞開口60、62中先形成黏合層或/與阻障層。接著，再利用另一道微影蝕刻製程去除週邊耐壓區16內之部分之導電層(圖未示)，以形成至少一閘極導線74a與至少一源極電極74b。其中，閘極導線74a直接接觸閘極圖案50b之表面，且源極電極74b直接接觸並覆蓋於晶胞區域14及過渡區15之絕緣層58以及部分半導體層18上。接著，於過渡區15以及週邊耐壓區16內形成一層保護層76，該保護層76覆蓋住閘極導線74a，但曝露出源極電極74b，藉以形成本發明之功率元件。
綜上所述，根據本發明之較佳實施例，乃提供一快速熱處理製程(rapid thermal processing，RTP)，用以修補存在於磊晶層中之晶格缺陷，進而提升半導體功率元件之良率。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12．．．N型摻雜矽基底
14．．．晶胞區
16．．．週邊耐壓區
15．．．過渡區
18．．．半導體層
20．．．墊層
20a．．．上層墊層
20b．．．下層墊層
24、26．．．溝槽
30．．．摻質來源層
34．．．基體摻質區
31．．．接縫缺陷
32．．．空穴缺陷
33．．．晶格錯位
48．．．閘極氧化層
40．．．場氧化層
50．．．閘極導電層
50a．．．閘極圖案
50b．．．閘極圖案
51．．．光阻圖案
52．．．離子井
53．．．光阻圖案
53a．．．開口
54．．．源極摻雜區
56．．．襯墊層
58．．．絕緣層
60．．．接觸洞開口
62．．．接觸洞開口
66．．．摻雜區
68．．．接觸插塞
74a．．．閘極導線
74b．．．源極電極
76．．．保護層
第1至第10圖所繪示的是根據本發明之較佳實施例之一種半導體功率元件之製作方法示意圖。
12．．．N型摻雜矽基底
14．．．晶胞區
16．．．週邊耐壓區
15．．．過渡區
18．．．半導體層
20．．．墊層
20a．．．上層墊層
20b．．．下層墊層
24、26．．．溝槽
30．．．摻質來源層
34．．．基體摻質區
Claims (11)
- 一種半導體功率元件的製作方法，包含有：提供一基底，其上包含有至少一半導體層以及一墊層；於該墊層及該半導體層內蝕刻出至少一溝槽；於該溝槽內及該墊層上形成一摻質來源層；進行一熱趨入製程，將該摻質來源層的摻質擴散至該半導體層；進行一快速高溫處理，以修補該摻質來源層內以及摻質來源層與半導體層接面間的缺陷；以及進行一研磨製程，去除該墊層上的該摻質來源層。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中在進行一研磨製程之後，另包含有：去除該墊層，以曝露出該半導體層。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該研磨製程係為化學機械研磨製程。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該快速高溫處理的光源係正面光源，且該快速高溫處理的溫度介於1200℃至1800℃之間。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該基底及該半導體層具有一第一導電型。
- 如申請專利範圍第5項所述之半導體功率元件的製作方法，其中該第一導電型為N型。
- 如申請專利範圍第6項所述之半導體功率元件的製作方法，其中該摻質來源層具有一第二導電型。
- 如申請專利範圍第7項所述之半導體功率元件的製作方法，其中該第二導電型為P型。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該摻質來源層包含有磊晶矽、多晶矽或非晶矽。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該摻質包含有磷。
- 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該墊層包含有氮化矽層或矽氧層。
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| TWI441261B (zh) * | 2011-05-13 | 2014-06-11 | Anpec Electronics Corp | 半導體功率元件的製作方法 |
| US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| TW201440145A (zh) * | 2013-04-09 | 2014-10-16 | Anpec Electronics Corp | 半導體功率元件的製作方法 |
| TW201440118A (zh) * | 2013-04-11 | 2014-10-16 | Anpec Electronics Corp | 半導體功率元件的製作方法 |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| WO2016028944A1 (en) | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
| JP2018117070A (ja) * | 2017-01-19 | 2018-07-26 | エイブリック株式会社 | 半導体装置及びその製造方法 |
| CN107195685B (zh) * | 2017-06-30 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | 超级结器件的制造方法 |
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