TWI417894B - 於動態隨機存取記憶體架構之定址期間實施省電之結構及方法 - Google Patents

於動態隨機存取記憶體架構之定址期間實施省電之結構及方法 Download PDF

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Publication number
TWI417894B
TWI417894B TW097109476A TW97109476A TWI417894B TW I417894 B TWI417894 B TW I417894B TW 097109476 A TW097109476 A TW 097109476A TW 97109476 A TW97109476 A TW 97109476A TW I417894 B TWI417894 B TW I417894B
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TW
Taiwan
Prior art keywords
column
array
address decoder
decoder logic
partitions
Prior art date
Application number
TW097109476A
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English (en)
Chinese (zh)
Other versions
TW200903508A (en
Inventor
Gerald K Bartley
Darryl J Becker
John M Borkenhagen
Philip R Germann
William P Hovis
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Ibm
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Filing date
Publication date
Priority claimed from US11/688,897 external-priority patent/US7492662B2/en
Priority claimed from US12/024,443 external-priority patent/US7791978B2/en
Application filed by Ibm filed Critical Ibm
Publication of TW200903508A publication Critical patent/TW200903508A/zh
Application granted granted Critical
Publication of TWI417894B publication Critical patent/TWI417894B/zh

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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Dram (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Semiconductor Memories (AREA)
TW097109476A 2007-03-21 2008-03-18 於動態隨機存取記憶體架構之定址期間實施省電之結構及方法 TWI417894B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/688,897 US7492662B2 (en) 2007-03-21 2007-03-21 Structure and method of implementing power savings during addressing of DRAM architectures
US12/024,443 US7791978B2 (en) 2008-02-01 2008-02-01 Design structure of implementing power savings during addressing of DRAM architectures

Publications (2)

Publication Number Publication Date
TW200903508A TW200903508A (en) 2009-01-16
TWI417894B true TWI417894B (zh) 2013-12-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW097109476A TWI417894B (zh) 2007-03-21 2008-03-18 於動態隨機存取記憶體架構之定址期間實施省電之結構及方法

Country Status (2)

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JP (2) JP2008234662A (ja)
TW (1) TWI417894B (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8811110B2 (en) * 2012-06-28 2014-08-19 Intel Corporation Configuration for power reduction in DRAM

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182727A (en) * 1991-10-09 1993-01-26 Mitsubishi Semiconductor America, Inc. Array layout structure for implementing large high-density address decoders for gate array memories
US5546353A (en) * 1995-05-26 1996-08-13 National Semiconductor Corporation Partitioned decode circuit for low power operation
US6295595B1 (en) * 1999-04-21 2001-09-25 Tower Semiconductor Ltd. Method and structure for accessing a reduced address space of a defective memory
US6415421B2 (en) * 2000-06-13 2002-07-02 Mentor Graphics Corporation Integrated verification and manufacturability tool
US6631089B1 (en) * 2001-07-06 2003-10-07 Halo Lsi, Inc. Bit line decoding scheme and circuit for dual bit memory array
US6788612B2 (en) * 2001-04-23 2004-09-07 Aplus Flash Technology, Inc. Flash memory array structure suitable for multiple simultaneous operations
US6804148B2 (en) * 2002-10-22 2004-10-12 Atmel Corporation Flash memory architecture with page mode erase using NMOS and PMOS row decoding scheme
US20060047493A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Memory management to enable memory deep power down mode in general computing systems
US7009910B2 (en) * 2001-08-23 2006-03-07 Winbond Electronics Corporation Semiconductor memory having a flexible dual-bank architecture with improved row decoding
US20060187697A1 (en) * 2004-04-02 2006-08-24 Virage Logic Corp. ROM with a partitioned source line architecture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214585A (ja) * 1986-03-14 1987-09-21 Mitsubishi Electric Corp 半導体記憶装置
JP3157666B2 (ja) * 1993-12-22 2001-04-16 日本電気株式会社 半導体メモリ
JP3908338B2 (ja) * 1997-06-30 2007-04-25 富士通株式会社 半導体記憶装置
JP2002093159A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
TWI225260B (en) * 2002-10-07 2004-12-11 Samsung Electronics Co Ltd Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture
TWI233619B (en) * 2002-11-19 2005-06-01 Samsung Electronics Co Ltd Circuits and methods for changing page length in a semiconductor memory device
KR100614640B1 (ko) * 2003-09-26 2006-08-22 삼성전자주식회사 워드라인 부분활성화 커맨드를 갖는 반도체메모리장치
US7793037B2 (en) * 2005-05-31 2010-09-07 Intel Corporation Partial page scheme for memory technologies

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182727A (en) * 1991-10-09 1993-01-26 Mitsubishi Semiconductor America, Inc. Array layout structure for implementing large high-density address decoders for gate array memories
US5546353A (en) * 1995-05-26 1996-08-13 National Semiconductor Corporation Partitioned decode circuit for low power operation
US6295595B1 (en) * 1999-04-21 2001-09-25 Tower Semiconductor Ltd. Method and structure for accessing a reduced address space of a defective memory
US6415421B2 (en) * 2000-06-13 2002-07-02 Mentor Graphics Corporation Integrated verification and manufacturability tool
US6788612B2 (en) * 2001-04-23 2004-09-07 Aplus Flash Technology, Inc. Flash memory array structure suitable for multiple simultaneous operations
US6631089B1 (en) * 2001-07-06 2003-10-07 Halo Lsi, Inc. Bit line decoding scheme and circuit for dual bit memory array
US7009910B2 (en) * 2001-08-23 2006-03-07 Winbond Electronics Corporation Semiconductor memory having a flexible dual-bank architecture with improved row decoding
US6804148B2 (en) * 2002-10-22 2004-10-12 Atmel Corporation Flash memory architecture with page mode erase using NMOS and PMOS row decoding scheme
US20060187697A1 (en) * 2004-04-02 2006-08-24 Virage Logic Corp. ROM with a partitioned source line architecture
US20060047493A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Memory management to enable memory deep power down mode in general computing systems

Also Published As

Publication number Publication date
TW200903508A (en) 2009-01-16
JP2014222559A (ja) 2014-11-27
JP2008234662A (ja) 2008-10-02
JP5973508B2 (ja) 2016-08-23

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