TWI413213B - 對齊之邏輯元件格與互連線繞線架構 - Google Patents

對齊之邏輯元件格與互連線繞線架構 Download PDF

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Publication number
TWI413213B
TWI413213B TW095105355A TW95105355A TWI413213B TW I413213 B TWI413213 B TW I413213B TW 095105355 A TW095105355 A TW 095105355A TW 95105355 A TW95105355 A TW 95105355A TW I413213 B TWI413213 B TW I413213B
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TW
Taiwan
Prior art keywords
pitch
transistor
adjusted
winding pitch
winding
Prior art date
Application number
TW095105355A
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English (en)
Chinese (zh)
Other versions
TW200636915A (en
Inventor
Shannon Vance Morton
Original Assignee
Nvidia Technology Uk Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Nvidia Technology Uk Ltd filed Critical Nvidia Technology Uk Ltd
Publication of TW200636915A publication Critical patent/TW200636915A/zh
Application granted granted Critical
Publication of TWI413213B publication Critical patent/TWI413213B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW095105355A 2005-02-24 2006-02-17 對齊之邏輯元件格與互連線繞線架構 TWI413213B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/066,041 US7287237B2 (en) 2005-02-24 2005-02-24 Aligned logic cell grid and interconnect routing architecture

Publications (2)

Publication Number Publication Date
TW200636915A TW200636915A (en) 2006-10-16
TWI413213B true TWI413213B (zh) 2013-10-21

Family

ID=36927791

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095105355A TWI413213B (zh) 2005-02-24 2006-02-17 對齊之邏輯元件格與互連線繞線架構

Country Status (5)

Country Link
US (1) US7287237B2 (enExample)
EP (1) EP1861801A2 (enExample)
JP (1) JP4773466B2 (enExample)
TW (1) TWI413213B (enExample)
WO (1) WO2006090126A2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060281221A1 (en) * 2005-06-09 2006-12-14 Sharad Mehrotra Enhanced routing grid system and method
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8448102B2 (en) * 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7401310B1 (en) * 2006-04-04 2008-07-15 Advanced Micro Devices, Inc. Integrated circuit design with cell-based macros
US7735041B2 (en) * 2006-08-03 2010-06-08 Chipx, Inc. Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8607180B2 (en) * 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
KR102661932B1 (ko) * 2016-12-16 2024-04-29 삼성전자주식회사 멀티플 패터닝 리소그래피를 위한 집적 회로, 집적 회로의 설계를 위한 컴퓨팅 시스템 및 컴퓨터 구현 방법
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102373540B1 (ko) 2018-04-19 2022-03-11 삼성전자주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US20020007478A1 (en) * 2000-07-17 2002-01-17 Li-Chun Tien Routing definition to optimize layout design of standard cells
US6629308B1 (en) * 2000-07-13 2003-09-30 Xilinx, Inc. Method for managing database models for reduced programmable logic device components

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073154B1 (en) * 2002-05-21 2006-07-04 Altera Corporation Apparatus and methods for interconnect zones and associated cells in integrated circuits
JP2004342757A (ja) * 2003-05-14 2004-12-02 Toshiba Corp 半導体集積回路及びその設計方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6629308B1 (en) * 2000-07-13 2003-09-30 Xilinx, Inc. Method for managing database models for reduced programmable logic device components
US20020007478A1 (en) * 2000-07-17 2002-01-17 Li-Chun Tien Routing definition to optimize layout design of standard cells

Also Published As

Publication number Publication date
EP1861801A2 (en) 2007-12-05
US7287237B2 (en) 2007-10-23
WO2006090126A3 (en) 2006-12-07
US20060195810A1 (en) 2006-08-31
TW200636915A (en) 2006-10-16
JP4773466B2 (ja) 2011-09-14
WO2006090126A2 (en) 2006-08-31
JP2008532132A (ja) 2008-08-14

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