JP4773466B2 - 配列された論理セル格子及び相互接続ルーティング構造 - Google Patents

配列された論理セル格子及び相互接続ルーティング構造 Download PDF

Info

Publication number
JP4773466B2
JP4773466B2 JP2007556650A JP2007556650A JP4773466B2 JP 4773466 B2 JP4773466 B2 JP 4773466B2 JP 2007556650 A JP2007556650 A JP 2007556650A JP 2007556650 A JP2007556650 A JP 2007556650A JP 4773466 B2 JP4773466 B2 JP 4773466B2
Authority
JP
Japan
Prior art keywords
pitch
transistor
routing
resized
initial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007556650A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008532132A5 (enExample
JP2008532132A (ja
Inventor
シャノン・ヴァンス・モートン
Original Assignee
イセラ・インコーポレーテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by イセラ・インコーポレーテッド filed Critical イセラ・インコーポレーテッド
Publication of JP2008532132A publication Critical patent/JP2008532132A/ja
Publication of JP2008532132A5 publication Critical patent/JP2008532132A5/ja
Application granted granted Critical
Publication of JP4773466B2 publication Critical patent/JP4773466B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2007556650A 2005-02-24 2006-02-17 配列された論理セル格子及び相互接続ルーティング構造 Expired - Fee Related JP4773466B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/066,041 2005-02-24
US11/066,041 US7287237B2 (en) 2005-02-24 2005-02-24 Aligned logic cell grid and interconnect routing architecture
PCT/GB2006/000573 WO2006090126A2 (en) 2005-02-24 2006-02-17 Aligned logic cell grid and interconnect routing architecture

Publications (3)

Publication Number Publication Date
JP2008532132A JP2008532132A (ja) 2008-08-14
JP2008532132A5 JP2008532132A5 (enExample) 2010-06-17
JP4773466B2 true JP4773466B2 (ja) 2011-09-14

Family

ID=36927791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007556650A Expired - Fee Related JP4773466B2 (ja) 2005-02-24 2006-02-17 配列された論理セル格子及び相互接続ルーティング構造

Country Status (5)

Country Link
US (1) US7287237B2 (enExample)
EP (1) EP1861801A2 (enExample)
JP (1) JP4773466B2 (enExample)
TW (1) TWI413213B (enExample)
WO (1) WO2006090126A2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060281221A1 (en) * 2005-06-09 2006-12-14 Sharad Mehrotra Enhanced routing grid system and method
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8448102B2 (en) * 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7401310B1 (en) * 2006-04-04 2008-07-15 Advanced Micro Devices, Inc. Integrated circuit design with cell-based macros
US7735041B2 (en) * 2006-08-03 2010-06-08 Chipx, Inc. Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8607180B2 (en) * 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
KR102661932B1 (ko) * 2016-12-16 2024-04-29 삼성전자주식회사 멀티플 패터닝 리소그래피를 위한 집적 회로, 집적 회로의 설계를 위한 컴퓨팅 시스템 및 컴퓨터 구현 방법
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102373540B1 (ko) 2018-04-19 2022-03-11 삼성전자주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020007478A1 (en) * 2000-07-17 2002-01-17 Li-Chun Tien Routing definition to optimize layout design of standard cells

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6629308B1 (en) * 2000-07-13 2003-09-30 Xilinx, Inc. Method for managing database models for reduced programmable logic device components
US7073154B1 (en) * 2002-05-21 2006-07-04 Altera Corporation Apparatus and methods for interconnect zones and associated cells in integrated circuits
JP2004342757A (ja) * 2003-05-14 2004-12-02 Toshiba Corp 半導体集積回路及びその設計方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020007478A1 (en) * 2000-07-17 2002-01-17 Li-Chun Tien Routing definition to optimize layout design of standard cells

Also Published As

Publication number Publication date
EP1861801A2 (en) 2007-12-05
US7287237B2 (en) 2007-10-23
WO2006090126A3 (en) 2006-12-07
US20060195810A1 (en) 2006-08-31
TW200636915A (en) 2006-10-16
WO2006090126A2 (en) 2006-08-31
JP2008532132A (ja) 2008-08-14
TWI413213B (zh) 2013-10-21

Similar Documents

Publication Publication Date Title
JP4773466B2 (ja) 配列された論理セル格子及び相互接続ルーティング構造
JP7668763B2 (ja) セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ）
JP5080280B2 (ja) 集積回路のトランジスタ性能を最適化するための方法
US7492013B2 (en) Systems and arrangements to interconnect components of a semiconductor device
US9691768B2 (en) Nanowire or 2D material strips interconnects in an integrated circuit cell
JP3461443B2 (ja) 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
US9400862B2 (en) Cells having transistors and interconnects including nanowires or 2D material strips
US9378320B2 (en) Array with intercell conductors including nanowires or 2D material strips
US20060190893A1 (en) Logic cell layout architecture with shared boundary
US6560753B2 (en) Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit
US7725870B2 (en) Method for radiation tolerance by implant well notching
Vaidyanathan et al. Rethinking ASIC design with next generation lithography and process integration
US9947765B2 (en) Dummy gate placement methodology to enhance integrated circuit performance
Kheterpal et al. Routing architecture exploration for regular fabrics
Ryzhenko et al. Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries
JP3996735B2 (ja) 半導体装置
Tai et al. Morphed standard cell layouts for pin length reduction
US7698681B2 (en) Method for radiation tolerance by logic book folding
JP4441541B2 (ja) 半導体装置
Lazzari et al. A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits
US6907588B2 (en) Congestion estimation for register transfer level code
Garg et al. Lithography driven layout design
Lin et al. Performance study of VeSFET-based, high-density regular circuits
Lazzari¹ et al. GENERATION STRATEGY FOR STATIC CMOS
JP2005093947A (ja) 半導体集積回路のレイアウト装置および方法ならびこれらを使用して製造された半導体装置

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091201

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100301

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100308

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20100401

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100817

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20101117

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20101125

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101217

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110524

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110623

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140701

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees