TWI412040B - 非揮發記憶體單元之低電壓程式化系統與方法 - Google Patents

非揮發記憶體單元之低電壓程式化系統與方法 Download PDF

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Publication number
TWI412040B
TWI412040B TW096149097A TW96149097A TWI412040B TW I412040 B TWI412040 B TW I412040B TW 096149097 A TW096149097 A TW 096149097A TW 96149097 A TW96149097 A TW 96149097A TW I412040 B TWI412040 B TW I412040B
Authority
TW
Taiwan
Prior art keywords
voltage
word line
line
gate
volatile memory
Prior art date
Application number
TW096149097A
Other languages
English (en)
Chinese (zh)
Other versions
TW200842891A (en
Inventor
Dana Lee
Jeffrey Lutze
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/614,879 external-priority patent/US7944749B2/en
Priority claimed from US11/614,884 external-priority patent/US7623389B2/en
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Publication of TW200842891A publication Critical patent/TW200842891A/zh
Application granted granted Critical
Publication of TWI412040B publication Critical patent/TWI412040B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
TW096149097A 2006-12-21 2007-12-20 非揮發記憶體單元之低電壓程式化系統與方法 TWI412040B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/614,879 US7944749B2 (en) 2006-12-21 2006-12-21 Method of low voltage programming of non-volatile memory cells
US11/614,884 US7623389B2 (en) 2006-12-21 2006-12-21 System for low voltage programming of non-volatile memory cells

Publications (2)

Publication Number Publication Date
TW200842891A TW200842891A (en) 2008-11-01
TWI412040B true TWI412040B (zh) 2013-10-11

Family

ID=39462459

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096149097A TWI412040B (zh) 2006-12-21 2007-12-20 非揮發記憶體單元之低電壓程式化系統與方法

Country Status (5)

Country Link
EP (1) EP2102868B1 (enExample)
JP (1) JP5166442B2 (enExample)
KR (1) KR101402076B1 (enExample)
TW (1) TWI412040B (enExample)
WO (1) WO2008079725A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5657063B2 (ja) * 2013-07-01 2015-01-21 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
US10332593B2 (en) * 2015-09-14 2019-06-25 Toshiba Memory Corporation Semiconductor memory device configured to sense memory cell threshold voltages in ascending order
US10707226B1 (en) * 2019-06-26 2020-07-07 Sandisk Technologies Llc Source side program, method, and apparatus for 3D NAND

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002096632A2 (en) * 2001-05-25 2002-12-05 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US20040080980A1 (en) * 2002-10-23 2004-04-29 Chang-Hyun Lee Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices
US6822909B1 (en) * 2003-04-24 2004-11-23 Advanced Micro Devices, Inc. Method of controlling program threshold voltage distribution of a dual cell memory device
US6894924B2 (en) * 2001-10-22 2005-05-17 Samsung Electronics Co., Ltd. Operating a non-volatile memory device
US7002843B2 (en) * 2004-01-27 2006-02-21 Sandisk Corporation Variable current sinking for coarse/fine programming of non-volatile memory
US7057940B2 (en) * 2003-08-19 2006-06-06 Powerchip Semiconductor Corp. Flash memory cell, flash memory cell array and manufacturing method thereof
US7099193B2 (en) * 2003-09-08 2006-08-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device, electronic card and electronic apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002056316A1 (en) * 2001-01-12 2002-07-18 Hitachi, Ltd. Nonvolatile semiconductor storage device
US20060017085A1 (en) * 2004-07-26 2006-01-26 Prateep Tuntasood NAND flash memory with densely packed memory gates and fabrication process
JP4902972B2 (ja) * 2005-07-15 2012-03-21 ルネサスエレクトロニクス株式会社 不揮発性記憶素子の制御方法
JP2007058964A (ja) * 2005-08-23 2007-03-08 Renesas Technology Corp 不揮発性半導体記憶装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002096632A2 (en) * 2001-05-25 2002-12-05 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US6894924B2 (en) * 2001-10-22 2005-05-17 Samsung Electronics Co., Ltd. Operating a non-volatile memory device
US20040080980A1 (en) * 2002-10-23 2004-04-29 Chang-Hyun Lee Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices
US6822909B1 (en) * 2003-04-24 2004-11-23 Advanced Micro Devices, Inc. Method of controlling program threshold voltage distribution of a dual cell memory device
US7057940B2 (en) * 2003-08-19 2006-06-06 Powerchip Semiconductor Corp. Flash memory cell, flash memory cell array and manufacturing method thereof
US7099193B2 (en) * 2003-09-08 2006-08-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device, electronic card and electronic apparatus
US7002843B2 (en) * 2004-01-27 2006-02-21 Sandisk Corporation Variable current sinking for coarse/fine programming of non-volatile memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Jae-Duk Lee et al., "A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated by GIDL Current,"Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st, 12-16 Feb. 2006. *

Also Published As

Publication number Publication date
JP2010514089A (ja) 2010-04-30
EP2102868A2 (en) 2009-09-23
WO2008079725A3 (en) 2008-08-14
WO2008079725A2 (en) 2008-07-03
KR20090101163A (ko) 2009-09-24
TW200842891A (en) 2008-11-01
JP5166442B2 (ja) 2013-03-21
EP2102868B1 (en) 2016-02-24
KR101402076B1 (ko) 2014-05-30

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