TWI399794B - 用於含金屬層之加強成核的半導體表面電漿處理 - Google Patents

用於含金屬層之加強成核的半導體表面電漿處理 Download PDF

Info

Publication number
TWI399794B
TWI399794B TW095141533A TW95141533A TWI399794B TW I399794 B TWI399794 B TW I399794B TW 095141533 A TW095141533 A TW 095141533A TW 95141533 A TW95141533 A TW 95141533A TW I399794 B TWI399794 B TW I399794B
Authority
TW
Taiwan
Prior art keywords
plasma
metal
layer
oxide
semiconductor substrate
Prior art date
Application number
TW095141533A
Other languages
English (en)
Other versions
TW200739689A (en
Inventor
Dina H Triyoso
Olubunmi O Adetutu
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200739689A publication Critical patent/TW200739689A/zh
Application granted granted Critical
Publication of TWI399794B publication Critical patent/TWI399794B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/2822Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3141Deposition using atomic layer deposition techniques [ALD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Description

用於含金屬層之加強成核的半導體表面電漿處理
本發明一般係與半導體處理有關;更明確地說,係與用於含金屬層之加強成核的半導體表面電漿處理有關。
半導體裝置愈來愈需要用到以氧化矽為基礎之薄閘極介電膜。然而,以SiOn 為基礎之薄閘極介電膜會導致閘極洩漏增加。如今已有考慮以高介電常數(K)的薄膜取代以SiOn 為基礎的閘極介電質。傳統上,高介電常數(K)膜是利用原子層沉積法(ALD)之已知製程形成,然而,該薄膜會導致該高介電常數介電質在含矽表面上的成核狀況很差。先前試圖解決此問題的方法包括了運用標準清潔程序(例如,SC-2清潔程序)。然而,此步驟使用ALD製程成核沉積該閘極介電材料,沉積化學氧化物之一薄層。因此,該化學氧化物就成為該閘極介電質的一整體部分,其影響該閘極介電質的整合性以及比例。此外,該化學氧化物會減少該閘極介電薄膜的總體介電常數。
因此,需要用於含金屬層之加強成核的半導體表面電漿處理方法。
一方面,本發明提供一種用於形成一介電層之方法。該方法可包括提供一半導體表面,並蝕刻該半導體基板之一薄層以便曝露該半導體表面,其中經曝露之該表面是疏水性。該方法可進一步包括將利用電漿處理該半導體基板之經曝露之 該表面,以中和與經曝露之該表面相關聯的疏水性。該方法可進一步包括運用一原子層沉積製程在經電漿處理之該表面的一頂部表面上形成一含金屬層。
另一方面,本發明提供一種用於形成一高常數介電層的方法。此方法可包括蝕刻一半導體基板之一薄層以便曝露該半導體基板之一表面,其中經曝露之該表面是疏水性。該方法可進一步包括利用電漿處理該半導體基板之經曝露之該表面,以中和與經曝露之該表面相關聯的疏水性並將該半導體基板的一頂層轉變成一非晶形式。該方法可進一步包括運用一原子層沉積製程在經電漿處理之該表面的一頂部表面上形成一含金屬層。
圖1係於處理期間一半導體裝置的斷面圖,此處理與本發明之一具體實施例相符。半導體裝置(100)可包括一基板(10)。就一形式來說,基板(10)可以是一塊半導體,例如矽、鍺化矽,或鍺,或任何適當的半導體材料。或者,基板(10)可植入為一絕緣體上矽(SOI)基板。如第一步驟之部分,該基板(10)的頂部表面(12)可經蝕刻以移除任何氧化物,例如,在基板(10)頂部表面(12)上所形成的原生氧化物。舉例來說,厚度可能係10到20埃的薄層(14)可被蝕刻除去。任何適當的蝕刻技術(例如乾式蝕刻或溼式蝕刻)均可採用。舉例來說,可用氟氫酸蝕刻層(14)。雖然圖1顯示一被蝕刻之底部層基板(10),一類似於半導體裝置(100)的其他級之層亦可同樣蝕刻。
接下來,如圖2所示,半導體裝置(100)的頂部表面(16)可經受一電漿處理(18)。使用氫氟酸可使基板(10)的頂部表面(16)成為疏水性。舉例來說,可執行一原位電漿處理以中和疏水性的表面(例如,半導體(100)的頂部表面(16))。電漿處理(18)可運用功率範圍100瓦到1000瓦來執行。執行電漿處理(18)的持續時間係1秒到60秒。在電漿點火階段之後可用任何鈍性氣體,例如氬、氮、氦、氙,或以上之一組合作為該電漿處理的一部分。如圖3所示,電漿處理可導致一電漿改質層(20)。利用電漿處理該半導體基板的經曝露之該表面可改進電漿改質層(20)之頂部表面(22)上含金屬層的成核。如電漿處理的結果,電漿改質層(20)可被改變成更為非晶性形式。舉例來說,電漿改質層(20)之深度可為10到100埃。為進一步協助將電漿改質層(20)轉變成一非晶形式的製程,可使用額外的氣體,例如,氟化物(例如,NF3 、F2 或B3 F6 )、氯化物(例如,Cl2 ),及/或氮化物(N2 或NH3 )。
接著,如圖4所示,使用一原子層沉積製程,可在電漿改質層(20)的一頂部表面(22)上沉積一薄的閘極介電質,例如金屬氧化物。薄閘極介電層(例如,一含金屬層)可使用多次原子層沉積製程循環形成。每一循環可導致至少一部分金屬氧化物層可形成在電漿改質層(20)之頂部表面(22)上。運用多次原子層沉積循環沉積前緣(24、26和28)可導致一含金屬層(30)之形成。舉例來說,含金屬層(30)可為任何金屬氧化物層,例如:二氧化鉿、氧化鑭、氧化釔、氧化鈦、氧化鉭或具有其他稀土金屬或過渡金屬的氧化物。該金屬氧化物也可包括任意數目的金屬,例如,氧化鋁鉿、其他金屬鋁酸鹽等等。或者,含金屬層(30)可為任何金屬矽酸鹽,例如,矽酸鉿、矽酸鑭,以及具有其他稀土金屬或過渡金屬的任何其他矽酸鹽類。額外地和/或可替換地,含金屬層(30)也可包括金屬-矽-氧氮化合物,例如HfSix Oy Nz .
在前述規格書中,已參考特定具體實施例來說明本發明。然而,習知此項技術者應瞭解可進行各種修改及變化而不脫離如以下申請專利範圍所提出之本發明之範疇。因此,本說明書及附圖應視為說明性,而非限制性,且希望所有此類修改均包括於本發明之範疇內。
以上已針對特定具體實施例而說明好處、其他優點及問題解決方案。然而,好處、優點、問題解決方案、及引起任何利益、優點、或解決方案發生或變得突出之(多個)元件,均不應視為任一或所有申請專利之一關鍵、必須或本質特徵或元件。本文中所使用的術語"包括"、"包含"或其任何其他變化均意欲涵蓋非專有內含項,使得包含一元件清單的製程、方法、物品或裝置不僅包括這等元件,而且還包括未明確列出或此類製程、方法、物品或裝置固有的其他元件。
10...基板
12...頂部表面
14...薄層
16...頂部表面
18...電漿處理
20...薄層
22...頂部表面
24...沉積前緣
26...沉積前緣
28...沉積前緣
30...薄層
100...半導體裝置
本發明以範例方式而加以說明,並不受限於該等附圖,其中相同參考指示相同元件,且其中:圖1係於處理期間一半導體裝置的斷面圖,此處理與本發明之一具體實施例相符;圖2係利用電漿處理一半導體裝置的斷面圖,此電漿處理與本發明之一具體實施例相符;圖3係一具有電漿改質層之半導體裝置的斷面圖,此電漿改質層與本發明之一具體實施例相符;以及圖4係一具有閘極介電質之半導體裝置的斷面圖,此閘極介電質與本發明之一具體實施例相符。
習知此項技術者應瞭解,出於簡單及清楚起見而說明圖示中的元件且不必比例縮放。例如,該等圖示中的某些元件可能相對於其他元件而加以放大以促進理解本發明之具體實施例。
10...基板
20...電漿改質層
22...頂部表面
24...沉積前緣
26...沉積前緣
28...沉積前緣
30...含金屬層
100...半導體裝置

Claims (20)

  1. 一種用於形成介電層的方法,其包括:提供一半導體基板;蝕刻該半導體基板之一薄層以便曝露該半導體基板之一表面,其中經曝露之該表面係疏水性;利用電漿處理該半導體基板之經曝露之該表面以中和與經曝露之該表面相關聯之疏水性並在深度10至100埃之間形成一非晶態形式之一電漿改質層;以及運用一原子層沉積製程在經電漿處理之該表面的一頂部表面上形成作為介電質之一含金屬層。
  2. 如請求項1之方法,其中蝕刻包括運用氫氟酸以蝕刻該薄層。
  3. 如請求項1之方法,其中該電漿係原地實施。
  4. 如請求項1之方法,其中該含金屬層包括至少金屬氧化物。
  5. 如請求項4之方法,其中該金屬氧化物係下列至少一項:二氧化鉿、氧化鑭、氧化釔、氧化鈦、氧化鉭、氧化鋯,或一具有其他稀土金屬或過渡金屬的氧化物,或以上任何組合。
  6. 如請求項1之方法,其中該含金屬層包括金屬矽酸鹽和金屬-矽-氧氮化合物之至少一項。
  7. 如請求項6之方法,其中該金屬矽酸鹽係下列至少一項:矽酸鉿、矽酸鑭,以及一具有其他稀土金屬或過渡金屬之任何其他矽酸鹽,或以上任何組合。
  8. 如請求項1之方法,其中利用電漿處理該半導體基板之經曝露之該表面用以產生一電漿改質層。
  9. 如請求項8之方法,其中利用電漿處理該半導體基板之經曝露之該表面以改進該電漿改質層之頂部表面上的該含金屬層之成核。
  10. 如請求項1之方法,其中經曝露之該表面係利用功率範圍為100瓦到500瓦的電漿處理,而且持續時間範圍是1到60秒。
  11. 一種用於形成一高介電常數層的方法,其包括:蝕刻該半導體基板之一薄層以曝露該半導體基板之一表面;利用電漿處理該半導體基板之經曝露之該表面以將該半導體基板一頂層改變成一非晶形式;以及運用一原子層沉積製程在經電漿處理之該表面一頂部表面之上形成一含金屬層。
  12. 如請求項11之方法,其中蝕刻包括運用氫氟酸以蝕刻該薄層。
  13. 如請求項11之方法,其中該電漿係原地實施。
  14. 如請求項11之方法,其中該含金屬層包括至少金屬氧化物。
  15. 如請求項14之方法,其中該金屬氧化物係下列至少一項:二氧化鉿、氧化鑭、氧化釔、氧化鈦、氧化鉭、氧化鋯,或一具有其他稀土金屬或過渡金屬之氧化物,或以上任何組合。
  16. 如請求項11之方法,其中該含金屬層包括至少金屬矽酸鹽。
  17. 如請求項16之方法,其中該金屬矽酸鹽係下列至少一項:矽酸鉿、矽酸鑭,以及其他任何具有其他稀土金屬或過渡金屬的矽酸鹽,或以上任何組合。
  18. 如請求項11之方法,其中利用電漿處理該半導體基板之經曝露之該表面以產生一電漿改質層。
  19. 如請求項18之方法,其中利用電漿處理該半導體基板之經曝露之該表面以改進該電漿改質層之頂部表面上的該含金屬層之成核。
  20. 如請求項11之方法,其中該含金屬層包括至少金屬-矽-氧氮化物。
TW095141533A 2005-11-30 2006-11-09 用於含金屬層之加強成核的半導體表面電漿處理 TWI399794B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/290,320 US7618902B2 (en) 2005-11-30 2005-11-30 Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

Publications (2)

Publication Number Publication Date
TW200739689A TW200739689A (en) 2007-10-16
TWI399794B true TWI399794B (zh) 2013-06-21

Family

ID=38088093

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095141533A TWI399794B (zh) 2005-11-30 2006-11-09 用於含金屬層之加強成核的半導體表面電漿處理

Country Status (5)

Country Link
US (2) US7618902B2 (zh)
KR (1) KR20080074144A (zh)
CN (1) CN101427354B (zh)
TW (1) TWI399794B (zh)
WO (1) WO2007111699A2 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7618902B2 (en) * 2005-11-30 2009-11-17 Freescale Semiconductor, Inc. Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer
US7943527B2 (en) * 2008-05-30 2011-05-17 The Board Of Trustees Of The University Of Illinois Surface preparation for thin film growth by enhanced nucleation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW535238B (en) * 2001-03-23 2003-06-01 Dow Corning Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
US6674138B1 (en) * 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US20040147101A1 (en) * 2000-11-24 2004-07-29 Pomarede Christophe F. Surface preparation prior to deposition

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
US7326655B2 (en) * 2005-09-29 2008-02-05 Tokyo Electron Limited Method of forming an oxide layer
US7618902B2 (en) * 2005-11-30 2009-11-17 Freescale Semiconductor, Inc. Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040147101A1 (en) * 2000-11-24 2004-07-29 Pomarede Christophe F. Surface preparation prior to deposition
TW535238B (en) * 2001-03-23 2003-06-01 Dow Corning Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
US6674138B1 (en) * 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices

Also Published As

Publication number Publication date
WO2007111699A3 (en) 2008-12-11
US20100035434A1 (en) 2010-02-11
CN101427354A (zh) 2009-05-06
TW200739689A (en) 2007-10-16
CN101427354B (zh) 2011-07-13
KR20080074144A (ko) 2008-08-12
US20070123056A1 (en) 2007-05-31
US8030220B2 (en) 2011-10-04
WO2007111699A2 (en) 2007-10-04
US7618902B2 (en) 2009-11-17

Similar Documents

Publication Publication Date Title
US7071122B2 (en) Field effect transistor with etched-back gate dielectric
KR100519798B1 (ko) 향상된 생산성을 갖는 박막 형성 방법
US9330937B2 (en) Etching of semiconductor structures that include titanium-based layers
US7132360B2 (en) Method for treating a semiconductor surface to form a metal-containing layer
US7045073B2 (en) Pre-etch implantation damage for the removal of thin film layers
JP3590636B2 (ja) パターン内に間隔層を製造する方法
JP7168741B2 (ja) 選択的表面改質を利用する構造の充填技術
CN110739211B (zh) 使用等离子体改性的介电材料的选择性循环干式蚀刻工艺
CN110739204B (zh) 用于介电材料的蚀刻的预清洁
KR100716689B1 (ko) 높은 k 값의 게이트 유전체를 갖는 반도체 장치를제조하는 선택적 에칭 공정
JP2004134753A (ja) 多重の誘電率と多重の厚さを有するゲート絶縁体層を形成する方法
TW201517211A (zh) 沉積-蝕刻-沉積製程中的表面處理
US6867102B2 (en) Method for making a semiconductor device having a high-k gate dielectric
KR20150141135A (ko) 개질 처리 방법 및 반도체 장치의 제조 방법
TW200849392A (en) Method for depositing a high quality silicon dielectric film on germanium with high quality interface
JP7459420B2 (ja) 高度なパターン形成用途のためのインサイチュでの選択的堆積及びエッチング
JP3756456B2 (ja) 半導体装置の製造方法
TWI399794B (zh) 用於含金屬層之加強成核的半導體表面電漿處理
JP6946463B2 (ja) ワードライン抵抗を低下させる方法
US20080026584A1 (en) LPCVD gate hard mask
JP7037384B2 (ja) 半導体装置の製造方法
JP2004031394A (ja) 半導体装置の製造方法
TW564519B (en) Process for forming shallow trench isolation (STI) with corner protection layer
WO2005013374A1 (ja) 半導体装置および半導体装置の製造方法
US8748260B2 (en) Method for manufacturing nano-crystalline silicon material for semiconductor integrated circuits

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees