TWI387064B - 半導體封裝基板及其製法 - Google Patents

半導體封裝基板及其製法 Download PDF

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Publication number
TWI387064B
TWI387064B TW096115687A TW96115687A TWI387064B TW I387064 B TWI387064 B TW I387064B TW 096115687 A TW096115687 A TW 096115687A TW 96115687 A TW96115687 A TW 96115687A TW I387064 B TWI387064 B TW I387064B
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Taiwan
Prior art keywords
conductive
layer
semiconductor package
package substrate
electrical connection
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TW096115687A
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English (en)
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TW200845321A (en
Inventor
Wen Hung Hu
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Unimicron Technology Corp
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Priority to TW096115687A priority Critical patent/TWI387064B/zh
Priority to US12/114,517 priority patent/US7847400B2/en
Publication of TW200845321A publication Critical patent/TW200845321A/zh
Priority to US12/908,777 priority patent/US8269354B2/en
Application granted granted Critical
Publication of TWI387064B publication Critical patent/TWI387064B/zh

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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Description

半導體封裝基板及其製法
本發明係有關於一種半導體封裝基板及其製法，尤指一種形成有導電柱之半導體封裝基板及其製法。
在現行覆晶(Flip Chip)技術中，於積體電路(IC)之半導體晶片的主動面上具有電極墊，而有機電路板亦具有相對應該電極墊之電性連接墊，於該半導體晶片之電極墊與電路板之電性連接墊之間形成有焊錫結構或其他導電黏著材料，該焊錫結構或導電黏著材料提供該半導體晶片以及電路板之間的電性連接以及機械性的連接，相關製程即如第1A至1F圖所示。
請參閱第1A圖，首先，提供一表面具有複數電性連接墊111及線路112之電路板11。
請參閱第1B圖，接著於該形成有電性連接墊111之電路板11表面上以印刷、旋塗或貼合形成一絕緣保護層12，並藉由圖案化製程於該絕緣保護層12中形成開孔120以露出部份該電性連接墊111上表面。
請參閱第1C圖，在該絕緣保護層12及開孔120表面形成有一導電層13，該導電層13主要作為後述電鍍焊錫材料所需之電流傳導路徑。
請參閱第1D圖，接著於該電路板11上形成一阻層14，並經圖案化製程，以於該阻層14中形成開孔140並露出該絕緣保護層開孔120。
請參閱第1E圖，再對該電路板11進行電鍍(Electroplating)製程，藉由該導電層13具導電特性，俾在進行電鍍時作為電流傳導路徑，以在該阻層開孔140及絕緣保護層開孔120中形成一導電柱15，且該導電柱15頂緣係突出於該絕緣保護層開孔120，並在阻層開孔140中形成側緣151。
請參閱第1F圖，移除該阻層14及其所覆蓋之導電層13，使該導電柱15於該絕緣保護層12表面形成凸出之側緣151。
然，上述習知製法中，該絕緣保護層開孔120之尺寸及該阻層開孔140之尺寸皆十分微細，一般約50μm－60μm，故對位極為不易，為使該阻層開孔140可與該絕緣保護層開孔120對位，通常將該阻層開孔140之尺寸加大，藉以降低對位的困難度及提高製程對位準確度，而當絕緣保護層開孔120孔徑更小時，受限於機台精度，阻層開孔140之尺寸亦可能加大至絕緣保護層開孔120之兩倍。
惟加大該阻層開孔140之尺寸，導致該導電柱15之頂面產生側緣151，使各該導電柱15之間的間距必須加大，如此即無法於該導電柱15頂面上形成細間距之預焊錫凸塊。
且該導電柱15之側緣151係凸出於該絕緣保護層12表面，容易因溫度變化及CTE(coefficient of thermal expansion)差異產生應力，並集中於該導電柱15與側緣151之間，而產生破壞的情況。
因此，如何提出一種半導體封裝電路板及其製法，以形成細間距之導電柱，實已成為目前業界亟待克服之難題。
鑒於上述之缺失，本發明之一目的即在提供一種半導體封裝基板及其製法，得於基板本體之電性連接墊上形成細間距之導電柱。
本發明之又一目的在於提供一種半導體封裝基板及其製法，得避免產生應力集中的情況。
本發明之再一目的在於提供一種半導體封裝基板及其製法，得限制底部填充材料之流動位置。
本發明之另一目的在於提供一種半導體封裝基板及其製法，得降低封裝後之整體厚度。
為達上述及其他目的，本發明提出一種半導體封裝基板，係包括：基板本體，至少一表面具有複數電性連接墊；複數導電柱，係分別完全包覆各該電性連接墊；以及絕緣保護層，係形成於該基板本體表面，且具有顯露部以露出該導電柱。
該基板本體具有電性連接墊之表面復包括有複數線路，該基板本體表面復包括有介電層，於該介電層表面具有該電性連接墊及線路，且於該基板本體之介電層與電性連接墊，以及介電層與線路之間具有一導電層。
本發明復提供一種半導體封裝基板之製法，係包括：提供至少一表面具有複數電性連接墊之基板本體；於各該電性連接墊表面上形成有一導電柱，使該導電柱完全包覆該電性連接墊之頂面及側表面；以及於該基板本體表面形成一絕緣保護層，且該絕緣保護層表面形成顯露部，以藉該顯露部露出該導電柱。
該基板本體具有電性連接墊之表面復包括有複數線路，而該電性連接墊及線路之製程係包括：提供一表面具有介電層之基板本體；於該介電層表面形成一導電層；於該導電層上形成一第一阻層，且於該第一阻層中形成複數開口以露出部份之導電層；以及於該等開口中電鍍形成該電性連接墊及線路。
該導電柱之製程係包括：移除該第一阻層；於該導電層上形成有一第二阻層，且於該第二阻層中對應該電性連接墊位置形成有開孔，以完全露出該電性連接墊之頂面及側表面；以及於該等開孔中之電性連接墊表面形成該導電柱；復包括移除該第二阻層及其所覆蓋之導電層。
上述之半導體封裝基板及其製法中，該顯露部係為複數未貫穿該絕緣保護層之凹部，俾以各別露出各該導電柱之頂面及其周圍側表面；或該顯露部係為複數貫穿該絕緣保護層之開孔，並露出該基板本體部份表面，俾以對應完全露出各該導電柱之頂面及側表面；或該顯露部係為一未貫穿該絕緣保護層之凹陷區，以露出各該導電柱之頂面及其周圍側表面；或該顯露部係為一貫穿該絕緣保護層之開槽，並露出該基板本體部份表面，以完全露出各該導電柱之頂面及側表面。
本發明之半導體封裝基板及其製法，該導電柱之頂端無習知之側緣，而可避免產生應力集中，且該導電柱完全包覆在該電性連接墊之頂面及側表面，得有較佳之結合強度以避免破壞，且該電性連接墊之寬度與一般線路層之線寬相近，既使該導電柱完全包覆該電性連接墊，該導電柱之尺寸亦小於習知具側緣之導電柱，而得以形成細間距之導電柱；之後復於該基板本體表面形成該絕緣保護層，且該絕緣保護層表面形成一顯露部，而該顯露部係為複數凹部、複數開孔、一凹陷區或一開槽以露出該等導電柱之頂面及其周圍側表面，俾於形成該導電柱後再形成該絕緣保護層，俾可避免習知製程中先形成絕緣保護層再電鍍形成導電柱，因阻層與絕緣保護層之間開孔對位問題，導致該導電柱頂端於絕緣保護層表面形成側緣，使得該導電柱之間的間距無法縮小；並可藉由該凹部、開孔、凹陷區或開槽限制該底部填充材料之流動位置以避免產生溢膠的情況；又得藉由該凹部、開孔、凹陷區或開槽以降低半導體封裝件之整體厚度。
以下係藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
[第一實施例]
請參閱第2A至2J圖，係為本發明之半導體封裝基板及其製法。
請參閱第2A圖，首先提供至少一表面形成有介電層21之基板本體20，且於該介電層21上形成一導電層22，該導電層22主要作為後述電鍍金屬材料所需之電流傳導路徑，其可由金屬或沉積數層金屬層所構成，如選自銅、錫、鎳、鉻、鈦、銅－鉻等單層或多層結構，或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導電高分子材料。
請參閱第2B圖，於該導電層22上利用印刷、旋塗或貼合等方式形成一第一阻層23，且該第一阻層23藉由曝光、顯影等圖案化製程以形成有複數個開口230，以露出基板本體20表面部分之導電層22，該第一阻層23可為一例如乾膜或液態光阻等光阻層(Photoresist)。
請參閱第2C圖，於該第一阻層23之開口230中之導電層22表面進行電鍍(Electroplating)製程，藉由該導電層22具導電特性，俾在進行電鍍時作為電流傳導路徑，以在該等開口230中電鍍形成有線路24及電性連接墊241，且該線路24或電性連接墊241電性連接該基板本體20(圖式中未表示)；惟關於基板本體形成導電線路及電性連接墊之製程技術繁多，乃業界所周知之製程技術，非本發明之重點，為避免模糊本發明之技術特徵，故未再予贅述。
請參閱第2D圖，移除該第一阻層23，以露出該線路24、電性連接墊241及未被遮覆之導電層22。
請參閱第2E圖，於該線路24、電性連接墊241及導電層22表面形成有一第二阻層25，該第二阻層25係為一例如乾膜或液態光阻等光阻層(Photoresist)，再藉由曝光、顯影等圖案化製程使該第二阻層25形成複數個開口250以露出該電性連接墊241，俾以完全露出該電性連接墊241之頂面241a及側表面241b。
請參閱第2F圖，對該基板本體20進行電鍍製程，藉由該導電層22具導電特性作為電流傳導路徑，以在該等開口250中之電性連接墊241表面上電鍍形成一導電柱26，使該導電柱26完全包覆該電性連接墊241之頂面241a及側表面241b，得有較佳之結合強度以避免破壞，且該電性連接墊241之寬度與一般線路層24之線寬相近，既使該導電柱26完全包覆該電性連接墊241，且該導電柱241之尺寸亦小於習知具側緣151之導電柱15，而得以形成細間距之導電柱15；該導電柱26之材料可為諸如鉛、錫、銀、銅、金、鉍、銻、鋅、鎳、鋯、鎂、銦、碲以及鎵等金屬之其中一者；惟，依實際操作之經驗，由於銅為成熟之被電鍍材料且成本較低，該導電柱26以由電鍍銅所構成者為較佳，但非以此為限。
請參閱第2G圖，移除該第二阻層25及其所覆蓋之導電層22。
請參閱第2H圖，於該基板本體20之介電層21表面形成一絕緣保護層27；於本實施例中，係利用印刷、旋塗及貼合之任一方式將該絕緣保護層27形成於該基板本體20之介電層21、線路24及導電柱26表面，該絕緣保護層27可為感光性絕緣防焊材料，例如以環氧樹脂為基材之綠漆等，具有縮錫與防焊特性之材料所製成，該絕緣保護層27亦可為有機及無機之抗氧化膜之任一具有縮錫與防焊特性之材料所製成，並非以綠漆為限。
請參閱第2I圖，於該絕緣保護層27表面置有一具有不透光區域281之光罩28，使未為該不透光區域281所覆蓋之絕緣保護層27進行曝光(硬化)。
請參閱第2J圖，之後移除該絕緣保護層27未被曝光部份(未硬化)之表面，進而於該絕緣保護層27表面形成複數個係為凹部270之顯露部，俾以對應顯露各該導電柱26之頂面26a及其周圍側表面26b，之後該絕緣保護層27之凹部270下未被曝光部份再進行曝光，使該凹部270完全硬化成形；該絕緣保護層27之凹部270係環繞在該導電柱26之周圍，且凹部270未貫穿該絕緣保護層27，使得後續封裝製程中，於該導電柱26頂端形成之焊錫凸塊的形狀接近圓形，俾以降低應力集中及接合時之橋接異常。
另請參閱第2J’圖，或將該絕緣保護層27未被曝光部份(未硬化)全部移除，以成為複數個係為開孔271之顯露部，並露出該基板本體20之介電層21部份表面，俾以各別完全露出該導電柱26之頂面26a及側表面26b，使該導電柱26周圍無絕緣保護層27，而於封裝接合時銲錫完整包覆導電柱26，以降低封裝之應力。
本發明復提出一種半導體封裝基板，其係包括：基板本體20，至少一表面具有線路24及複數電性連接墊241；複數導電柱26，係各別完全包覆形成於該電性連接墊241之頂面241a及側表面241b；以及絕緣保護層27，係形成於該基板本體20表面，且於該絕緣保護層27表面形成有複數係為凹部270之顯露部，其中，該凹部270未貫穿該絕緣保護層27，並對應露出各該導電柱26之頂面26a及其周圍側表面26b。
該半導體封裝基板之絕緣保護層27表面，亦可形成有複數貫穿絕緣保護層27之開孔271，並露出該基板本體部份表面，以對應完全露出各該導電柱26之頂面26a及側表面26b。
該基板本體20之介電層21與電性連接墊241，以及介電層21與線路24之間具有一導電層22，該導電層22之材料係選自銅、錫、鎳、鉻、鈦及銅－鉻合金所組群組之其中一者，或該導電層22可為導電高分子材料。
該導電柱26之材料係選自鉛、錫、銀、銅、金、鉍、銻、鋅、鎳、鋯、鎂、銦、碲以及鎵等金屬之其中一者。
[第二實施例]
請參閱第3A及3B圖，係為本發明之另一實施製法，與前一實施例之不同處在於該光罩之不透光區域係全部覆蓋各該導電柱，並包括各該導電柱之間的區域。
如第3A圖所示，係接續第一實施例之第2I圖，該光罩28之不透光區域281’係完全覆蓋在各該導電柱26，以及各該導電柱26之間的區域，使未為該不透光區域281所覆蓋之絕緣保護層27進行曝光。
請參閱第3B圖，之後移除該絕緣保護層27未被曝光部份之表面，進而於該絕緣保護層27表面形成一係為凹陷區272之顯露部，該凹陷區272未貫穿該絕緣保護層27，並露出各該導電柱26之頂面26a及其周圍側表面26b，之後該絕緣保護層27之凹陷區272下未被曝光部份再進行曝光，使該凹陷區272完全硬化成形，得藉由該凹陷區272以避免封裝用之底部填充材料(Underfill)產生溢流，而得限制底部填充材料之流動。
另請參閱第3B’圖，或將該絕緣保護層27未被曝光部份(未硬化)全部移除，以成為一係為開槽273之顯露部，以露出該基板本體20之介電層21部份表面，並完全露出該導電柱26之頂面26a及側表面26b；由於該導電柱26周圍無絕緣保護層27，而得避免封裝用之底部填充材料(Underfill)產生溢流以限制底部填充材料之流動，並可降低封裝高度，以及降低結合應力。
本發明復提出一種半導體封裝基板，其係包括：基板本體20，至少一表面具有線路24及複數電性連接墊241；複數導電柱26，係完全包覆形成於該電性連接墊241之頂面241a及側表面241b；以及絕緣保護層27，係形成於該基板本體20表面，且於該絕緣保護層27表面形成有一係為凹陷區272之顯露部，其中，該凹陷區272未貫穿該絕緣保護層27，並露出各該導電柱26之頂面26a及其側表面26b。
該半導體封裝基板之絕緣保護層27表面，亦可形成一貫穿該絕緣保護層27之開槽273，並露出該基板本體部份表面，以完全露出各該導電柱26之頂面26a及側表面26b。
本發明之半導體封裝基板及其製法，該導電柱之頂端無習知之側緣，故受溫度變化時應力較小，且該導電柱完全包覆在該電性連接墊之頂面及側表面，得有較佳之結合強度以避免破壞，且該電性連接墊之寬度與一般線路層之線寬相近，該導電柱之尺寸亦小於習知具側緣之導電柱；之後復於該基板本體表面形成該絕緣保護層，且該絕緣保護層表面形成一係為凹部、開孔、凹陷區或開槽之顯露部以露出該等導電柱之頂面及其周圍側表面，俾於形成該導電柱後再形成該絕緣保護層，可避免習知製程中先形成絕緣保護層再電鍍形成導電柱，因阻層與絕緣保護層之間開孔對位問題，導致該導電柱頂端於絕緣保護層表面形成側緣，使得該導電柱之間的間距無法縮小；並可藉由該顯露部限制該底部填充材料之流動位置以避免產生溢膠的情況；又得藉由該顯露部以降低半導體封裝件之整體厚度。
上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與變化。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
11、20．．．基板本體
111、241．．．電性連接墊
12．．．絕緣保護層
120．．．絕緣保護層開孔
13、22．．．導電層
14．．．阻層
140．．．阻層開孔
15、26．．．導電柱
151．．．側緣
21．．．介電層
23．．．第一阻層
230．．．第一阻層開口
24．．．線路
241a、26a．．．頂面
241b、26b．．．側表面
25．．．第二阻層
250．．．第二阻層開口
27．．．絕緣保護層
270．．．凹部
271．．．開孔
272．．．凹陷區
273．．．開槽
28．．．光罩
281、281’．．．不透光區域
第1A至1F圖係為習知嵌埋半導體晶片之製法流程圖；第2A至2J圖係為本發明之嵌埋半導體晶片之基板之製法流程圖；第2J’圖係為第2J圖之另一實施方式剖視圖；第3A及3B圖係為本發明之嵌埋半導體晶片之基板之製法流程圖；以及第3B’圖係為第3B圖之另一實施方式剖視圖。
20．．．基板本體
21．．．介電層
24．．．線路
241．．．電性連接墊
26．．．導電柱
26a．．．頂面
26b．．．側表面
27．．．絕緣保護層
270．．．顯露部

Claims (22)

  1. 一種半導體封裝基板，係用以覆晶(Flip Chip)方式結合晶片，包括：基板本體，至少一表面具有複數電性連接墊；複數銅導電柱，係分別完全包覆各該電性連接墊；以及絕緣保護層，係形成於該基板本體表面，且具有顯露部以露出該銅導電柱。
  2. 如申請專利範圍第1項之半導體封裝基板，其中，該基板本體具有電性連接墊之表面復包括有複數線路。
  3. 如申請專利範圍第2項之半導體封裝基板，其中，該基板本體表面復包括有介電層，於該介電層表面具有該電性連接墊及線路。
  4. 如申請專利範圍第3項之半導體封裝基板，復包括該基板本體之介電層與電性連接墊之間具有一導電層，以及介電層與線路之間具有一導電層。
  5. 如申請專利範圍第4項之半導體封裝基板，其中，該導電層之材料係選自銅、錫、鎳、鉻、鈦、及銅-鉻合金所組群組之其中一者。
  6. 如申請專利範圍第4項之半導體封裝基板，其中，該導電層係為導電高分子材料。
  7. 如申請專利範圍第1項之半導體封裝基板，其中，該顯露部係為複數未貫穿該絕緣保護層之凹部，以對應露出各該銅導電柱之頂面及其周圍側表面。
  8. 如申請專利範圍第1項之半導體封裝基板，其中，該顯露部係為複數貫穿該絕緣保護層之開孔，並露出該基板本體部份表面，以對應完全露出各該銅導電柱之頂面及側表面。
  9. 如申請專利範圍第1項之半導體封裝基板，其中，該顯露部係為一未貫穿該絕緣保護層之凹陷區，以露出各該銅導電柱之頂面及其周圍側表面。
  10. 如申請專利範圍第1項之半導體封裝基板，其中，該顯露部係為一貫穿該絕緣保護層之開槽，並露出該基板本體部份表面，以完全露出各該銅導電柱之頂面及側表面。
  11. 一種半導體封裝基板之製法，係包括：提供至少一表面具有複數電性連接墊之基板本體；於各該電性連接墊表面上形成有一導電柱，使該導電柱完全包覆該電性連接墊之頂面及側表面；以及於各該基板本體表面形成一絕緣保護層，且該絕緣保護層表面形成顯露部，藉該顯露部以露出各該導電柱。
  12. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該基板本體具有電性連接墊之表面復包括有複數線路。
  13. 如申請專利範圍第12項之半導體封裝基板之製法，其中，該電性連接墊及線路之製程係包括：提供一表面具有介電層之基板本體； 於該介電層表面形成一導電層；於該導電層上形成一第一阻層，且於該第一阻層中形成複數開口以露出部份之導電層；以及於各該開口中電鍍形成該電性連接墊及線路。
  14. 如申請專利範圍第13項之半導體封裝基板之製法，其中，該導電層之材料係選自銅、錫、鎳、鉻、鈦、及銅-鉻合金所組群組之其中一者。
  15. 如申請專利範圍第13項之半導體封裝基板之製法，其中，該導電層係為導電高分子材料。
  16. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該導電柱之製程係包括：移除該第一阻層；於該導電層上形成有一第二阻層，且於該第二阻層中對應該電性連接墊位置形成有開孔，以完全露出該電性連接墊之頂面及側表面；以及於各該開孔中之電性連接墊表面形成該導電柱。
  17. 如申請專利範圍第16項之半導體封裝基板之製法，復包括移除該第二阻層及其所覆蓋之導電層。
  18. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該導電柱係選自鉛、錫、銀、銅、金、鉍、銻、鋅、鎳、鋯、鎂、銦、碲、及鎵所組群組之其中一者。
  19. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該顯露部係為複數未貫穿該絕緣保護層之凹部，俾以對應露出各該導電柱之頂面及其周圍側表面。
  20. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該顯露部係為複數貫穿該絕緣保護層之開孔，並露出該基板部份表面，以對應完全露出各該導電柱之頂面及側表面。
  21. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該顯露部係為一未貫穿該絕緣保護層之凹陷區，以露出各該導電柱之頂面及其周圍側表面。
  22. 如申請專利範圍第11項之半導體封裝基板之製法，其中，該顯露部係為一貫穿該絕緣保護層之開槽，並露出該基板本體部份表面，以完全露出各該導電柱之頂面及側表面。
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