TWI382474B - 完全去耦化的高電壓和低電壓電晶體的製造方法 - Google Patents

完全去耦化的高電壓和低電壓電晶體的製造方法 Download PDF

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TWI382474B
TWI382474B TW097111129A TW97111129A TWI382474B TW I382474 B TWI382474 B TW I382474B TW 097111129 A TW097111129 A TW 097111129A TW 97111129 A TW97111129 A TW 97111129A TW I382474 B TWI382474 B TW I382474B
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transistor
high voltage
low voltage
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low
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TW200839893A (en
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Hu Yongzhong
Tai Sung-Shan
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Alpha & Omega Semiconductor
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Description

完全去耦化的高電壓和低電壓電晶體的製造方法
本發明涉及一種裝置結構及其製造方法，特別涉及一種通過特殊的隔離或絕緣結構來，來增強改進了的完全去耦化的高電壓和低電壓電晶體的製造方法。
高電壓和低電壓半導體裝置的製造方法和結構特徵是非常不同的。尤其是，高電壓裝置如橫向擴散金屬氧化物半導體(LDMOS)，高電壓氮摻雜金屬氧化物半導體(HV NMOS)，高電壓磷摻雜金屬氧化物半導體(HV PMOS)電晶體，高電壓PNP型三極管和高壓NPN型三極管是由具有較大尺寸的裝置零件在一個晶圓和晶片(die)上所構成的。這些裝置的製造方法通常需要非臨界塗層(non-critical mask layers)，如掩蓋層(buried layer)、高電壓井(HVwells)、主體區域和第一多晶矽柵極(1P gates)。相反，低電壓裝置如低電壓互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS)電晶體，是採用高密度製造的。因此，在一個晶片中這些裝置的封裝密度是最受關注的。為了實現上述設計，低電壓電晶體需要使用臨界防護層，如第二多晶矽柵極、接觸器、金屬和通過塗層。高電壓和低電壓電路之間尺寸和幾何學精度需求的差異能達到一個數量級(one order of magnitude)。這些結構特徵的差異包括了空間和精度控制的差異，以及製造方法的差異，該結構特徵的差異顯著地增加了在同一晶圓上嘗試整合低電壓 和高電壓裝置的難度。而且，高電壓裝置的方法通常需要高溫和長的熱迴圈週期。這樣的高溫長時間熱處理的需要將會破壞位於同一晶圓上的低電壓裝置和其製造過程。
同時，受晶片系統(SOC: System on Chip)的趨勢的驅使，在同一晶圓上整合低電壓和高電壓裝置的需要永遠在增加。所述的整合提供了小型化，低能量消耗和高水準的整合功能的益處。
根據以上所述的整合裝置結構和製造方法，對於製造高電壓和低電壓整合裝置而言，由於對低電壓裝置的迫切需求，必須採用低電壓半導體製造過程。高電壓裝置結構和製造方法原本採用較低精度的校正和控制，由於這個原因，現同樣需要採用高精度的校正和控制，這就導致了生產成本的增加。高溫和長時間熱迴圈同樣阻礙了將許多低電壓裝置整合進高電壓裝置中。
因此，在電路設計和裝置製造領域，提供一個新的改進的構造和製造方法以解決上述困難的需求依然存在。特別地，仍然需要新的改進的結構，以使得，高電壓裝置的製造方法不受制於低電壓裝置的需求，非必須的複雜處理和通常由在同一個晶圓上整合高電壓和低電壓電晶體所導致的增加的成本可以被避免。
因此，本發明的一個目的在於提供一種新的改進的高電壓和低電壓退耦和絕緣結構，該結構採用退耦製造方法，以使得傳統高電壓和低電壓整合製造方法所遇到的上 述困難和局限能被克服。
進一步而言，本發明的一個目的在於提供一種新的採用退耦層的高電壓和低電壓退耦結構，從而高電壓和低電壓裝置的製造被完全地去耦化，並可在兩個單獨的平臺上實現。通過採用微米技術或微米以上技術的非臨界處理程式來製造高電壓裝置。通過採用亞微米技術或亞微米以下技術的臨界處理步驟來製造低電壓電路。
本發明的另一個目的在於提供一種採用退耦層的新的高電壓和低電壓退耦結構，從而高電壓和低電壓裝置的製造可以完全被完全地去耦化，並可在兩個單獨的平臺上實現，即兩個半導體鑄件。該高電壓裝置能以低成本，在可進行微米技術或微米以上技術的非臨界處理程式的低端製造工廠中生產製造。該低電壓電路在另外的一個可進行亞微米技術或亞微米以下技術的臨界處理步驟的高端製造工廠中製造。
本發明的一個實施例簡要的公開了一個包括至少一個高電壓電晶體和一個低電壓電晶體的電子裝置，所述的至少一個高電壓電晶體和一個低電壓電晶體位於同一個晶圓上，所述的低電壓電晶體的封裝密度約為高電壓電晶體的封裝密度的十倍。在一個具體實施例中，高電壓電晶體包括一個橫向擴散金屬氧化物半導體(LDMOS)電晶體，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高 電壓氮摻雜金屬氧化物半導體(NMOS)電晶體，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高電壓PMOS電晶體，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高電壓PNP電晶體，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高電壓NPN電晶體，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高電壓雙極連接電晶體(BJT)，低電壓電晶體包括一個互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS)電晶體，上述電晶體被支持在同一個晶圓上。在另一個實施例中，高電壓電晶體包括一個高電壓井、一個主體區域和一個多晶矽柵極，低電壓電晶體包括一個低電壓井。在另一個實施例中，高電壓電晶體包括一個高電壓井、一個主體區域和一個多晶矽柵極，所述的多晶矽柵極進一步包括一個高電壓低電壓退耦層，作為蝕刻掉的側牆環繞多晶矽柵極。在另一個實施例中，低電壓電晶體進一步包括一個低電壓柵極、低電壓源極和主體區域。在另 一個實施例中，低電壓電晶體進一步包括一個低電壓柵極、低電壓源極和漏極區域，一個具有多組金屬層(ML)和多組內置電介質層(ILD)的標準互補金屬氧化物半導體(互補金屬氧化物半導體(CMOS))BEOL，所述的多組內置電介質層(ILD)具有一個穿過內置電介質層(ILD)的連接溝槽，以向源極和漏極區域提供電連接。在另一個實施例中，高電壓電晶體具有一個寬度為0.5-10微米的線寬，低電壓電晶體具有一個寬度小於0.5微米的線寬，所述的高電壓電晶體和低電壓電晶體被支持在同一個晶圓上。在另一個實施例中，在同一個晶圓上，提供高電壓電晶體，以保證可在5伏至數百伏甚至更高的電壓條件下操作，提供低電壓電晶體，以保證可在低於5伏的條件下操作。
本發明進一步公開了一種電子裝置的製造方法，該電子裝置具有被支持在同一個晶圓上整合的高電壓和低電壓電晶體。該方法包括以下步驟：形成高電壓低電壓退耦層，以覆蓋部分製造好的高電壓電晶體；從部分製造好的低電壓電晶體上蝕刻掉高電壓低電壓退耦層，以進一步進行之後的低電壓製造程式。在一個實施例中，形成高電壓低電壓退耦層的步驟包括，形成一個約為30-150埃的高溫氧化物(HTO)氧化物層和一個低壓化學汽相沉積(LPCVD)氮化物層，以覆蓋部分製造好的高電壓電晶體的步驟。
在閱讀了以下具體實施例的細節性描述後，本領域的普通技術人員將會理解本發明的目的和優勢，這些實施例 將會根據附圖加以闡述。
第1A-1圖和第1A-2圖是兩個橫截面視圖，描述了橫向擴散金屬氧化物半導體(LDMOS)電晶體和雙極連接電晶體(BJT)裝置的製造過程，通過第1A圖的橫截面視圖所示的製造方法，上述裝置作為高電壓裝置與低電壓電晶體整合。如第1A-1圖和第1A-2圖所示，高電壓橫向擴散金屬氧化物半導體(LDMOS)和雙極連接電晶體(BJT)裝置的製造過程開始於一個常規的初始基底105，在本發明中，為一個P+基底。採用一個掩蓋層塗層(buried layer mask)(圖中未示出)來引入掩蓋層115和115’，然後進行擴散過程形成掩蓋層從而達到絕緣目的。然後生長一個外延層110。使用一個高壓井塗層(圖中未示出)，向橫向擴散金屬氧化物半導體(LDMOS)和雙極連接電晶體(BJT)裝置中引入高電壓井120和120’。使用一個活性塗層(圖中未示出)，在外延層110的頂表面形成一組矽的局部氧化(LOCOS)區域125。形成一個厚的柵極氧化物層128，然後進行柵極層沉積，採用一個柵極塗層(圖中未示出)來進行柵極蝕刻程式，在裝置的頂表面形成柵極片段130。幾個處理步驟同樣被用於形成所述的高電壓裝置組成。第1A-1圖表示出一個附加的高電壓處理程式，用於形成橫向擴散金屬氧化物半導體(LDMOS)主體區域135、源極和漏極區域140、主體連接引入區域145。第1A-2圖表示出一個附加的高電壓處理程式，用於形成雙極連接電晶體 (BJT)裝置的雙極基底區域150、基底連接引入區域151、發射器區域153和控制區域155。生長外延層110、形成過程矽的局部氧化(LOCOS)125、高電壓柵極氧化物128和柵極層130的過程同樣也被用於低電壓電晶體區域，如第1A圖所示。
根據第1B-1圖、第1B-2圖和第1B圖所示，在完成高電壓裝置處理程式後，形成一個約30-150埃的高溫氧化物(HTO)氧化物層和一個低壓化學汽相沉積(LPCVD)氮化物層160，作為一個退耦裝置以使得形成在同一晶圓上的高電壓和低電壓裝置去耦化。晶圓現在可以用於另一個加工過程以繼續高電壓裝置的製造步驟。如第1C圖所示，使用一個高電壓塗層(圖中未示出)從低電壓裝置區域的頂部覆蓋在退耦層160和柵極片段130上。退耦層160留在如第1B-2圖和第1B-2圖所示的高電壓裝置區域，以保護高電壓裝置避免低電壓處理程式的影響。然後一個低電壓井塗層(圖中未示出)被用於引入低電壓井165。在第1D圖中，生成一個低電壓柵極氧化物層170。然後，進行一個第二多晶矽沉積，再執行三氯氧磷(POCL3)摻雜和鎢化矽(WSix)沉積，一個P2-柵極塗層(圖中未示出)被用於蝕刻低電壓柵極175，並形成圖案。
在形成低電壓裝置柵極的製造程式後，使用一個低電壓塗層(圖中未示出)來蝕刻並移除高電壓裝置上的退耦層160，如第1E-1圖和第1E-2圖，留下一個側牆，環繞高電壓柵極的多晶矽柵極130。然後，使用輕度摻雜柵極 (LDD)塗層，引入輕度摻雜柵極(LDD)區域180。在第1F-1圖、第1F-2圖和第1F圖中，進行間隔沉積，然後進行蝕刻處理，形成環繞所述柵極175的側牆絕緣層178。使用源極和漏極塗層(圖中未示出)，而從在輕度摻雜柵極(LDD)區域180中引入源極漏極區域185，然後進行源極漏極鈦矽化合物處理，以改善傳導率。然後，對後道線(BEOL)的標準互補金屬氧化物半導體(CMOS)後端進行二到三次金屬層(ML)處理，在內置電介質層(ILD0)190上形成連接金屬，所述的內置電介質層(ILD0)190上具有貫穿的溝槽連接195以提供與源極和漏極區域的電連接。
儘管本發明通過之前的具體實施例進行描述，應該理解上述公開並不解釋為限制作用。在閱讀了上述公開內容後，本領域的普通技術人員顯然可以推出多種變更和修改。相應地，附加權利要求應被解釋為涵蓋所有可能的變更和修改，上述變更和修改沒有超出本發明的精神和範圍。
160‧‧‧退耦層
140‧‧‧源極和漏極區域
130‧‧‧第一多晶矽柵極
135‧‧‧主體區域
145、151‧‧‧引入區域
125‧‧‧矽的局部氧化(LOCOS)區域
120、120’‧‧‧高電壓井
110‧‧‧生長外延層
115、115’‧‧‧掩蓋層
105‧‧‧P+基底
128‧‧‧高電壓柵極氧化物
150‧‧‧雙極基底區域
153‧‧‧發射器區域
155‧‧‧控制區域
165‧‧‧低電壓井
170‧‧‧低電壓柵極氧化物
175‧‧‧鎢化矽摻雜第二多晶矽
178‧‧‧側牆絕緣層
180‧‧‧輕度摻雜柵極(LDD)區域
185‧‧‧源極漏極區域
190‧‧‧內置電介質層(ILD0)
第1A-1圖，第1A-2圖和第1A圖至第1F-1圖，第1F-2圖和第1F圖是一組描述完全去耦化的高電壓(completely decoupled high voltage)橫向擴散金屬氧化物半導體(LDMOS)和雙極連接電晶體(BJT)裝置的製造過程的連續橫截面視圖，上述完全去耦化的高電壓(completely decoupled high voltage)橫向擴散金屬氧化物半導體(LDMOS)和雙極連接電晶體(BJT)裝置與低電壓電晶體被整合在同一個晶圓上。
160‧‧‧退耦層
140‧‧‧源極和漏極區域
130‧‧‧第一多晶矽柵極
135‧‧‧主體區域
145‧‧‧引入區域
125‧‧‧矽的局部氧化(LOCOS)區域
120‧‧‧高電壓井
110、N‧‧‧外延層生長外延層
115‧‧‧掩蓋層
105‧‧‧P+基底

Claims (16)

  1. 一種電子裝置，其特徵在於，包括至少一個高電壓電晶體和一個低電壓電晶體，所述的高電壓電晶體和低電壓電晶體被支持在同一個晶圓上，所述的低電壓電晶體的封裝密度大約是所述的高電壓電晶體的封裝密度的10倍；其中，所述的高電壓電晶體在所述低電壓電晶體的製造過程中由一高電壓低電壓退耦層保護，且形成該高電壓低電壓退耦層的步驟包括：形成一個高電壓低電壓退耦層，覆蓋一部分製造好的高電壓電晶體和一部分製造好的低電壓電晶體上；從一部分製造好的低電壓電晶體上蝕刻掉所述的高電壓低電壓退耦層，以進一步在其上進行低電壓製造程式；所述高電壓低電壓退耦層留在高電壓電晶體區域保護高電壓電晶體避免低電壓處理程式的影響；在形成低電壓裝置柵極的製造程式後，使用低電壓塗層來蝕刻並移除高電壓電晶體上的高電壓低電壓退耦層。
  2. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個橫向擴散金屬氧化物半導體(LDMOS)電晶體，所述的低電壓電晶體包含一個互補金屬氧化物半導體(CMOS)電晶體，所述的LDMOS電晶體和CMOS電晶體被支持在同一個晶圓上。
  3. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓氮摻雜金屬氧化物半導體(NMOS)電晶體，所述的低電壓電晶體包含一 個互補金屬氧化物半導體(CMOS)電晶體，所述的NMOS電晶體和CMOS電晶體被支持在同一個晶圓上。
  4. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓磷摻雜金屬氧化物半導體(PMOS)電晶體，所述的低電壓電晶體包含一個互補金屬氧化物半導體(CMOS)電晶體，所述的PMOS電晶體和CMOS電晶體被支持在同一個晶圓上。
  5. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓PNP型三極管電晶體，所述的低電壓電晶體包含一個互補金屬氧化物半導體(CMOS)電晶體，所述的PNP型三極管電晶體和CMOS電晶體被支持在同一個晶圓上。
  6. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓NPN型三極管電晶體，所述的低電壓電晶體包含一個互補金屬氧化物半導體(CMOS)電晶體，所述的NPN型三極管電晶體和CMOS電晶體被支持在同一個晶圓上。
  7. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓雙極連接電晶體(BJT)電晶體，所述的低電壓電晶體包含一個互補金屬氧化物半導體(CMOS)電晶體，所述的BJT電晶體和CMOS電晶體被支持在同一個晶圓上。
  8. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包含一個高電壓井、一個主體區 域和一個多晶矽柵極，所述的低電壓電晶體包含一個低電壓井。
  9. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體包括一個高電壓井、一個主體區域和一個多晶矽柵極，所述的多晶矽柵極進一步包括一個高電壓低電壓退耦層，作為蝕刻掉的側牆環繞所述的多晶矽柵極。
  10. 如申請專利範圍第8項所述的電子裝置，其特徵在於，所述的低電壓電晶體進一步包括一個低電壓柵極、低電壓源極和主體區域.
  11. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體具有一個0.5-10微米的線寬，所述的低電壓電晶體具有一個小於0.5微米的線寬，所述的高電壓電晶體和低電壓電晶體被支持在同一個晶圓上。
  12. 如申請專利範圍第1項所述的電子裝置，其特徵在於，所述的高電壓電晶體在高於5伏的電壓下使用，所述的低電壓電晶體在低於5伏的電壓下使用，所述的高電壓電晶體和低電壓電晶體被支持在同一個晶圓上。
  13. 一種位於製造過程中間步驟的半導體晶圓，其特徵在於，包含如下部分：一組至少部分製造好的高電壓電晶體；一個製造一組低電壓電晶體的區域，所述的低電壓電晶體的封裝密度大約是所述的高電壓電晶體的封裝密度 的10倍；一個高電壓低電壓退耦層，形成高電壓低電壓退耦層的步驟包括：形成一個高電壓低電壓退耦層，以覆蓋一部分製造好的高電壓電晶體和一部分製造好的低電壓電晶體上；從一部分製造好的低電壓電晶體上蝕刻掉所述的高電壓低電壓退耦層，以進一步在其上進行低電壓製造程式；所述高電壓低電壓退耦層留在高電壓電晶體區域保護高電壓電晶體避免低電壓處理程式的影響；以及在形成低電壓裝置柵極的製造程式後，使用低電壓塗層來蝕刻並移除高電壓電晶體上的高電壓低電壓退耦層。
  14. 如申請專利範圍第13項所述的一種位於製造過程中間步驟的半導體晶圓，其特徵在於，所述的高電壓低電壓退耦層包含一個約30-150埃的高溫氧化物(HTO)氧化物層和一個低壓化學汽相沉積(LPCVD)氮化物層。
  15. 一種在半導體晶圓上製造電子裝置的方法，其特徵在於包含以下步驟：形成一個高電壓低電壓退耦層，以覆蓋一部分製造好的高電壓電晶體和一部分製造好的低電壓電晶體上；從一部分製造好的低電壓電晶體上蝕刻掉所述的高電壓低電壓退耦層，以進一步在其上進行低電壓製造程式，所述高電壓低電壓退耦層留在高電壓電晶體區域保護高電壓電晶體避免低電壓處理程式的影響；在形成低電壓裝置柵極的製造程式後，使用低電壓塗層來蝕刻並移除高電壓電晶體上的高電壓低電壓退耦層。
  16. 如申請專利範圍第15項所述的一種在半導體晶圓上製造電子裝置的方法，其特徵在於，所述的形成高電壓低電壓退耦層的步驟包含，形成一個約30-150埃的高溫氧化物(HTO)氧化物層和一個低壓化學汽相沉積(LPCVD)氮化物層，以覆蓋所述的部分製造好的高電壓電晶體的步驟。
TW097111129A 2007-03-27 2008-03-27 完全去耦化的高電壓和低電壓電晶體的製造方法 TWI382474B (zh)

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