1374693 30194twf.doc/n 六、發明說明： » 【發明所屬之技術領域】 本發明是有關於一種線路板的製造方法，且特別是有 關於一種提高基板於製程中的強度的線路板製造方法。 【先前技術】 近年來，隨著電子技術的日新月異，以及高科技電子 φ 產業的相繼問世，使得更人性化、功能更佳的電子產品不 斷地推陳出新，並朝向輕、薄、短、小的趨勢邁進。在此 趨勢之下，電午產品的線路板亦朝向薄型化的方向發展。 圖1繪示習知之線路板的製程剖面圖。請參照圖i， _ 線路基板110配置於滾輪120上，且滾輪120帶動線路基 板110沿著方向V前進，並於前進的途中藉由多個喷嘴130 對線路基板110喷灑藥液或其他溶液，以進行蝕刻、除膠 渣或顯影等步驟。然而’由於線路基板110的厚度過薄以 致於強度不佳，且滾輪間距較大，故當線路基板110受到 藥液喷灑時易彎折而落於滾輪120之間造成卡板。 【發明内容】 本發明提供一種線路板的製造方法，可提高基板於製 程中的強度。 本發明提出一種線路板的製造方法如下所述。首先， &供一基板，基板包括一絕緣層與配置於絕緣層上的一第 一導電層，基板具有一中心區域與位於中心區域外圍之一 30194twf.doc/n 周邊區域’ 第—導電層區分為位於中心區域的 分以及位於周邊區域的—周邊部分。接著，. :周成一硬化層，硬化層的材質包括防悍： 枓塞孔材枓或熱固型材料。然後，圖案化第一 中心部分，以形成一線路層。 g 法。在本㈣之—實關巾，軸硬化料方法包括網印 之—實施例中’硬化層包括多個條狀結構。 塊狀社構X日ί —實施例中，硬化層包括多個彼此獨立的 間隙。。各塊狀結構與其周邊的塊狀結構之間存在- 側與3ΓΓ—實施射，中心區域具有相對的—第一 的周邊部y 層形成於與第—㈣及第二側相鄰 第-實施Γ :中心區域具有彼此相對的一 且硬化層形成於:=側接J::則與第二側的-第三側’ 部分上。 、/、 弟—側以及第三側相鄰的周邊 第之；'實關中，中心輯具錢此相對的- 且第三側料1以及彼此相對的—第三侧與—第四側， 與第-側:、ίΓ彳自:連鮮―側與第二側，硬化層形成於 在太it 一側、第二側以及第四側相鄰的周邊部分上。 米。I明之一實施例中，基板的厚度小於等於90微 1374693 30194twf.doc/n 在本發明之一實施例中，絕緣層的厚度小於等於7〇 微米。 在本發明之一實施例中，線路板的製造方法更包括於 形成線路層之後，形成覆蓋部分線路層的一防焊層。 ^在本發明之一實施例中，線路板的製造方法更包括在 开乂成防:tp層之後，移除基板之位於周邊區域的部分以及硬 化層。1374693 30194twf.doc/n VI. Description of the Invention: » Technical Field of the Invention The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of manufacturing a wiring board which improves the strength of a substrate in a process. [Prior Art] In recent years, with the rapid development of electronic technology and the advent of high-tech electronics φ industry, more humanized and functional electronic products are constantly being introduced, and the trend toward light, thin, short and small Step forward. Under this trend, the circuit boards of the electronic lunch products are also developing in a thinner direction. FIG. 1 is a cross-sectional view showing a process of a conventional circuit board. Referring to FIG. 1 , the circuit substrate 110 is disposed on the roller 120 , and the roller 120 drives the circuit substrate 110 to advance along the direction V, and sprays the liquid substrate or other solution on the circuit substrate 110 by using the plurality of nozzles 130 on the way forward. For etching, desmear or development steps. However, since the thickness of the circuit substrate 110 is too thin to be inferior in strength and the pitch of the roller is large, when the circuit substrate 110 is sprayed with the chemical liquid, it is easily bent and falls between the rollers 120 to cause a card. SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a wiring board, which can improve the strength of a substrate in a process. The present invention proposes a method of manufacturing a wiring board as follows. First, a substrate is provided, and the substrate comprises an insulating layer and a first conductive layer disposed on the insulating layer, the substrate has a central region and a peripheral region located at a periphery of the central region 30194 twf.doc/n It is divided into points located in the center area and peripheral parts located in the surrounding area. Next, : Zhou Chengyi hardened layer, the hardened layer material includes anti-mite: 枓 plug hole material or thermosetting material. Then, the first central portion is patterned to form a wiring layer. g method. In the present invention, the shaft hardening method includes screen printing. In the embodiment, the hardened layer comprises a plurality of strip structures. Block Structure X - In the embodiment, the hardened layer includes a plurality of gaps independent of each other. . Between each block structure and its surrounding block structure, there are - side and 3 ΓΓ - the radiation is emitted, and the central region has opposite - the first peripheral portion y layer is formed adjacent to the first (fourth) and the second side - the implementation The central region has one opposite to each other and the hardened layer is formed on: = side J:: then on the second side - the third side' portion. , /, the younger side and the third side adjacent to the periphery; 'in the real customs, the center is equipped with money relative to this - and the third side material 1 and the opposite side - the third side and the fourth side, with The first side: the 硬化 Γ彳 from: the fresh side and the second side, the hardened layer is formed on the peripheral portion adjacent to the side of the tai, the second side, and the fourth side. Meter. In one embodiment, the thickness of the substrate is less than or equal to 90 micro 1374693 30194 twf.doc/n. In one embodiment of the invention, the thickness of the insulating layer is less than or equal to 7 μm. In an embodiment of the invention, the method of manufacturing the wiring board further comprises forming a solder resist layer covering a portion of the wiring layer after forming the wiring layer. In one embodiment of the present invention, the method of fabricating the wiring board further includes removing the portion of the substrate located in the peripheral region and the hardened layer after opening the anti-tp layer.
乂在本發明之一實施例中，線路板的製造方法更包括在 =成硬化層之前，於基板的周邊區域形成貫穿基板的多個 疋位孔，且在形成硬化層時，硬化層暴露出定位孔。 在本發明之—實關巾，麵成魏狀後，形成線 路層。 在本發明之一實施例中，當硬化層的材質為塞孔材料 或熱固型材_，線路板的製造方法更包括下述步驟。在 j硬化層之前，於基板的中心區域形成貫穿基板的至少In an embodiment of the present invention, the method of manufacturing the circuit board further includes forming a plurality of clamping holes penetrating the substrate in a peripheral region of the substrate before the hardening layer is formed, and exposing the hardened layer when the hardened layer is formed. Positioning holes. In the solid cover towel of the present invention, the surface layer is formed into a Wei shape. In an embodiment of the invention, when the hardened layer is made of a plug material or a thermoset profile, the method of manufacturing the circuit board further includes the following steps. Forming at least a through substrate in the central region of the substrate before the hardened layer
^孔。在形成硬化層之後，於[導電層以及貫孔的内 成-第二導電層。在圖案化第—導電層的中心部分 、5打®案化第二導電層之位於中心區域的部分。 在本發明之一實施例中，線路板的製造方法更包括在 =成硬^之後並在形成第二導電層之前，對貫孔的内壁 進仃一除膠渣製程。 ❹之一貫施例中，線路板的製造方法更包括在 形成貝孔之月”對第一導電層進行—薄化製程。 在本發明之一實施例中，硬化層包括至少一網格狀結 1374693 30194twf.doc/n .- 構。 . 基於上述，本發明是藉由在基板的周邊區域中开;成石 化層來提升強度。因此，本發明可避免習知的基板^严石 較薄以致於強度較差所導致的卡板問題，進而可提升^度 板的製程良率。 、、路 為讓本發明之上述特徵和優點能更明顯易懂，下文 舉實施例’並配合所附圖式作詳細說明如下。 、 ^【實施方式】 圖2A〜圖2E繪示本發明一實施例之線路板的製程剖 面圖。圖3A與圖3B分別緣示圖2A與圖2B的上視圖， - 且圖2A與圖2B分別繪示圖3A與圖3B之基板沿14，線段 的剖面圖。圖4繪示圖3A之基板沿π_ΙΓ線段的剖面圖。 請同時參照圖2A、圖3A與圖4 ’首先，提供一基板 200’基板200包括一絕緣層210與分別配置於絕緣層21〇 之相對二表面212、214的二導電層220。本實施例之基板 書 200例如為一核心基板。在本實施例中，基板2〇〇的厚度 T1例如小於專於90微米，其中絕緣層210的厚度丁2例如 小於等於70微米。 基板200具有一中心區域23〇與位於中心區域23〇外 圍之一周邊區域240，且導電層22〇區分為位於中心區域 230的一中心部分222以及位於周邊區域24〇的一周邊部 分224。接著，例如以機械鑽孔的方式於基板2〇〇的周邊 區域240形成貫穿基板2〇〇的多個定位孔η。 1374693 30194twf.doc/n 之後，請同時參照圖2B與圖3B，例如以網印法形成 一硬化層300於導電層220的周邊部分224上，且硬化層 300暴露出定位孔η，硬化層3〇〇的材質包括防焊材料或 基孔材料。值得注意的是’在本實施例中’硬化層3〇〇可 形成於基板200的—表面252上或是形成於基板200的相 對二表面252、254上。 詳細而言’在本實施例中，中心區域230具有彼此相 對的一第一側232芩一第二側234以及彼此相對的一第三 側236與一第四側238，且第三侧236與第四側238皆連 接第一侧232與第二側234。 圖3Β繪示的硬化層3〇〇是形成於與第一侧232、第二 側234、第三側236以及第四側238相鄰的周邊部分224 上，但本發明並不限於此。舉例來說，在其他實施例中， 硬化層300可僅形成在與第—側232以及第二側234相鄰 的周邊部分224上，或者是僅形成在與第一側232、第二 側234以及第三側236相鄰的周邊部分224上。 在本實施例中’硬化層300可具有多個條状結構310, 但本發明並不限於此。舉例來說，在其他實施例，中，硬化 層300包括多個彼此獨立的塊狀結構（未繪示），且各塊 狀結構與其周邊的塊狀結構之間存在一間隙。 由前述可知’本實施例是藉由在基板200的周邊區域 24匕中形成硬化層3GG來提升強度。因此，本實施例可避 ，習知的基板因厚度較薄以致於強度較差所導致的卡板問 題，進而可提升線路板的製程良率。而且，本實施例之線 30194twf.doc/n 路板的製造方法與習知的機台相容，故不需另外調整 的機台。 ° 然後，請參照圖2C，於導電層220上形成—罩幕層（ 繪示）。然後，對罩幕層進行一曝光顯影製程，以形成— 圖案化罩幕層400。之後，請參照圖2D，蝕刻導電^ 2如 之暴露於圖案化罩幕層400外的部分，以形成—線路声l。 然後，移除圖案化罩幕層400。 曰。 接著，請參照圖2E，在本實施例中，形成覆蓋部分線 路層L的一防焊層500。在本實施例中，於形成防焊層5卯 之後，可選擇性地移除基板200之位於周邊區域24〇的部 分以及硬化層300。換言之，以本發明之線路板的製造方 法所製得的線路板成品將不具有硬化廣300。 圖5A〜圖5F繪示本發明一實施例之線路板的製程剖 面圖。圖6A〜圖6D繪示圖5A〜圖5D的上視圖，且圖 5A〜圖5D繪示圖6A〜圖6D之基板沿ι_Γ線段的剖面圖。 圖7、圖8、圖9、圖10與圖U繪示圖6B之硬化層的五 種變化結構。 首先’請參照圖5A，提供一基板2〇〇，基板200與圖 2八之基板200的結構相同，故於此不多加描述。然後，請 同蚪參照圖5B與圖6A，在本實施例中，可對導電層22〇 進行一薄化製程，以減少導電層220的厚度。接著，於基 板200的中心區域230例如以機械鑽孔的方式形成貫穿基 板200的多個貫孔TH。於本實施例中，可在形成貫孔TH 的同時，於基板200的周邊區域240形成貫穿基板200的 1374693 30194twf.doc/n 多個定位孔H。 然後，請同時參照圖5C與圖6Β，於導電層22〇的周 邊部分224上形成-硬化層·，且硬化層暴露出定 位孔Η，硬化層30㈣材質為塞孔材料。在本實施例中， 硬化層300可以形成於基板2〇〇的—表面252上或者是 形成於基板200的二表面252、2Μ上。在本實施例中，硬 化層30G包括多個彼此獨立的塊狀結構32()，且各塊狀結^ Hole. After the hardened layer is formed, the [conducting layer and the through hole are formed into a second conductive layer. In the central portion of the patterned first conductive layer, the portion of the second conductive layer located in the central region is formed. In an embodiment of the invention, the method of fabricating the circuit board further includes performing a desmear process on the inner wall of the through hole after the formation of the second conductive layer. In a consistent embodiment of the invention, the method of manufacturing the wiring board further comprises: performing a thinning process on the first conductive layer in the month of forming the beacon. In an embodiment of the invention, the hardened layer comprises at least one grid-like junction. 1374693 30194twf.doc/n .- structure. Based on the above, the present invention enhances the strength by opening in the peripheral region of the substrate; forming a petrochemical layer. Therefore, the present invention can avoid the thinness of the conventional substrate. The problem of the card board caused by the poor strength can further improve the process yield of the board. The above features and advantages of the present invention can be more clearly understood, and the following embodiments are combined with the drawings. 2A to 2E are cross-sectional views showing a process of a circuit board according to an embodiment of the present invention. Figs. 3A and 3B are respectively a top view of Figs. 2A and 2B, and 2A and FIG. 2B are respectively a cross-sectional view of the substrate along the line 14 of FIG. 3A and FIG. 3B. FIG. 4 is a cross-sectional view of the substrate of FIG. 3A along the π_ΙΓ line segment. Please refer to FIG. 2A, FIG. 3A and FIG. First, a substrate 200 is provided. The substrate 200 includes an insulating layer 210. The two conductive layers 220 are disposed on the opposite surfaces 212 and 214 of the insulating layer 21, respectively. The substrate book 200 of the embodiment is, for example, a core substrate. In the embodiment, the thickness T1 of the substrate 2 is less than 90 micrometers, wherein the thickness of the insulating layer 210 is, for example, less than or equal to 70 micrometers. The substrate 200 has a central region 23 〇 and a peripheral region 240 located at a periphery of the central region 23 ,, and the conductive layer 22 is divided into the central region 230. A central portion 222 and a peripheral portion 224 located in the peripheral region 24A. Next, a plurality of positioning holes η penetrating the substrate 2A are formed in the peripheral region 240 of the substrate 2A by mechanical drilling, for example, 1374693 30194twf. After doc/n, please refer to FIG. 2B and FIG. 3B simultaneously, for example, a hardened layer 300 is formed on the peripheral portion 224 of the conductive layer 220 by screen printing, and the hardened layer 300 exposes the positioning hole η, and the hardened layer 3 is The material includes a solder resist material or a base material. It is noted that 'in the present embodiment, the hardened layer 3 can be formed on the surface 252 of the substrate 200 or formed on the opposite surfaces 252 of the substrate 200. 254. In detail, in the present embodiment, the central region 230 has a first side 232, a second side 234 opposite to each other, and a third side 236 and a fourth side 238 opposite to each other, and a third The side 236 and the fourth side 238 are connected to the first side 232 and the second side 234. The hardened layer 3 图 shown in FIG. 3A is formed on the first side 232, the second side 234, the third side 236, and the fourth The side 238 is adjacent to the peripheral portion 224, but the invention is not limited thereto. For example, in other embodiments, the hardened layer 300 may be formed only in the peripheral portion adjacent to the first side 232 and the second side 234. 224 is either formed only on the peripheral portion 224 adjacent the first side 232, the second side 234, and the third side 236. The hardened layer 300 may have a plurality of strip structures 310 in this embodiment, but the invention is not limited thereto. For example, in other embodiments, the hardened layer 300 includes a plurality of block structures (not shown) that are independent of each other, and a gap exists between each block structure and the surrounding block structure. As is apparent from the foregoing, the present embodiment enhances the strength by forming the hardened layer 3GG in the peripheral region 24 of the substrate 200. Therefore, the present embodiment can avoid the problem that the conventional substrate is thinned and the strength is poor, and the board yield problem can be improved. Moreover, the manufacturing method of the line 30194twf.doc/n board of the present embodiment is compatible with the conventional machine, so that no additional adjustment is required. Then, referring to FIG. 2C, a mask layer (shown) is formed on the conductive layer 220. Then, an exposure development process is performed on the mask layer to form a patterned mask layer 400. Thereafter, referring to FIG. 2D, the portion of the conductive layer 2 exposed to the outside of the patterned mask layer 400 is etched to form a line sound. The patterned mask layer 400 is then removed. Hey. Next, referring to Fig. 2E, in the present embodiment, a solder resist layer 500 covering a portion of the wiring layer L is formed. In the present embodiment, after the solder resist layer 5 is formed, the portion of the substrate 200 located in the peripheral region 24A and the hardened layer 300 can be selectively removed. In other words, the finished circuit board produced by the method of manufacturing the wiring board of the present invention will not have a hardening width 300. 5A to 5F are cross-sectional views showing the process of a circuit board according to an embodiment of the present invention. 6A to FIG. 6D are top views of FIGS. 5A to 5D, and FIGS. 5A to 5D are cross-sectional views of the substrate of FIGS. 6A to 6D taken along line ι_Γ. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. U illustrate five variations of the hardened layer of FIG. 6B. First, please refer to FIG. 5A, a substrate 2 is provided, and the substrate 200 has the same structure as the substrate 200 of FIG. 2, and thus will not be described here. Then, referring to FIG. 5B and FIG. 6A, in the embodiment, the thinning process can be performed on the conductive layer 22A to reduce the thickness of the conductive layer 220. Next, a plurality of through holes TH penetrating the substrate 200 are formed in the central region 230 of the substrate 200, for example, by mechanical drilling. In the present embodiment, a plurality of positioning holes H penetrating through the substrate 200 may be formed in the peripheral region 240 of the substrate 200 while forming the through holes TH. Then, referring to Fig. 5C and Fig. 6A, a hardened layer is formed on the peripheral portion 224 of the conductive layer 22, and the hardened layer exposes the positioning hole, and the hardened layer 30 (4) is made of a plug material. In the present embodiment, the hardened layer 300 may be formed on the surface 252 of the substrate 2 or on the two surfaces 252, 2 of the substrate 200. In the present embodiment, the hardened layer 30G includes a plurality of block structures 32() independent of each other, and each of the block junctions
構32〇與其周邊的塊狀結構32〇之間存在一間隙g。在^ 貝施例中’間隙G約為i釐米。在本實施例中，塊狀結構 320例如為矩形，且其長度A例如為10釐米，其寬度W 例如為4釐米。 一一在本只施，中，圖6B繪示的硬化層3㈨是形成於與 =側232、第二侧234以及第三侧236相鄰的周邊部分 一^。在其他實施例中’硬化層300亦可僅形成於與第 2 32以及第二側234相鄰的周邊部分上（請參，昭There is a gap g between the structure 32〇 and the surrounding block structure 32〇. In the case of ^, the gap G is about i cm. In the present embodiment, the block structure 320 is, for example, rectangular, and has a length A of, for example, 10 cm and a width W of, for example, 4 cm. In the present application, the hardened layer 3 (9) shown in Fig. 6B is formed on the peripheral portion adjacent to the = side 232, the second side 234, and the third side 236. In other embodiments, the hardened layer 300 may be formed only on the peripheral portion adjacent to the second and second sides 234 (see,
圖）’，者是形成於與第—側232、第二側234、第三側 ^及第1側238相鄰的周邊部分224上（請參照圖8 )。 # π “他A施例中，請參照圖9，硬化層300a的材質包 心^材料（例如白漆），且硬化層施包括至少二網 ^ =及:格狀結構910可如圖9所示是形成於與 ^ 弟一側234相鄰的周邊部分上。網格 ^ ίο亦可以是形成在與第一側232、第二側辦以 去ί 3 236相鄰的周邊部* 224上（請參照圖H))，或 者疋形成在與第—側议、第二側234、第三側236以及第 1374693 30194twf.doc/n 四側⑽相鄰的周邊部分224上（請參照圖u)。 接者，請同時參昭圖θ μ 斜勺,與圖6C’在本實施例中，可 TH貝所進仃—除料製程，以清除形成貫孔 化展3〇〇紐#Γ查。值得注意的是，由於本實施例之硬 ^層300的材質為塞孔材料，因此，硬化層· 膠渣製程的影響。 亡$ :同日守參知、圖5D與圖6D ’例如以電鍍的方式 形成-¥電層610於導電層22〇以及貫孔^的内壁§上。 f本實施财’由於硬化層包料倾此獨立的塊狀 、’、。構32:因此’導電層q。與硬化層細的接合面積較 大，而迫將提升導電層61〇與硬化層3〇〇的接合力。 然後，請參照圖5E ’例如以微影钱刻的方式圖案化導 電層220的令心部分222以及導電層61〇之位於中心區域 230的部分’以形成—線路層L，線路層l包括一圖案化 導電層220a與一圖案化導電層61〇a。在本實施例中，當 =微影蝕刻的方式圖案化導電層22〇的中心部分222以及 導電層610之位於中心區域23〇的部分時，間隙Q有利於 在基板200與光罩（未繪示）之間進行抽真空。 之後，請參照圖5F，在本實施例中，形成覆蓋部分線 路層L的一防烊層5〇〇。此外，在本實施例中，於形成防 焊層500之後’可選擇性地移除基板200之位於周邊區域 240的部分以及硬化層300。 綜上所述，本發明是藉由在基板的周邊區域中形成硬 化層來提升強度。如此一來，本發明可避免習知的基板因 1374693 30194twf.doc/n .· 厚度較薄以致於強度較差所導致的卡板 . 線路板的製程良率。而且，本發明之線跤題，進而可提升 習知的機台相容，故不需另外調整習知的製造方法與 雖然本發明已以實施例揭露如上，鈇=。 本發明，任何所屬技術領域中具有通常二 本發明之精神和範圍内，當可作些許之動盘 離 發明之保護範圍當視後附之申請專利範圍所^者為=本 ® 【圖式簡單說明】 圖1繪示習知之線路板的製程剖面圖。 圖2A〜圖2E緣示本發明一實施例之線路板的製程 面圖。 圖3A與圖3B分別繪示圖2A與圖2B的上視圖，且 圖2A與圖2B分別繪示圖3A與圖3B之基板沿Ι-Γ線段的 剖面圖。 圖4繪示圖3Α之基板沿ΙΙ-ΙΓ線段的剖面圖。 • 圖5Α〜圖5F繪示本發明一實施例之線路板的製程剖 面圖。 圖6Α〜圖6D繪示圖5Α〜圖5D的上視圖，且圖5八 〜圖5D繪示圖6Α〜圖6D之基板沿Ι-Γ線段的剖面圖。 圖7、圖8、圖9、圖10與圖11緣示圖6Β之硬化層 的五種變化結構。 ] 11 1374693 30194twf.doc/n . 【主要元件符號說明】 110 :線路基板 120 :滾輪 130 :喷嘴 200 :基板 210 :絕緣層 212、214'252、254 :表面 220、610 :導電層 ❿ 220a、610a :圖案化導電層 222 :中心部分 224:周邊部分 230 :中心區域 232 :第一側 234 :第二側 236 :第三側 238 :第四側 φ 240 :周邊區域 300、300a :硬化層 310 :條狀結構 320 :塊狀結構 400 :圖案化罩幕層 500 :防焊層 910 :網格狀結構 A :長度 12The figure ′ is formed on the peripheral portion 224 adjacent to the first side 232, the second side 234, the third side ^, and the first side 238 (please refer to Fig. 8). # π "In the case of A, please refer to FIG. 9, the material of the hardened layer 300a is covered with a material (for example, white paint), and the hardened layer includes at least two nets and a: the lattice structure 910 can be as shown in FIG. The display is formed on a peripheral portion adjacent to the side 234 of the body. The mesh ίο may also be formed on the peripheral portion * 224 adjacent to the first side 232 and the second side. Referring to FIG. H)), or 疋 is formed on the peripheral portion 224 adjacent to the fourth side, the second side 234, the third side 236, and the first side (10) of the 1374693 3194 twf.doc/n (please refer to FIG. u). In addition, please refer to the θ μ 斜 oblique spoon at the same time, and in Figure 6C ′ in this example, you can enter the 贝 除 除 除 除 除 除 除 除 除 除 除 除 除 除 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 It is to be noted that since the material of the hard layer 300 of the present embodiment is a plug material, the effect of the hardened layer and the slag process is performed. Death: the same day, see Figure 5D and Figure 6D 'for example, electroplating The method is formed - the electric layer 610 is on the conductive layer 22 〇 and the inner wall of the through hole § f. This implementation of the fiscal 'because of the hard layer encapsulation of this independent block, ', structure 32: 'The conductive layer q. The fine bonding area with the hardened layer is large, and the bonding force of the conductive layer 61〇 and the hardened layer 3〇〇 is forced to be lifted. Then, referring to FIG. 5E, for example, the pattern is patterned by lithography. The core portion 222 of the conductive layer 220 and the portion of the conductive layer 61 located at the central portion 230 are formed to form a circuit layer L. The circuit layer 1 includes a patterned conductive layer 220a and a patterned conductive layer 61A. In the embodiment, when the central portion 222 of the conductive layer 22 and the portion of the conductive layer 610 located at the central portion 23A are patterned in a manner of lithography, the gap Q is favorable for the substrate 200 and the photomask (not shown). Thereafter, referring to FIG. 5F, in the present embodiment, a tamper-proof layer 5A covering a portion of the wiring layer L is formed. Further, in the present embodiment, after the solder resist layer 500 is formed' The portion of the substrate 200 located in the peripheral region 240 and the hardened layer 300 may be selectively removed. In summary, the present invention enhances the strength by forming a hardened layer in the peripheral region of the substrate. Thus, the present invention can Avoid the conventional substrate due to 1374 693 30194twf.doc/n .. The thickness of the board is such that the strength of the board is poor, the process yield of the board. Moreover, the line problem of the invention can further improve the compatibility of the conventional machine, so There is a need to additionally adjust the conventional manufacturing method and although the present invention has been disclosed above by way of example, the present invention is within the spirit and scope of the present invention in any of the technical fields, and may be used as a discretionary invention. The scope of protection is as follows: the scope of the patent application is = this ® [Simplified description of the drawings] Figure 1 shows a process sectional view of a conventional circuit board. 2A to 2E are views showing a process of a circuit board according to an embodiment of the present invention. 3A and 3B are respectively a top view of FIG. 2A and FIG. 2B, and FIGS. 2A and 2B are respectively cross-sectional views of the substrate of FIGS. 3A and 3B along a Ι-Γ line segment. 4 is a cross-sectional view of the substrate of FIG. 3 along the ΙΙ-ΙΓ line segment. Fig. 5A to Fig. 5F are cross-sectional views showing the process of a circuit board according to an embodiment of the present invention. 6A to 5D are top views of FIGS. 5A to 5D, and FIGS. 5-8 to 5D are cross-sectional views of the substrate of FIG. 6A to FIG. 6D along a Ι-Γ line segment. Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. 11 show the five variations of the hardened layer of Fig. 6. 11 1374693 30194twf.doc/n. [Description of main component symbols] 110: circuit substrate 120: roller 130: nozzle 200: substrate 210: insulating layer 212, 214'252, 254: surface 220, 610: conductive layer ❿ 220a, 610a: patterned conductive layer 222: central portion 224: peripheral portion 230: central region 232: first side 234: second side 236: third side 238: fourth side φ 240: peripheral region 300, 300a: hardened layer 310 : strip structure 320 : block structure 400 : patterned mask layer 500 : solder resist layer 910 : grid structure A : length 12