TW200947658A - Chip package carrier and fabricating method thereof - Google Patents

Abstract

A chip package carrier including a first wiring layer, a second wiring, a dielectric layer and a conductive connection structure is provided. The first wiring includes at least one chip pad, and the second wiring layer includes at least one ball pad. The dielectric layer is disposed between the first wiring layer and the second wiring layer. The conductive connection structure has a top end-surface and a bottom end-surface opposite to the top end-surface, and the area of the top end-surface is eqeal or smaller than the area of the bottom end-surface. The chip pad is connected to the top end-surface, and the ball pad is connected to the bottom end-surface.

Description

200947658 υ/ι^υυπ 27283twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a chip package carrier ) and its manufacturing method. [Prior Art]

❹ Today's semiconductor technology is developed, and many wafers have a large number of transducer elements that are still densely arranged and many pads disposed on the surface of the wafer. In order to be able to use these wafers, particularly high number of pads, these wafers are typically mounted on a wafer package carrier to form a chip package. 1 is a schematic cross-sectional view of a conventional chip package. Referring to FIG. 1 'the conventional chip package 100 includes a chip package carrier 110, a wafer 120, and a plurality of solder balls S1, S2, wherein the wafer 12 is mounted on the chip package carrier 11 through the solder balls S1. on. The chip package carrier 110 includes an upper circuit layer 112, a lower circuit layer 114, a dielectric layer 116, and a plurality of conductive blind via structures ι8, wherein dielectric = 116 is disposed between the upper circuit layer 112 and the lower circuit layer 114. And these = electrically blind via structures m are electrically connected to the upper circuit layer 112 and the lower circuit layer upper circuit layer 112 includes a plurality of wafer pads 11a = =, and the lower circuit layer 114 includes a plurality of solder ball pads ^ Ma electrically connects the wafers 12 through the solder balls S1, and these 5 200947658 υ / xzuu ^ f 27283 twf.doc / n solder ball pads 114a connect the solder balls S2. Through the solder balls S2, the solder ball pads 114a can be electrically connected to an external circuit board, such as a motherboard (other board).

❹ These conductive blind via structures 118 are connected between the die pads U2a and the solder ball pads 114a. In detail, each of the electric blind hole structures 118 has an upper end surface 118a and a lower end surface U8b, wherein the upper end surface 118a is connected to the wafer pad 112a, and the lower end surface n8b is connected to the solder ball pad 114a. Further, the area of the upper end surface 118a is larger than the area of the lower end surface 118b. Since the conductive via structure 118 is connected between the die pad 112a and the solder ball pads H4a, the wafer 12 can pass through the solder balls S1 and the chip package carrier 110. Incomingly connect an external circuit board. In this way, the wafer ι2〇 operates. With the advancement of technology, today's handheld electronic devices, such as mobile phones, digital cameras, and notebook computers, are moving toward thinner, smaller, and lighter weights. In order to satisfy the above trend, the wafer package carrier 110 has to be developed toward a trend of increasing line density. How to improve the chip package The line density of the carrier 110 is an important issue at present. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a wafer package carrier to fabricate a wafer package carrier having a high line density. The present invention provides a wafer package carrier to increase line density. The present invention provides a method of fabricating a wafer package carrier, including the following steps: 200947658 071200^^7283twf.doc/n. First, a substrate is provided, wherein the substrate comprises a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer. Next, at least one blind via is formed on the substrate, wherein the blind via penetrates the dielectric layer and partially exposes the first conductive layer. Next, at least one blind via is formed on the substrate, wherein the blind via penetrates the dielectric layer and partially exposes the first conductive layer. Thereafter, an anti-mineral layer covering the first conductive layer is formed in a comprehensive manner. After forming the anti-plating layer, a via plating process is performed to form a conductive connection structure in the blind via, wherein the conductive connection structure fills the blind via. The electrically conductive connecting structure has an upper end surface and an lower end surface opposite to the upper end surface. The first conductive layer is connected to the upper end surface, and the second conductive layer is connected to the lower end surface. The area of the upper end face may be less than or equal to the area of the lower end face. The first conductive layer is then patterned to form a first wiring layer, the first wiring layer of the basin includes at least a wafer pad, and the wafer is connected to the upper end surface. In an embodiment of the invention, the patterning second conductive layer further comprises: forming a second wiring layer, wherein the second wiring layer comprises at least one solder ball pad and the solder ball pads are connected to the lower end surface. In the present invention-embodiment, the above method of forming a blind via includes a laser drilling process. In an embodiment of the invention, the thickness of the second conductive layer is simultaneously increased when the via plating process is performed. After the through-hole billing process, the thickness of the second conductive layer is further reduced. In an embodiment of the invention, the method of patterning the first conductive layer and the second conductive layer includes a lithography and etching process. 200947658 U/uuu4 z7283twf.d〇c/n The present invention further provides a chip package comprising a first wiring layer, a second wiring layer, a dielectric layer and a conductive connection structure. The first circuit layer includes at least one wafer pad. The second circuit layer includes at least one solder ball pad. The dielectric layer is disposed between the first circuit layer and the second circuit layer. The conductive connection structure is disposed in the dielectric layer and is connected between the die pad and the solder ball pad, wherein the conductive connection structure has an upper end surface and an upper end surface opposite to the upper end surface, and the area of the upper end surface may be less than or equal to The area of the lower end face. The wafer pad is connected to the upper end surface, and the solder ball pad is connected to the lower end surface. In an embodiment of the invention, the conductive connecting structure is tapered from a lower end surface toward an upper end surface. In an embodiment of the invention, the lower end surface has a concave or dimple. Since the first conductive layer is protected by the anti-plating layer during the process, the thickness and uniformity of the conductive layer are not affected by the process, and the etching of the post-forming circuit has a relatively good etching capability, so that the present invention can improve The line density of the chip package carrier. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] Figs. 2A to 2E are schematic flow charts showing a method of manufacturing a wafer package carrier according to an embodiment of the present invention. Referring first to Figure 2A, the method of fabricating a wafer-sealed loading board of the present embodiment includes the following steps. First, a substrate 21 is provided. The substrate 210 includes a first conductive layer 212', a second conductive layer 214, 200947658 u/ iz.w*t 27283 twf.doc/n, and a dielectric layer 216. The layer 216 is disposed between the first conductive layer 212 and the second conductive layer 214'. The material of the second conductive layer 212 and the second conductive layer 214' may be copper, aluminum or other suitable metal material, and the insulating layer 216 is, for example, a prepreg. In addition, the substrate 21A may be a copper foil substrate (CCL) or other suitable substrate. Referring to FIG. 2A and FIG. 2B, then, at least one blind via B' is formed on the substrate 21A, wherein the blind via B penetrates through the dielectric layer 216 and the second conductive layer 214, that is, the blind via B is from the second conductive layer 214. Extending to the first conductive layer 212. Further, the blind via B partially exposes the first conductive layer 212. Although only the two blind holes B' are shown in the head 2B, but in other solid covers, the blind holes B may be formed on the substrate 2 ι. Therefore, the number of the blind holes B shown in FIG. 2B is merely an example, not The invention is defined. The method of ❹/blind hole B may be a laser drilling process. When the blind hole b=^^ hole is formed, the step of forming the blind hole 8 includes irradiating a bundle of L on the second conductive layer 214, to dissolve a portion of the second conductive layer, the first snow: a file; Electrical layer 216. In other words, the laser beam L will be fired from the second electric layer 214' and burned through the dielectric layer 216 to form the blind hole B.丄8 has an opening Ή and a bottom surface F' where the bottom surface F is opposite to 歼u. The laser beam 烧 is from the second conductive layer 214 and begins to dissolve. The aperture of the blind hole B in the L-face L t embodiment may be tapered from the opening H toward the face F. Referring to Figure 2C, the 'forming-conducting connection structure 22 is within the blind ’' wherein the electrically conductive connection structure 220 is disposed within the dielectric layer 216. The electrical connection structure 220 fills the blind hole B and has an upper end surface 222 and a lower end surface 224. The upper end surface 222 is opposite the lower end surface, wherein the upper end surface 222 is located on the bottom surface. The lower end surface 224 is located at the opening 。. The conductive connection structure 220 is connected between the first conductive layer 212 and the second conductive layer 214. In detail, the first conductive layer 212 is connected to the upper end surface 222, and the second conductive layer 214' is connected to the lower end surface 224. Since the area of the opening σ 盲 of the blind hole is larger than the area of the bottom surface F,

The area of the upper end a? of the conductive connecting structure 220 may be smaller than the area of the lower end surface 224. In addition, since the hole length of the blind hole can be tapered from the opening n toward the bottom surface F, the conductive connection structure 220 can be tapered from the lower end surface 224 toward the upper end surface 222. In the present embodiment, the method of forming the conductive connection structure 220 may include the following steps. First, a __anti-clock layer is formed in which the anti-mine layer is superposed on the first conductive layer 212, and the anti-plating layer 230 may be a dry film. Next, after the anti-plating layer 23 is formed, a via plating process is performed to form the conductive connection structure 22G, wherein the via clock process includes electroless plating and electroforming. Since the first conductive layer 212 is completely covered by the anti-plating layer 230, and the through-hole plating process includes electroless plating and electroplating, when the above-mentioned through-hole electric remnant is performed, the thickness of the second conductive layer 214 is simultaneously The lower end surface 224 of the conductive connecting structure 220 forms a concave D, that is, the lower end surface 224 of the conductive connecting structure 220 has a concave D.

214, J π 圃 圃 图 2 2, in the through hole plating process ~ only the thickness of the first conductive layer 212' can correspond to the second conductive layer "200947658 \f I a ^.w * t 27283 Twf^doc/n ίThe method of manufacturing the guide carrier can include reducing the number

In summary, after the thickness of the second conductive layer 214 is increased, the second conductive layer 214' may be subjected to a (four) process, and (10) except for a portion of the second conductive layer 214'', the paste process may be fine. Process. After the second conductive layer 214' is subjected to a remnant process, the thickness of the second conductive layer 2M may be close to the thickness of the first conductive layer, or substantially equal to the thickness of the first conductive layer 212. In addition, after reducing the thickness of the second conductive layer 214, the anti-bond layer 23G may be removed to completely expose the first conductive layer 212 to 0 s. See FIG. 2D and FIG. 2E' and then 'pattern first. a conductive layer 212, to form a first wiring layer 212, and a patterned second conductive layer 214 to form a second wiring layer 214, wherein the first conductive layer 212 is patterned, and the second conductive layer 214' The method can be a lithography and etching process. After the first wiring layer 212 and the second wiring layer 214 are formed, substantially a wafer package carrier 200 including the first wiring layer 212, the second wiring layer 214, the dielectric layer 216, and the conductive connection structure 220 has been completed. The first circuit layer 212 includes at least one die pad 212a and a plurality of traces 212b', and the second circuit layer 214 includes at least one solder ball pad 214a and a plurality of traces 214b, wherein the ball bond pad 214a may be a ring Type ring pad. The conductive connection structure 220 is connected between the die pad 212a and the solder ball pad 214a, wherein the die pad 212a is connected to the upper end surface 222, and the solder ball pad 214a is connected to the lower end surface 224. In addition, when the solder ball pad 214a is a ring type pad, the lower end surface 224 is located in the ring type pad, that is, the lower end surface 224 is surrounded by the ball pad 214a. The wafer pads 212a can be electrically connected to a wafer (not shown), and the wafer pads 212a can be electrically connected to the wafer by flip chip, wire bond or the like. The solder ball pads 214a can be connected to solder balls to enable the package package carrier 200 to be assembled to an external circuit board, such as a motherboard. Since the conductive connection structure 220 is connected between the die pad 212a and the solder ball pad 214a, the wafer can be electrically connected to the outer φ circuit board by the chip package carrier 2 to operate. In other embodiments not shown, after the first wiring layer 212 and the second wiring layer 214 are formed, two solder resist layers may be formed on the first wiring layer 212 and the second wiring layer 214, respectively. The solder resist layers cover the first wiring layer 212 and the second wiring layer 214 to protect the first wiring layer 212 and the second wiring layer 214. In addition, the solder resist layers expose the die pad 212a and the solder ball pads 214a' to electrically connect the wafer to the external circuit board to the wafer package carrier 200. It is worth mentioning that although FIG. 2E only shows one wafer pad 212a and the ball (four) 214a, in other implementations, the first circuit layer 212 may include a plurality of die pads 212a, and the second circuit layer乜You can include multiple solder ball pads 2Ha. Accordingly, it is emphasized herein that the number of both the gusset pads 212a and the solder ball pads 214a shown by the figures is merely illustrative and not limiting of the invention. In summary, since the area of the upper end surface of the above-mentioned conductive connecting structure is larger than the area of the lower end surface, the wafer pad connected to the upper end surface can be counted as a small-area pad. Thus, the present invention can improve the line density of the chip package 12 200947658 27283 twjf, doc/nv, x a/vr carrier board to conform to today's handheld digital cameras and notebook computers, etc. (eg, mobile phones, volume) Light development trend. In the wafer package carrier of the present invention, the first wiring layer for forming the wafer pads is in the via plating process = ❹, and the first circuit layer does not need to be followed. == = two such 'in the manufacturing method of the chip package carrier, the thickness of the first layer of the present invention, the thickness of the first circuit layer, and the first circuit layer can be improved (fmepiteh), thereby improving the first line The present invention has been disclosed in the preferred embodiments of the present invention. Retouching, = The present invention is based on the definition of a wafer package. FIG. 1 is a schematic cross-sectional view of a conventional chip package. FIG. 2A to FIG. The wafer package carrier of the embodiment is manufactured The main flow of a method for symbol elements DESCRIPTION chip package 100 110: Chun closure wafer carrier layer 112 on line 112a, 212a:. Sook wafer pick 13 27283twf.doc / n 200947658 \ j / ντ

Lines 112b, 212b, 214b: walk 114: lower circuit layers 114a, 214a: solder ball pads 116, 216: dielectric layer 118: conductive blind via structures 118a, 222: upper end faces 118b, 224: lower end face 120: wafer 200 : Chip package carrier 210 : substrate 212 : first wiring layer 212 ′ : first conductive layer 214 : second wiring layer 214 ′ : second conductive layer 220 : conductive connection structure 230 : anti-plating layer B : blind hole D : concave Pattern F: bottom surface Η: opening L. laser beam S b: solder ball

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Claims (1)

200947658 27283twf.doc/n X. Patent Application Range: 1' A method for manufacturing a wafer package carrier, comprising: providing a substrate, wherein the substrate comprises a first conductive layer, a second and - disposed on the first conductive Forming at least one blind via on the substrate between the layer and the second conductive layer, wherein the blind via penetrates the via and partially exposes the first conductive layer; forming a comprehensive coverage of the first conductive layer After the conductive layer is formed, a through-hole plating process is performed to form a blind hole, and the conductive connection structure fills the k-electrode connection structure to have an upper end surface and a guide surface opposite to the upper end surface: The upper end face, and the second "= the first conductive layer" to form a first circuit layer includes at least a wafer interface, and the crystal 'connection:: 丄 包 包包二二! The carrier plate « , , ^ 呆 忑 忑 - conductive layer to form a flute _ &# i connect the circuit layer including at least - solder ball joints, and the ball is closed ^ as claimed in the scope of the patent The method for forming the blind hole in the wafer & rt includes a thunder Drilling 4 to form a green sheet of the conductive connecting structure 15 200947658 - / 283twf.doc / n to form a comprehensive coating covering the first conductive layer; and after forming the anti-plating layer, 5. A method for manufacturing a wafer package carrier as described in claim 4, wherein when the via plating process is performed, the thickness of the second conductive layer is simultaneously increased, and the via hole is formed. After the electroplating process, the method further includes reducing the thickness of the second conductive layer. The method of manufacturing the chip package carrier according to claim 1, wherein the first conductive layer and the second conductive are patterned. The method of layer includes a lithography and etching process. 7. A chip package carrier, comprising: a first circuit layer comprising at least one die pad; a second circuit layer comprising at least one solder ball pad; a dielectric a layer disposed between the first circuit layer and the second circuit layer, wherein the electrical connection structure is disposed in the dielectric layer and connected to the crystal=, and the spheroidal ball pad, wherein the layer Conductive connection structure Having a lower end surface of the upper end surface, the wafer is connected to the upper solder ball joint and connected to the lower end surface. The wafer package carrier board according to item 7 of the patent scope, The connection structure is tapered from the lower end surface toward the upper end surface. The lower end == the wafer package carrier board according to item 7, wherein two: no application: the wafer package described in item 7 is 16