TW201722224A - Printed circuit board and fabrication method thereof - Google Patents

Abstract

A printed circuit board is provided, including an insulating layer, a first pad layer, a wiring layer, an electronic component, a plurality of second pad layers, and a plurality of conductive vias. The insulating layer has a first side and a second side opposite to the first side. The first pad layer, the wiring layer, and the electronic component are embedded in the insulating layer and exposed to the first side. The second pad layers are on the second side of the insulating layer. The conductive vias are in the insulating layer, and connect the first pad layer, the electronic component and the second pad layers.

Description

Printed circuit board and manufacturing method thereof

The present invention relates to a printed circuit board and a method of fabricating the same, and more particularly to a printed circuit board without a core board and a method of fabricating the same.

Printed circuit boards (PCBs) are widely used in various electronic products such as mobile phones, personal digital assistants, and thin film transistor liquid crystal displays (TFT-LCDs). In addition to fixing various electronic components, the printed circuit board is mainly used to provide mutual current connection of electronic components.

The lightness of electronic products has become the trend of the development of the electronics industry today. With the shrinking demand for electronic products, how to improve the wiring density and layout area of printed circuit boards is an important issue in the circuit board industry.

According to an embodiment of the present invention, a printed circuit board includes: an insulating layer having a first side and a second side opposite to the first side; a first pad layer and a circuit layer respectively embedded In the insulating layer and exposed to the first side; an electronic component, embedded in the insulating layer, and exposed On the first side; a plurality of second pad layers on the second side of the insulating layer; and a plurality of conductive holes in the insulating layer, and respectively connecting the first pad layer, the electronic component and the second pad layer.

In addition, an embodiment of the present invention also provides a method for fabricating a printed circuit board, comprising: providing a core board and at least one circuit board structure on the core board; removing the core board to obtain a circuit board structure, including an insulating layer And a conductive layer, wherein the conductive layer is embedded in the insulating layer and exposed to one of the first sides of the insulating layer to form a first pad layer and a circuit layer; forming a through hole through the insulating layer of the circuit board structure, and The circuit board structure is attached to an adhesive material, wherein the first pad layer and the circuit layer are oriented toward the adhesive material; an electronic component is placed in the through hole, and the adhesive material fixes the electronic component; and another insulating layer is formed on the electronic component And on a second side of the insulating layer of the circuit board structure, the second side is opposite to the first side; forming a plurality of conductive holes in the insulating layer and/or another insulating layer, and forming a plurality of second pads Another insulating layer, wherein the conductive via connects the first pad layer, the electronic component and the second pad layers; and removes the adhesive material to expose the first pad layer, the circuit layer and the electronic component on the first side of the insulating layer.

102‧‧‧Insulation

104‧‧‧ first side

106‧‧‧ second side

108‧‧‧Electrical hole

110‧‧‧First cushion

112‧‧‧Wire

114‧‧‧Second cushion

302‧‧‧Central floor

304‧‧‧First conductive layer

306‧‧‧First insulation

308‧‧‧Second conductive layer

310‧‧‧ Third conductive layer

312‧‧‧First photosensitive layer

314‧‧‧ openings

315‧‧‧ openings

316‧‧‧(first) cushion

317‧‧‧Line layer

318‧‧‧Second insulation

320‧‧‧through hole

322‧‧‧Adhesive

324‧‧‧Electronic components

324A‧‧‧ positive

324B‧‧‧negative

326‧‧‧ Third insulation

328‧‧‧Blind hole

329‧‧‧Blind hole

330‧‧‧ plating initiation layer

332‧‧‧Second photosensitive layer

334‧‧‧ openings

336‧‧‧ fifth conductive layer

338‧‧‧Electrical hole

340‧‧‧Electrical hole

342‧‧‧Second cushion

344‧‧‧Protective layer

346‧‧‧ openings

348‧‧‧ plating initiation layer

350‧‧‧ copper bumps

352‧‧‧ openings

402‧‧‧Central floor

404‧‧‧First conductive layer

406‧‧‧First insulation

408‧‧‧Second conductive layer

410‧‧‧ Third conductive layer

412‧‧‧First photosensitive layer

414‧‧‧ openings

415‧‧‧ openings

416‧‧‧(first) cushion

417‧‧‧Line layer

418‧‧‧Second insulation

420‧‧‧Blind hole

422‧‧‧ plating initiation layer

424‧‧‧Second photosensitive layer

426‧‧‧ openings

428‧‧‧ fifth conductive layer

430‧‧‧Electrical hole

432‧‧‧through hole

434‧‧‧Adhesive

436‧‧‧Electronic components

436A‧‧‧ positive

436B‧‧‧negative

438‧‧‧ Third insulation layer

440‧‧‧Blind hole

441‧‧‧Blind hole

442‧‧‧ plating initiation layer

444‧‧‧ third photosensitive layer

446‧‧‧ openings

448‧‧‧ sixth conductive layer

450‧‧‧Electrical hole

452‧‧‧Electrical hole

454‧‧‧Second cushion

456‧‧‧protection layer

458‧‧‧ openings

460‧‧‧ plating initiation layer

462‧‧‧ copper bumps

464‧‧‧ openings

C1, C1'‧‧‧ board structure

C2, C2'‧‧‧ Printed Circuit Board

D‧‧‧distance

S1‧‧‧ first side

S2‧‧‧ second side

Figure 1 shows a plan view of a printed circuit board.

Figure 2 shows a cross-sectional view of a printed circuit board.

3A to 3M are cross-sectional views showing stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

4A to 4N are diagrams showing a printed circuit according to an embodiment of the present invention A cross-sectional view of each stage of the method of making the board.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 1 shows a plan view of a printed circuit board. Figure 2 shows a cross-sectional view of a printed circuit board. Referring to FIG. 1 and FIG. 2, an insulating layer 102 is used as a main body of a printed circuit board. A first pad layer 110 is on the first side 104 of the insulating layer 102, and a second pad layer 114 is located on the insulating layer 102. On the second side 106, the first pad layer 110 is connected to the second pad layer 114 via a conductive hole 108. A wire 112 is located on the first side 106 of the insulating layer 102.

As shown in Figures 1 and 2, the first pad layer 110 on the same layer (on the first side 104) of the printed circuit board is spaced apart from the wire 112 by a specific distance d because of the process capability or material. limits. Due to this particular distance limitation, the wiring density of printed circuit boards is limited. In addition, the electronic components (including active and/or passive components, not shown) of a general printed circuit board are disposed on the first side 104 and/or the second side 106 (surface) of the insulating layer 102, thus limiting printing. The layout area of the surface of the board is difficult to achieve.

According to the above, the following provides a printed circuit board and related manufacturing method, so that the pad layer and the circuit layer are embedded in the printed circuit board, so that the pad layer and the circuit layer and the wires on the surface of the printed circuit board can be located in different layers, so the pad The distance between the layer and the circuit layer and the wire is not limited to the process capability of image transfer, but the wiring density can be increased; in addition, at least one electronic component is set. Embedded in a printed circuit board, this increases the layout area of the printed circuit board surface and helps to reduce the surface area of the printed circuit board.

Hereinafter, a method of fabricating a printed circuit board according to an embodiment of the present invention will be described based on Figs. 3A to 3M. Referring to FIG. 3A, a copper foil substrate is provided comprising a center layer 302 and a first conductive layer (eg, copper foil) 304 formed on opposite sides of the center layer 302.

Next, a first insulating layer 306 is formed on the first conductive layer 304. In some embodiments, the material of the first insulating layer 306 includes an epoxy resin, a bismaleimie triacine (BT), and a polyimide (PI). ), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluoroethylene Polytetrafluorethylene (PTFE), and the first insulating layer 306 may be formed on the first conductive layer 304 by pressing or coating.

Subsequently, a second conductive layer 308 and a third conductive layer 310 are respectively formed on the first insulating layer 306. In some embodiments, the materials of the second conductive layer 308 and the third conductive layer 310 include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or alloys thereof, and the second conductive layer 308 and the first The three conductive layers 310 may have the same or different materials. In addition, the second conductive layer 308 and the third conductive layer 310 may be formed on the first insulating layer 306 by pressing or plating.

Referring to FIG. 3B, a first photosensitive layer 312 including at least one opening 314 and an opening 315 is formed on the third conductive layer 310. In some real In the embodiment, the first photosensitive layer 312 is formed by coating a dry film or coating and a subsequent lithography process.

Referring to FIGS. 3B and 3C, a region of the third conductive layer 310 that is not covered by the first photosensitive layer 312 (ie, in the opening 314 and the opening 315) forms a fourth conductive layer including at least one pad layer. 316 and a circuit layer 317. In some embodiments, the material of the fourth conductive layer comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or an alloy thereof, and the fourth conductive layer can be grown on the first photosensitive layer by electroplating. The opening 314 of the opening 312 and the opening 315. Subsequently, the first photosensitive layer 312 is removed.

Referring to FIG. 3D, a second insulating layer 318 is formed on the fourth conductive layer (including the pad layer 316 and the circuit layer 317), the third conductive layer 310, and the first insulating layer 306. In some embodiments, the material of the second insulating layer 318 includes an epoxy resin, a bismaleimide-triazabenzene (BT), a polyimine (PI), a build-up insulating film ( Ajinomoto build-up film), polyphenylene ether (PPO), polypropylene (PP), polymethyl acrylate (PMMA) or polytetrafluoroethylene (PTFE), and the second insulating layer 318 can be pressed or coated Formed on the fourth conductive layer, the third conductive layer 310, and the first insulating layer 306.

Then, a cutting process is performed to cut off a portion where the first insulating layer 306 and the second insulating layer 318 are attached (the broken line shown in the figure), so that the second conductive layer 308 and the third conductive layer can be formed in a subsequent step. Layer 310 is separated.

Referring to FIG. 3E, the second conductive layer 308 is separated from the third conductive layer 310 such that the copper foil substrate (including the center layer 302 and the two first conductive layers 304), the first insulating layer 306, and the second conductive layer 308 are included. One core board with The second insulating layer 318 is separated. Then, the core board is removed, and two circuit board structures C1 are obtained, wherein the two circuit board structures C1 are symmetrical to each other, and include a third conductive layer 310 and a fourth conductive layer thereon (including the pad layer 316 and Circuit layer 317) and second insulating layer 318.

However, in some embodiments, the foregoing process can also be performed on one of the core boards, such that after removing the core board, only a single board structure C1 is obtained.

It is to be noted that, in some embodiments, the third conductive layer 310, the fourth conductive layer (including the pad layer 316 and the circuit layer 317) and the first conductive layer 304 may be directly formed on the first conductive layer 304 of the copper foil substrate. The second insulating layer 318 (that is, the first insulating layer 306 and the second conductive layer 308 are omitted). Next, a cutting process is performed to cut the edge portion of the second insulating layer 318 and the first conductive layer 304 so that the core plate including the copper foil substrate and the third conductive layer 310 is separated from the second insulating layer 318. Then, the core board is removed to obtain the above two circuit board structures C1.

Referring to FIGS. 3E and 3F, for each of the two circuit board structures C1, the third conductive layer 310 is removed, so that the pad layer 316 of the fourth conductive layer embedded in the second insulating layer 318 and The circuit layer 317 is exposed. In some embodiments, the third conductive layer 310 can be removed by a wet chemical etch or dry etch process. Next, the second insulating layer 318 is subjected to a drilling process to form at least one through hole 320 penetrating the second insulating layer 318. In some embodiments, the via 320 can be formed by a mechanical drilling process.

Referring to FIGS. 3F and 3G, after forming the via 320 of the second insulating layer 318, the second insulating layer 318 is attached to an adhesive. The pad layer 316 and the circuit layer 317 of the fourth conductive layer embedded in the second insulating layer 318 are 322 (for example, a single-sided tape) facing the adhesive member 322. Next, an electronic component 324 is placed in the via 320 of the second insulating layer 318. Adhesive material 322 is used to secure electronic component 324. In some embodiments, the size (including length, width, and height) of the via 320 of the second insulating layer 318 corresponds to the electronic component 324, and the electronic component 324 can be placed in the second insulating layer 318 through a punching machine. In the through hole 320. In some embodiments, electronic component 324 can include an active component (eg, a CPU or memory, etc.) or a passive component (eg, a capacitor, resistor, inductor, etc.). In the exemplary embodiment, the electronic component 324 is a capacitor having a positive electrode 324A and a negative electrode 324B.

Referring to FIG. 3H, a third insulating layer 326 is formed on the second insulating layer 318 and the electronic component 324. In some embodiments, the material of the third insulating layer 326 includes an epoxy resin, a bismaleimide-triazabenzene (BT), a polyimine (PI), a build-up insulating film ( Ajinomoto build-up film), polyphenylene ether (PPO), polypropylene (PP), polymethyl acrylate (PMMA) or polytetrafluoroethylene (PTFE), and the third insulating layer 326 and the second insulating layer 318 may have Same or different materials. In addition, the third insulating layer 326 may be formed on the second insulating layer 318 and the electronic component 324 by pressing or coating. It is to be noted that when the third insulating layer 326 is formed on the second insulating layer 318 and the electronic component 324, the third insulating layer 326 portion is filled with the vias 320 of the electronic component 324 and the second insulating layer 318 ( The gap of FIG. 3F) can cover and fix the electronic component 324.

Referring to FIG. 3I, a drilling process is performed to form a blind via 328 in the third insulating layer 326 and the second insulating layer 318 to expose the fourth conductive layer. The pad layer 316 and the two blind holes 329 are formed in the third insulating layer 326 to expose the positive electrodes 324A and 324B of the electronic component (capacitor) 324. In some embodiments, the manner in which the blind holes 328 and 329 are formed includes a laser drilling process. Next, a plating initiation layer 330 is formed on the third insulating layer 326 in the blind vias 328 and 329. In some embodiments, the material of the plating initiation layer 330 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof, and the plating initiation layer 330 may be deposited in a blind hole. 328 and 329 are on the third insulating layer 326.

Referring to FIGS. 3I and 3J, a second photosensitive layer 332 including a plurality of openings 334 is formed on the plating initiation layer 330, and the positions of the openings 334 correspond to the blind holes 328 and 329. In some embodiments, the second photosensitive layer 332 is formed by a dry film or coating and subsequent lithography process. Next, the electroplating process is performed by using the electroplating starting layer 330 as a seed layer for electroplating, and a fifth conductive layer 336 is grown in a region (ie, the opening 328) where the electroplating starting layer 330 is not covered by the second photosensitive layer 332. The fifth conductive layer 336 can be filled into the blind holes 328 and 329, respectively, to form the conductive holes 338 and the conductive holes 340. In some embodiments, the material of the fifth conductive layer 336 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof.

Referring to FIGS. 3J and 3K, the second photosensitive layer 332 is removed, and the plating initiation layer 330 covering the second photosensitive layer 332 is removed. In some embodiments, the step of removing the plating initiation layer 330 overlying the second photosensitive layer 332 may employ a chemical etching method.

Referring to FIGS. 3K and 3L, the adhesive 322 attached to the second insulating layer 318 is removed, and the second insulating layer 318 is insulated from the third insulating layer 318. The layer 326 and the plurality of conductive structures are subjected to a flipping step such that the bottom portion faces upward and the top portion faces downward to form a printed circuit board C2 that does not include the core board.

As shown in FIG. 3L, the printed circuit board C2 includes an insulating layer (including a second insulating layer 318 and a third insulating layer 326) having a first side S1 and a second side S2 opposite to the first side S1; A first pad layer 316, a circuit layer 317 and an electronic component 324 are respectively embedded in the insulating layer and exposed to the first side S1; a plurality of second pad layers 342 are located on the second side S2 of the insulating layer And a plurality of conductive holes 338 and 340 are located in the insulating layer, and are respectively connected to the first pad layer 316, the electronic component 324 and the second pad layers 342. In some embodiments, the conductive vias 338 and 340 have slanted sidewalls, and more particularly, the conductive vias 338 and 340 are adjacent to portions of the second pad layer 342 (ie, adjacent to the second side S2 of the insulating layer). The portion adjacent to the first pad layer 316 and the electronic component 324 has a larger size.

It should be noted that, in the printed circuit board C2, since the pad layer 316 and the circuit layer 317 are embedded in the insulating layer, the pad layer 316 and the circuit layer 317 are located on the surface of the printed circuit board C2 (insulating layer). A portion of the wires (not shown) may be located in different layers, such that the distance between the pad layer 316 and the circuit layer 317 and the wires may not be limited by the process capability of image transfer (eg, wires on the insulating layer and adjacent insulating layers). The minimum distance between the pad layer 316 or the circuit layer 317 may be 10 μm or less, thereby increasing the wiring density of the printed circuit board C2. It is worth mentioning that, according to the above, the circuit conduction path in the printed circuit board C2 can be further shortened, so that electromagnetic interference (EMI) is reduced and better electrical performance is obtained.

In addition, since the electronic component 324 is embedded in the insulating layer, It is not necessary to occupy the space of the surface of the printed circuit board C2, so the layout area of the surface of the printed circuit board C2 can also be increased, and the surface area and the overall volume of the printed circuit board C2 can be reduced.

Referring to FIG. 3L and FIG. 3M again, in some embodiments, a protective layer 344 may be formed on the first side S1 and the second side S2 of the printed circuit board C2, wherein the protection is located on the second side S2. Layer 344 includes an opening 346 corresponding to the exposed first pad layer 316. Next, a plating initiation layer 348 is formed in the opening 346. The material of the plating starting layer 348 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or the above alloy, and the plating starting layer 348 can be formed by electroless plating. Next, an electroplating process is performed using the electroplating starting layer 348 as a seeding layer for electroplating, and at least one copper bump 350 is grown in the region of the electroplating starting layer 348 (ie, in the opening 346). Thereafter, a drilling process (for example, a mechanical drilling process) is performed to form a plurality of openings 352 in the protective layer 344 on the first side S1 and the second side S2 of the printed circuit board C2 to expose the first pad layer 316. The positive and negative electrodes 324A and 324B of the electronic component 324 and the second pad layer 342.

Hereinafter, a method of fabricating a printed circuit board according to another embodiment of the present invention will be described based on Figs. 4A to 4N. Referring to FIG. 4A, a copper foil substrate is provided comprising a center layer 402 and a first conductive layer (eg, copper foil) 404 formed on opposite sides of the center layer 402.

Next, a first insulating layer 406 is formed on the first conductive layer 404. In some embodiments, the material of the first insulating layer 406 includes an epoxy resin, a bismaleimide-triazabenzene (BT), a polyimine (PI), a build-up insulating film ( Ajinomoto build-up film), polyphenylene ether (PPO), polypropylene (PP), polymethyl acrylate (PMMA) or polytetrafluoroethylene (PTFE), and the first insulating layer 406 may be formed on the first conductive layer 404 by press bonding or coating.

Subsequently, a second conductive layer 408 and a third conductive layer 410 are respectively formed on the first insulating layer 406. In some embodiments, the materials of the second conductive layer 408 and the third conductive layer 410 include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or alloys thereof, and the second conductive layer 408 and the first The three conductive layers 410 may have the same or different materials. In addition, the second conductive layer 408 and the third conductive layer 410 may be formed on the first insulating layer 406 by pressing or plating.

Referring to FIG. 4B, a first photosensitive layer 412 including at least one opening 414 and an opening 415 is formed on the third conductive layer 410. In some embodiments, the first photosensitive layer 412 is formed by overlaying a dry film or coating and subsequent lithography processes.

Referring to FIGS. 4B and 4C, a region of the third conductive layer 410 that is not covered by the first photosensitive layer 412 (ie, in the opening 414 and the opening 415) forms a fourth conductive layer including at least one pad layer. 416 and a circuit layer 417. In some embodiments, the material of the fourth conductive layer comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or an alloy thereof, and the fourth conductive layer can be grown on the first photosensitive layer by electroplating. The opening 414 of the opening 412 and the opening 415. Subsequently, the first photosensitive layer 412 is removed.

Referring to FIG. 4D, a second insulating layer 418 is formed on the fourth conductive layer (including the pad layer 416 and the wiring layer 417), the third conductive layer 410, and the first insulating layer 406. In some embodiments, the second insulating layer 418 is packaged Including epoxy resin, bismaleimide-triazabenzene (BT), polyimine (PI), ajinomoto build-up film, polyphenylene ether (PPO) Polypropylene (PP), polymethyl acrylate (PMMA) or polytetrafluoroethylene (PTFE), and the second insulating layer 418 can be formed by pressing or coating on the fourth conductive layer, the third conductive layer 410 and On the first insulating layer 406.

Next, a drilling process is performed to form at least one blind via 420 in the second insulating layer 418 to expose the pad layer 416 of the fourth conductive layer. In some embodiments, the manner in which the blind holes 420 are formed includes a laser drilling process. Next, an electroplating starting layer 422 is formed on the second insulating layer 418 in the blind via 420. In some embodiments, the material of the plating initiation layer 422 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof, and the plating initiation layer 422 may be deposited in a blind hole. 420 is on the second insulating layer 418.

Referring to FIGS. 4D and 4E, a second photosensitive layer 424 including at least one opening 426 is formed on the plating initiation layer 422, and the position of the opening 426 corresponds to the blind via 420. In some embodiments, the second photosensitive layer 424 is formed by a dry film or coating and subsequent lithography process. Next, an electroplating process is performed using the electroplating starting layer 422 as a seed layer for electroplating, and a fifth conductive layer 428 is grown in a region (ie, the opening 426) where the electroplating starting layer 422 is not covered by the second photosensitive layer 424. The fifth conductive layer 428 can be filled into the blind via 420 to form the conductive via 430. In some embodiments, the material of the fifth conductive layer 428 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof.

Referring to FIGS. 4E and 4F, the second photosensitive layer 424 is removed, and the plating initiation layer 422 covering the second photosensitive layer 424 is removed. in In some embodiments, the step of removing the plating initiation layer 422 overlying the second photosensitive layer 424 may employ a chemical etching method.

Then, a cutting process is performed to cut off a portion where the first insulating layer 406 and the second insulating layer 418 are attached (the broken line shown in the figure), so that the second conductive layer 408 and the third conductive layer can be formed in a subsequent step. Layer 410 is separated.

Referring to FIG. 4G, the second conductive layer 408 is separated from the third conductive layer 410 such that the copper foil substrate (including the central layer 402 and the two first conductive layers 404), the first insulating layer 406, and the second conductive layer 408 are included. One of the core plates is separated from the second insulating layer 418. Then, removing the core board, two circuit board structures C1' are obtained, wherein the two circuit board structures C1' are symmetrical structures, and include a third conductive layer 410 and a fourth conductive layer thereon (including a pad layer) 416 and circuit layer 417), second insulating layer 318 and conductive structure.

However, in some embodiments, the aforementioned process operations may also be performed on one of the core boards, such that after the core board is removed, only a single board structure C1' is obtained.

It is to be noted that, in some embodiments, the third conductive layer 410 and the fourth conductive layer (including the pad layer 416 and the circuit layer 417) may be directly formed on the first conductive layer 404 of the copper foil substrate. The second insulating layer 418, the plating starting layer 422, and the fifth conductive layer 428 (that is, the first insulating layer 406 and the second conductive layer 408 are omitted). Next, a cutting process is performed to cut off the edge portion of the second insulating layer 418 and the first conductive layer 404, so that the core plate including the copper foil substrate and the third conductive layer 410 is separated from the second insulating layer 418. Then, the core board is removed to obtain the above two circuit board structures C1'.

Referring to FIG. 4G and FIG. 4H, for each of the two circuit board structures C1', the third conductive layer 410 is removed, so that the pad layer 416 of the fourth conductive layer embedded in the second insulating layer 418 is formed. And the circuit layer 417 is exposed. In some embodiments, the third conductive layer 410 can be removed by a wet chemical or dry etch process. Next, the second insulating layer 418 is subjected to a drilling process to form at least one through hole 432 penetrating the second insulating layer 418. In some embodiments, the through holes 432 can be formed by a mechanical drilling process.

Referring to FIGS. 4H and 4I, after forming the via 432 of the second insulating layer 418, the second insulating layer 418 is attached to an adhesive 434 (for example, a single-sided tape), and is embedded in the first layer. The pad layer 416 and the wiring layer 417 of the fourth conductive layer in the second insulating layer 418 are oriented toward the adhesive material 434. Next, an electronic component 436 is placed in the via 432 of the second insulating layer 418. Adhesive material 434 is used to secure electronic component 436. In some embodiments, the size (including length, width, and height) of the via 432 of the second insulating layer 418 corresponds to the electronic component 436, and the electronic component 436 can be placed in the second insulating layer 418 through a punching machine. Through hole 432. In some embodiments, electronic component 436 can include an active component (eg, a CPU or memory, etc.) or a passive component (eg, a capacitor, resistor, inductor, etc.). In the exemplary embodiment, the electronic component 436 is a capacitor having a positive electrode 436A and a negative electrode 436B.

Referring to FIG. 4J, a third insulating layer 438 is formed on the second insulating layer 418 and the electronic component 436. In some embodiments, the material of the third insulating layer 438 includes an epoxy resin, a bismaleimide-triazabenzene (BT), a polyimine (PI), a build-up insulating film ( Ajinomoto build-up film), polyphenylene ether (PPO), polypropylene (PP), polymethyl acrylate (PMMA) or polytetrafluoroethylene (PTFE), and the third insulating layer 438 and the second insulating layer 418 may have the same or different materials. In addition, the third insulating layer 438 may be formed on the second insulating layer 418 and the electronic component 436 by pressing or coating. It is to be noted that when the third insulating layer 438 is formed on the second insulating layer 418 and the electronic component 436, the third insulating layer 438 portion is filled with the via 432 of the electronic component 436 and the second insulating layer 418 ( The gap of the 4Hth) can cover and fix the electronic component 436.

Referring to FIGS. 4J and 4K , after the third insulating layer 438 is formed on the second insulating layer 418 and the electronic component 436 , the adhesive 434 attached to the second insulating layer 418 is removed. Then, a drilling process is performed to form a blind via 440 in the third insulating layer 438 to expose the conductive via 430 in the second insulating layer 418 and the fifth conductive layer 428 thereon, and in the third insulating layer 438. Two blind vias 441 are formed in which the positive electrodes 436A and 436B of the electronic component (capacitor) 436 are exposed. In some embodiments, the manner in which the blind holes 440 and 441 are formed includes a laser drilling process. Next, an electroplated starting layer 442 is formed on the third insulating layer 438 in the blind vias 440 and 441. In some embodiments, the material of the plating initiation layer 442 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof, and the plating initiation layer 442 may be formed in a blind hole by deposition. 440 and 441 are on the third insulating layer 438.

Referring to FIGS. 4K and 4L, a third photosensitive layer 444 including a plurality of openings 446 is formed on the plating initiation layer 442, and the positions of the openings 446 correspond to the blind holes 440 and 441. In some embodiments, the third photosensitive layer 444 is formed by a dry film or coating and subsequent lithography process. Next, an electroplating starting layer 442 is used as a seed layer for electroplating, and an electric power is performed. During the plating process, a sixth conductive layer 448 is grown in a region (ie, opening 446) where the plating initiation layer 442 is not covered by the third photosensitive layer 444, wherein the sixth conductive layer 448 can be filled into the blind holes 440 and 441, respectively. The conductive via 450 and the conductive via 452 are formed. In some embodiments, the material of the sixth conductive layer 448 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or an alloy thereof.

Referring to FIGS. 4L and 4M, the third photosensitive layer 444 is removed, and the plating initiation layer 442 covering the third photosensitive layer 444 is removed. In some embodiments, the step of removing the plating initiation layer 442 overlying the third photosensitive layer 444 may employ a chemical etching method. Next, the second insulating layer 418 and the third insulating layer 438 and the plurality of conductive structures are subjected to a flipping step such that the bottom portion faces upward and the top portion faces downward to form a printed circuit board C2' having no core board.

As shown in FIG. 4M, the printed circuit board C2' includes an insulating layer (including a second insulating layer 418 and a third insulating layer 438) having a first side S1 and a second side S2 opposite to the first side S1. A first pad layer 416, a circuit layer 417 and an electronic component 436 are respectively embedded in the insulating layer and exposed to the first side S1; a plurality of second pad layers 454 are located on the second side of the insulating layer And a plurality of conductive holes 430, 450 and 452 are located in the insulating layer, and are connected to the first pad layer 416, the electronic component 436 and the second pad layers 454, respectively. In some embodiments, the aforementioned conductive vias 430, 450, and 452 have sloped sidewalls, and more particularly, the conductive vias 430, 450, and 452 are adjacent to portions of the second pad layer 454 (ie, adjacent to the second side of the insulating layer) S2) has a larger size than the portion adjacent to the first pad layer 416 and the electronic component 436.

It should be particularly noted that in the aforementioned printed circuit board C2', Since the pad layer 416 and the circuit layer 417 are embedded in the insulating layer, the pad layer 416 and the circuit layer 417 and a part of the wires (not shown) on the surface of the printed circuit board C2' (insulating layer) may be located on different layers. The distance between the pad layer 416 and the circuit layer 417 and the wires may not be limited by the process capability of image transfer (e.g., the minimum distance between the wires on the insulating layer and the pad layer 416 or the circuit layer 417 in the adjacent insulating layer). It can be 10 μm or less, and the wiring density of the printed circuit board C2' can be increased. It is worth mentioning that, according to the above, the circuit conduction path in the printed circuit board C2' can be further shortened, so that electromagnetic interference (EMI) is reduced and better electrical performance is obtained.

In addition, since the electronic component 436 is embedded in the insulating layer without occupying the space of the surface of the printed circuit board C2', the layout area of the surface of the printed circuit board C2' can also be increased, and the printed circuit board C2' can be reduced. Surface area and overall volume.

Referring to FIG. 4M and FIG. 4N, in some embodiments, a protective layer 456 may be formed on the first side S1 and the second side S2 of the printed circuit board C2, wherein the protection is located on the second side S2. Layer 456 includes an opening 458 corresponding to the exposed first pad layer 416. Next, an electroplated starting layer 460 is formed in the opening 458. The material of the plating starting layer 460 includes nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten or the above alloy, and the plating starting layer 460 may be formed by electroless plating. Next, the plating initiation layer 460 is used as the seed layer for electroplating, and an electroplating process is performed to grow at least one copper bump 462 in the region of the plating initiation layer 460 (ie, in the opening 458). Thereafter, a drilling process (for example, a mechanical drilling process) is performed to form a plurality of protective layers 456 on the first side S1 and the second side S2 of the printed circuit board C2'. Opening 464 exposes first pad layer 416, positive and negative electrodes 436A and 436B of electronic component 436, and second pad layer 454.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art having the ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

316‧‧‧(first) cushion

317‧‧‧Line layer

318‧‧‧Second insulation

324‧‧‧Electronic components

324A‧‧‧ positive

324B‧‧‧negative

326‧‧‧ Third insulation

330‧‧‧ plating initiation layer

336‧‧‧ fifth conductive layer

338‧‧‧Electrical hole

340‧‧‧Electrical hole

342‧‧‧Second cushion

C2‧‧‧Printed circuit board

S1‧‧‧ first side

S2‧‧‧ second side

Claims (15)

A printed circuit board comprising: an insulating layer having a first side and a second side opposite the first side; a first pad layer and a circuit layer respectively embedded in the insulating layer and exposed to the The first side; an electronic component embedded in the insulating layer and exposed to the first side; a plurality of second pad layers on the second side of the insulating layer; and a plurality of conductive holes located at the first side In the insulating layer, the first pad layer, the electronic component and the second pad layers are respectively connected. The printed circuit board of claim 1, wherein the conductive holes have inclined side walls. The printed circuit board of claim 1, wherein a portion of the conductive holes adjacent to the second pad layers is larger than a size of the conductive holes adjacent to the first pad layer and the electronic component. The printed circuit board of claim 1, wherein the printed circuit board is a printed circuit board without a core board. The printed circuit board of claim 1, further comprising: a protective layer covering the insulating layer, wherein the protective layer has at least one opening exposing the first underlayer; and at least one copper bump is located In the opening, the first mat layer is connected. A manufacturing method of a printed circuit board, comprising: providing a core board and at least one circuit board structure on the core board; Removing the core board to obtain the circuit board structure, comprising an insulating layer and a conductive layer, the conductive layer is embedded in the insulating layer and exposed to a first side of the insulating layer to form a first pad layer and a circuit layer; forming a through hole of the insulating layer penetrating the circuit board structure, and attaching the circuit board structure to an adhesive material, wherein the first pad layer and the circuit layer are oriented toward the adhesive material; An electronic component is disposed in the through hole, and the adhesive material fixes the electronic component; forming another insulating layer on the second side of the electronic component and the insulating layer of the circuit board structure, the second side being opposite to the Forming a plurality of conductive holes in the insulating layer and/or the other insulating layer, and forming a plurality of second pads on the another insulating layer, wherein the conductive holes are connected to the first pad layer The electronic component and the second underlayer; and removing the adhesive to expose the first underlayer, the wiring layer and the electronic component on the first side of the insulating layer. The method for fabricating a printed circuit board according to claim 6, further comprising providing two mutually symmetric circuit board structures on opposite sides of the core board, and after removing the core board, obtaining the two The circuit board structure includes an insulating layer and a conductive layer. The conductive layer is embedded in the insulating layer and exposed to a first side of the insulating layer to form a first pad layer and a circuit layer. The method for manufacturing a printed circuit board according to claim 6, wherein in the step of providing a core board and at least one circuit board structure on the core board, the method further comprises: Providing a copper foil substrate comprising a center layer and at least one first conductive layer formed on the center layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer and a third conductive layer Laminating on the first insulating layer; forming a fourth conductive layer on the third conductive layer; and forming a second insulating layer on the fourth conductive layer, the third conductive layer and the first insulating layer. The manufacturing method of the printed circuit board of claim 8, wherein the step of removing the core board to obtain the circuit board structure further comprises: performing a cutting process, cutting the first insulating layer and the a portion of the second insulating layer that is bonded; separating the second conductive layer from the third conductive layer, such that the core plate including the copper foil substrate, the first insulating layer, and the second conductive layer and the second insulating layer Separating the layers and removing the core plate; and removing the third conductive layer to obtain the circuit board structure including the second insulating layer and the fourth conductive layer, wherein the fourth conductive layer is embedded in the second insulating layer And forming a first pad layer and a circuit layer in the layer and exposing to the first side of the second insulating layer. The method for fabricating a printed circuit board according to claim 9, wherein before the step of removing the core plate to obtain the circuit board structure, forming another conductive hole in the second insulating layer and connecting The first pad layer of the fourth conductive layer. A method of manufacturing a printed circuit board according to claim 6 of the patent application, The step of removing the adhesive is performed after the step of forming the other insulating layer on the second side of the electronic component and the insulating layer of the circuit board structure. The method of fabricating a printed circuit board according to claim 6, wherein the another insulating layer is formed on the second side of the electronic component and the insulating layer of the circuit board structure. The layer portion is filled with a gap between the electronic component and the through hole to cover and fix the electronic component. The method for fabricating a printed circuit board according to claim 6, wherein after the step of exposing the first pad layer, the circuit layer and the electronic component on the first side of the insulating layer, the method further comprises: Forming a protective layer on the first side of the insulating layer; forming at least one opening in the protective layer to expose the first pad layer; and forming at least one copper bump in the opening and connecting the first pad layer . The method for fabricating a printed circuit board according to claim 13, further comprising: forming a plurality of other openings in the protective layer to expose the circuit layer and the electronic component; and forming another protective layer on the other An insulating layer is formed, and a plurality of openings are formed in the other protective layer to expose the second layer pads. The method of manufacturing a printed circuit board according to claim 6, wherein the electronic component is an active component or a passive component.