TWI369115B - Signal interleaving for serial clock and data recovery - Google Patents

Signal interleaving for serial clock and data recovery

Info

Publication number
TWI369115B
TWI369115B TW096135806A TW96135806A TWI369115B TW I369115 B TWI369115 B TW I369115B TW 096135806 A TW096135806 A TW 096135806A TW 96135806 A TW96135806 A TW 96135806A TW I369115 B TWI369115 B TW I369115B
Authority
TW
Taiwan
Prior art keywords
data recovery
serial clock
signal interleaving
interleaving
signal
Prior art date
Application number
TW096135806A
Other languages
English (en)
Other versions
TW200828933A (en
Inventor
Dong-Yun Lee
Sung-Joon Kim
Original Assignee
Silicon Image Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=38917733&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TWI369115(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Silicon Image Inc filed Critical Silicon Image Inc
Publication of TW200828933A publication Critical patent/TW200828933A/zh
Application granted granted Critical
Publication of TWI369115B publication Critical patent/TWI369115B/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
TW096135806A 2006-09-25 2007-09-26 Signal interleaving for serial clock and data recovery TWI369115B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84734206P 2006-09-25 2006-09-25

Publications (2)

Publication Number Publication Date
TW200828933A TW200828933A (en) 2008-07-01
TWI369115B true TWI369115B (en) 2012-07-21

Family

ID=38917733

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096135806A TWI369115B (en) 2006-09-25 2007-09-26 Signal interleaving for serial clock and data recovery

Country Status (6)

Country Link
US (1) US8160192B2 (zh)
EP (1) EP1903712B1 (zh)
JP (2) JP5269387B2 (zh)
KR (1) KR101421481B1 (zh)
CN (1) CN101188490B (zh)
TW (1) TWI369115B (zh)

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US7742507B1 (en) * 2006-03-28 2010-06-22 Nortel Networks Limited Method and system for phase and byte alignment on a multiplexed high speed bus
US8204166B2 (en) * 2007-10-08 2012-06-19 Freescale Semiconductor, Inc. Clock circuit with clock transfer capability and method
GB2456517A (en) * 2008-01-15 2009-07-22 Andrzej Radecki Serial data communication circuit for use with transmission lines using both data and clock to enable recovery of data synchronously
KR20100129017A (ko) * 2009-05-29 2010-12-08 칭화대학교 지연 동기 루프 및 이를 포함하는 전자 장치
US8878792B2 (en) * 2009-08-13 2014-11-04 Samsung Electronics Co., Ltd. Clock and data recovery circuit of a source driver and a display device
US8222941B2 (en) * 2010-04-14 2012-07-17 Himax Technologies Limited Phase selector
US8548323B2 (en) * 2010-04-23 2013-10-01 Broadcom Corporation Daisy chainable ONU
DE112010005820B4 (de) 2010-08-23 2022-06-23 Toyota Jidosha Kabushiki Kaisha Elektrisch heizender Katalysator
US20120154059A1 (en) * 2010-12-17 2012-06-21 Nxp B.V. Multi phase clock and data recovery system
JP2012149604A (ja) 2011-01-20 2012-08-09 Ibiden Co Ltd 保持シール材、排ガス浄化装置、及び、排ガス浄化装置の製造方法
US9331878B2 (en) * 2011-06-14 2016-05-03 Agency For Science, Technology And Research Frequency shift keying transmitter
RU2014117004A (ru) 2011-11-02 2015-12-10 Тойота Дзидося Кабусики Кайся Регулирующее устройство для электроподогреваемого каталитического нейтрализатора
TWI449926B (zh) * 2012-04-09 2014-08-21 Wistron Corp 傳輸介面及判斷傳輸訊號之方法
TWI487287B (zh) * 2013-01-11 2015-06-01 Himax Tech Ltd 資料及時脈恢復裝置
CN104253620B (zh) * 2014-09-17 2016-03-30 清华大学 一种新型的高速串行接口发射机
CN105991136B (zh) * 2015-03-03 2020-12-01 上海联影医疗科技股份有限公司 模数转换器的串行接口及其数据对齐方法和装置
KR20200060612A (ko) * 2018-11-22 2020-06-01 삼성전자주식회사 데이터를 복원하기 위한 샘플링 타이밍을 조절하도록 구성되는 전자 회로
US11380395B2 (en) * 2020-09-04 2022-07-05 Micron Technology, Inc. Access command delay using delay locked loop (DLL) circuitry

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247903A (ja) * 1997-03-04 1998-09-14 Oki Electric Ind Co Ltd ビット同期回路
US6100735A (en) * 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
JP2001186111A (ja) * 1999-12-24 2001-07-06 Nec Corp ビット同期回路
JP4526194B2 (ja) * 2001-01-11 2010-08-18 ルネサスエレクトロニクス株式会社 オーバーサンプリングクロックリカバリ方法及び回路
KR100400041B1 (ko) * 2001-04-20 2003-09-29 삼성전자주식회사 정밀한 위상 조절이 가능한 지연 동기 루프 및 위상 조절방법
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
GB2385728B (en) * 2002-02-26 2006-07-12 Fujitsu Ltd Clock recovery circuitry
DE102004014695B4 (de) * 2003-03-26 2007-08-16 Infineon Technologies Ag Takt- und Datenwiedergewinnungseinheit
US6861886B1 (en) * 2003-05-21 2005-03-01 National Semiconductor Corporation Clock deskew protocol using a delay-locked loop
CN1307566C (zh) * 2003-10-29 2007-03-28 威盛电子股份有限公司 时钟及数据恢复电路
WO2005050231A1 (ja) * 2003-11-20 2005-06-02 Advantest Corporation タイミングコンパレータ、データサンプリング装置、及び試験装置
US7034597B1 (en) * 2004-09-03 2006-04-25 Ami Semiconductor, Inc. Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
TWI256539B (en) * 2004-11-09 2006-06-11 Realtek Semiconductor Corp Apparatus and method for generating a clock signal
US8085880B2 (en) * 2004-12-23 2011-12-27 Rambus Inc. Amplitude monitor for high-speed signals
US20070230646A1 (en) * 2006-03-28 2007-10-04 Talbot Gerald R Phase recovery from forward clock

Also Published As

Publication number Publication date
EP1903712B1 (en) 2012-11-21
CN101188490B (zh) 2013-04-10
JP5269387B2 (ja) 2013-08-21
EP1903712A3 (en) 2011-08-03
JP2013179671A (ja) 2013-09-09
TW200828933A (en) 2008-07-01
CN101188490A (zh) 2008-05-28
EP1903712A2 (en) 2008-03-26
US20080075222A1 (en) 2008-03-27
US8160192B2 (en) 2012-04-17
KR20080028341A (ko) 2008-03-31
KR101421481B1 (ko) 2014-07-22
JP2008099303A (ja) 2008-04-24

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