TWI362110B - Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof - Google Patents

Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof Download PDF

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TWI362110B
TWI362110B TW096127977A TW96127977A TWI362110B TW I362110 B TWI362110 B TW I362110B TW 096127977 A TW096127977 A TW 096127977A TW 96127977 A TW96127977 A TW 96127977A TW I362110 B TWI362110 B TW I362110B
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Taiwan
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layer
barrier layer
semiconductor device
voltage gate
boron
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TW096127977A
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TW200814312A (en
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Chyi Chyuan Huang
Shyh An Lin
Chenfu Hsu
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Taiwan Semiconductor Mfg
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1362110 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體元件 有關於改善半f體元件m H成方法，且特別 壓閉極氧化層所導致的不穩定。 ’、煎至冋电 【先前技術】 為頭件已被大量的使用在各種的應用上，且變 電話及家庭娛樂等。而電子：杜::中的應用包括電腦、 脊…“ k 電兀件被大量應用的理由之- 的擴充及成本的降低。因此技術上的改良已 成為發展半導體元件的重要部分。 ㈣以I:簡要說明用來形成半導體元件的製程。將- 電子元作為—基底或基板，録其上方形成各種 二。：此材料形成一適當的形狀，通常是稱為晶 子或：：；：選擇性地以一種或複數種摻質，如· 子偏子’處理此材料。藉由導 需的半導體特性。啬德夂絲β祕八 作貝U又付所 所需的元件 後各種結構會形成於晶圓上以獲得 面痕ί圓上的表面結構可以钱刻程序來完成。將晶圓表 =於-糊中。一般來說，可利用習知的微影技 。在《彡技術巾，光阻或其他抗钱 材料平勻地沉積於晶圓表面。此抗钱材料可選擇性透過 一罩幕來將部份的抗钱材料曝光而其他部份則未曝光。 0503^A32446TWF/kai 5 1362110 曝光後的光阻會變得更堅硬或更脆弱，接著可利用溶劑 清除較脆弱的部份，而存留的光阻可保護晶圓表面不被 蝕刻劑所侵蝕。當晶圓蝕刻程序完成後，再將之前存留 的光阻以一適當的溶劑去除。 此外，可利用各種沉積技術將其他材料，例如金屬 或其他導電及絕緣材料等沉積於晶圓表面，例如，以化 學氣相沉積（CVD)或濺鍍法進行沉積。也可額外佈植離 子。接著，選擇性地沉積及移除各種材料，使層狀堆疊 的電子元件結構形成於晶圓表面。 單一晶圓通常含有複數個晶粒，通常各晶粒皆為相 同結構，但並非絕對。在所有製程結束後（或在中間程序 時），可對晶圓進行檢查及測試，並將損壞的部份移除或 修復。最後將分離及測試過的晶粒封裝於一硬塑膠材料 中並以外部導線連接晶粒内部。封裝完成的晶粒具有許 多的導線，又可稱為晶片。 在製程當中，電子元件可同時形成於晶圓上。當某 一材料在沉積或選擇性蝕刻後，此材料可被用於許多相 同或不同的元件。因此需要小心的設計使其符合經濟效 益 例如，在高電壓混合訊號模式（high voltage mixed mode, HV-M.Μ)的應用方面，半導體元件具有一電容器結 構，置於NMOS低電壓（LV)閘極及NMOS高電壓（HV) 閘極之間，如第1A-1F圖所示。第1A-1F圖為半導體元 件10的傳統製程剖面圖，應注意的是，本文所述之“半 0503-A32446TWF/kai 6 1362110 導體元件”可為一或複數個晶粒所形成的晶片，且在其 他情況下，則是描述晶粒特定部份的元件或製程。 第1A-1F圖顯示半導體元件1〇的製備，首先形成基 板12，其被選擇性地摻雜以形成三個不同的區域。此三 個區域包括P型井15、n型井20及P型井25。在此步驟 中所形成三個區域可用來支持三個元件（請參照 圖）。如上所述，帛1圖的半導體元件包含此三種元件及 其相關結構。接著形成場氧化結構30、31、32、33 時（或之後）HV閘極氧化層％形成於 二 cmhQSiHeaie)化學氣相沉積及選擇 刻來形成。在沉積的材料上進酬程 的圖案，又稱為“圖案化”。 汀而要 第二閘極氧化層40形成於半導體元 如第1C圖所示。接著形成一 曰4表面， 性崎導電層以形成導電姓構' ;(:夕“夕)，並選擇 圖所示。結構46形成4!：:= 45道46及47 ’如第出 Α — / 電谷益的下導電層，導電結構45 為一 HV閘極，導電結構47 _ 化層/高溫氧化層，5^形成於盡φ 甲$ 〇多晶石夕間氧
—- V $成於導電結構46之上，如M 圖所示。最後，第二導電層 高溫氧化層5。之上以形成電容器的層/ 件10的表面配置如f 1F圖所*。 θ +導體兀 然而’由上述傳統製程所形成之 — 有可靠度;f料缺點。㈣ 服⑽層具 虱化層的低穩定度顯然是 °5〇3-A32446TWF/kai 7 1362110 在進行TEOS沉積時由p刑共 果。因[f ψ ^ ^ ^ p 土井15的硼擴散所造成的結 極的方法。 禋了衣備咼穩定度iiV閘 【發明内容】 本發明提供一種高穩定度的半導 成閘極氧化層之前沉積一 —，/、糸在形 氧化層的穩定度。 子轉層，以增加㈣閉極 本發明係提供-種半導體元件，包括 極及口閘極之間，此電容器形成^又 及一弟二導電層。導雷爲 、 等私層 圖案化成適#&構/ Λ積4成長多晶梦材料並 層結構二=:二:板。極板之間由介電 氮切層可為-薄；:：:二:化層及氮叫 成於λ拓卜㈠一少、 貝細例中，一離子阻障層形 ' (或夕晶矽氧化層形成於美;^卜u、i π 極氧化層分解所造成的離子Μ成^基板上）以防止閘 散的影般來^因為鬆 時，可顯現本發明之優勢^ 一鬧極形成於p型井上 為-氧化㈣。在例中，離子阻障層 葙數個务^ 乂 貝細例中，離子阻障層包括一或 =個虱乳化麵（Tax0yNz)、氮氧化鉛( 鋅（ZnOyNz)、碳化石夕⑶r 乳乳化 y及z為任何之非負整數。理拽 ’士δ—程序中沉積電容器介電層及離子阻障層。〜、 發明另提供一種半導體元件的形成方法，包括提 0503-Aj2446TWF/kai 8 1362110 供—基板’例如單晶矽晶圓， 包括p型井及相鄰的n型井心、丄反：形成複數個井， 上，且-氮化矽層形成於多曰，二:成”個元件 佳為-薄膜。在此實施例中，多=層上1切層較 介電層的—部份。 aa夕聽層形成電容器 石夕層可作為一哪停止声：層广成於p型井上，氮化 所造成的棚擴散。刊/ 極氧化材料的分解 在-較佳實施例中，沉積及==二化層。 電容器上極板及HV間極。〃取後的¥電層以形成 更明ίΓί本發明之上述和其他目的、特徵、和優點能 更明顯易'丨重，下文特舉較佳 〒俊點月匕 作詳細說明如下·· 例’並配合所附圖示， 【實施方式】 本發明係提供一種刹田^ +广 (HV-MM)技術來製造半導二電方^混合訊號模式 體元件包括-電容哭^ 法，本發明之半導 發明可應用於其他的半導體元件之上。本 造成的不良^件(=1缓和因硼擴散至Hv氧化區所 成的影響較下，鱗擴教至η型井上方所造 施例。 _ 至2F圖係顯示本發明之一實 0503-A32446TWF/kai 9 1362110 第2A至2F圖為半導體元件1〇〇之製程剖面圖 =實施例之^件與第1A_1F圖之元件類似，具有、 谷器基板與- HV閘極。與前案類似，首先在半 板上形成三個井區。在此實施例中，n型井ιΐ5形成= 板105中，且介於p型井及p型井m之間，如; 構、127、128、129，如第四圖所示。應注意的是， 上述各結構的相對尺寸可適度的改變。 利用，積與圖案化程序，如微影技術形成第—多晶 曰，如弟2C圖所示之多晶石夕結構13〇及135 的是，在此程序中多晶石夕結構並未形成 ^思 上述結構之上接或成長步驟形成於 ,也可使料’：佳為氮化梦 (Ta Ο Ν、Μ 之用/、他材科，例如氮氧化鈕 (Tax〇yNz)、乳氧化鍅(Zr〇yNz)、氮氧 條•氮氧切⑻侧之至少-種，tZ)x = 何之=數，Μζ為任何之非負整數，如第2d圖所示。 極板^ 層140在電容器結構_上下 要的// 為一良好的介電層（參照第2F圖）。更重 阻止或減緩在沉積Ην_氧化 擴散出來的硼。A 恭歆加占 了田P i·井110所 -閑極氧化：'例中1T£os沉積技術沉積 间独乳化材枓，亚利用濕式餘 化材料以形成閉極氧化結構】45，如第二：閉極氧 0503-A32446TWF/kai ώ丄丄t/ 在半導體元件〗〇〇 μ人I t -荽岡安π 々 上王面性沉積第二多晶矽層，接 者圖案化此多晶石夕層 7層接 第2E圖所示。上極姑^合盗I60的上極板150,如 ^ , 板150形成於Si#4層140上，且閘 極1)5形成於閘極氧化芦 閘 邮4 (或其他離子;如上所述，由於利用 避免蝴擴散，使間極^有/It保護間極氧化層145以 層是用HP ^ 的可靠度。由於離子阻障 itl又摇A'缓由P型井110所擴散出來的硼，因 此又稱為硼阻障層’，。 w 第二體元件的製造方法包括設置第-井於 一之間，形成第一氧化層於第一、第二及 二ΐ第—導電結構於氧化層及第-井上以及 弟一…D構於氧化層及第二井上方。接著沉積— 乳石夕⑶况)離子阻障層於第—、第二、及上 其中此Si3N4層形成於第 一井’ -^ L 汉弟一導电結構之上。形成第 -氧化層，形成第三導電結構 導電結構具有Si為層，且第二氧 : 形成第四導電結構於第層，取後 -間極，以作為—二弟四導電結構可形成 、 勹阿窀壓閘極。在一實施例中，第三并 為一 p型井。 一 ㈣另N?施例中’ S队層可包括一或複數個氮氧化 MTax〇yNz)、虱氣化錯(Zr〇yNz)、氮氧化辞(Zn〇^、碳 化石夕（slxcy)及氮氧化石夕（Six〇yNz)，其+ X為任何之正整 數’ y及z為任何之非負整數。 此實施例之形成方法包括形成一多晶石夕氧化膜，例 0503-A32446TWF/kai 11 (epi.⑴况層前利用—蟲晶成長程序 ,形成。在另一實施例中，以丁顧沉積 =:形成第二氧化層。第三及第四導電結構，如多晶矽： 同一程序中沉積而成。 带成tl—货施例中，本發明係提供—種半導體元件的 ==包括提供一基板，形成_p型井於該基板上， 積氦化發層於p型井上，形忠_ ^ (或其他料_；!& _ &料此氮化矽 序形成此氧化二Γ及上J以_沉積程 導電⑼^ 導電結構於氧化層上。此 以乂？： 極，例如，可作為-高電麗閘極，且 欠=?=。此方法更包括形成-電容器鄰接至此閉 電層於第-極板之上，此介電：包=板’形成-介 -第二極板於介電層之上：七羊石夕’以及形成 材料及單一的少曰二右。’極及第二極板可以相同的 早的多晶矽圖案化層形成。 在一實施例中，較佳同時 此氮化矽於p型井上 ’ 〃電層及沉積 物之介電；法包括形成—含多㈣氧化 多晶石夕氧^物 且在沉積氮切前先形成此 =柯明已以較佳實施例揭露如上 以限疋本發明，任何熟習此技 …、亚非用 精神和範圍内，當可作此也"在不脱離本發明之 之保護範圍當視後附％:二動广濶飾，因此本發明 甲。月專利乾圍所界定者為準。 0503-A32446TWF/kai 12 136211ο 【圖式簡單說明】 P型井及η型井區。 構，及一HV閘極氧化層 弟1A圖顯示在基板上形成 第1B圖顯示形成場氧化結 形成於p型井區上。 第1C圖顯示第二閘極氧仆 整個表I U魏層形成於半導體元件的 第1D圖顯示形成導電結構。 溫氧化層形成於導
^第1Ε圖顯示多晶矽間氧化層/高 電結構上。 圖顯示第—導電層沉積於曰 溫氧化層上以形成電容器的上導電層 間乳化層/高 ==示半導體基板上形成θρ型井及η型井區 第形成薄閑極氧化層及場氧化結構‘ 圖‘，„員不夕日日矽結構形成於閘極氧化声 示形成場氧化結構後沉積氮化；材料 f 2E圖顯示形成閘極氧化結構。 4 e。 第2F圖頭示本發明之半導體結構。 【主要元件符號說明】 1〇〜半導體元件； 12〜基板； 15、25〜P型井； 20〜N型井； 3〇、3卜32、33〜場氧化結構； 35〜HV閘極氧化層； 40〜第二閘極氧化層； 45、46、47〜導電結構； 5〇〜多晶矽間氧化層/高溫氧化層； 〇503-A32446TWF/kai 13 1362110 55- /第二導電層； 100〜半導體元件； 105 〜基板； 110、120〜ρ型井； 115 〜η型井； 125〜薄閘極氧化層； 126 、127、128、129〜場氧化結構； 130 、135〜多晶矽結構 ， 138· 〜多晶石夕氧化層； 140〜氮化發（Si3Ν4)層 145· 〜閘極氧化結構； 15 0〜上極板； 155 〜^閘極； 160〜電容器結構。
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Claims (1)

1/362110. __ 第96127977號申請專利範圍修正本 1〇〇年5月6日修正替換頁 ‘ 十、申請專利範圍： --—— • 1.一種半導體元件，包括： 一電容器，包括： 一第一導電層； 一第二導電層’設置於該第一導電層上方； 一硼阻障層的一第一部分，設置於該第一及第二導 電層之間作為一介電層；以及
一向電壓閘極，鄰近該電容器，包括： 該爛阻障層的一第二部分；以及 一導電層，設置於該硼阻障層的該第二部分上。 2.如申請專利範圍第1項所述之半導體元件，苴中嗜 硼阻障層包括氮化矽（Si3N4)。 一 3.如申請專利範圍第1項所述之半導體元件，並中該 :阻障層包括氮氧化㈣⑽具）、氮氧化錯沿〇具)了 氮乳化鋅（Zn〇yNz)、碳切（SixCy)及氮氧切抓〇而 之？種材料’其中χ為任何之正整數及 之非負整數。 -電4二lit利範圍第1項所述之半導體元件，其中該 间電屋閘極更包括一第一氧化層及一第 者以該硼阻障層的該第二部分隔離。 θ Λ 電容之第1項所述之半導體元件，其中該 電谷裔之卿P早層及該高電壓閘極之雜障層由一 程序沉積而成。 6.如申請專利範圍第5項所述之半導體元件，其中該 〇50j-A32446TWFl/chiaulin 15 1362110
第96127977號申請專利範圍修正本 硼阻障層為一薄膜。 __ 7_如申請專利範圍帛6項所述 伽障層的厚度在應至500入之間Λ體讀其中該 -低==範圍第1項所述之半導體元件，更包括 9·如申請專利範财8項所述之半導體元件，其中該 低電閘極包括該硼阻障層的一第三部分。 U).如申請專利範圍第丨項所述之半導體元件，其中 5亥回電壓閘極形成於一 ρ型井上0 11.如申料利㈣第丨項所述之半導體元件， j容器形成於1型井上’且該高電壓閘極形成於一 ρ 12.如申請專利範圍第u項所述之半導體元件，更包 括—低電壓閘極形成於一 p型井上。 ^ U.如申請專利範圍第12項所述之半導體元件，其中 該η型枝置於該低電壓閘極之p型井及該高電壓問極 之Ρ型井之間。 14·一種半導體元件，包括： 一基板，包括一 Ρ型井； 一電容器，形成於該基板上，該電容器包括一下極 板、上極板及一硼阻障層的一第一部分，該第一部分介 於上極板與下極板之間；以及 一高電壓閘極結構，形成於該Ρ型井之上，其中該 咼電壓閘極結構包括一形成於該硼阻障層的一第二部分 16 0503-A_>2446TWFl/chiaulin 1362110 第96127977號申请專利範圍修正本 ⑽年5月6日修正替換頁 • 上之閘極。 -—_〜 _ 15·如申請專利範圍第14項所述之半導體元件，1 該硼阻障層包括氮化矽（Si3N4)。 ’、 16.如申請專利範圍第14項所述之半導體元件，苴 該硼阻障層包括氮氧化鈕(Tax〇yNz)、氮氧化、鉛 、氮氧化辞(Zn〇yNz)、碳化石夕（SixCy)及氮氧化矽
=y z)之至少—種材料，其中χ為任何之正整數，乂及 z為任何之非負整數。 ^如申請專利範圍帛14項所述之半導體元件，更包 一乳化層，該氧化層以-氮切層與該p型井隔離。 18. —種半導體元件，包括： 一電容器，包括： 一第一導電層； 一第二導電層，設置於該第一導電層上；以及 …:氮化石夕⑸办)層的一第一部分，設置於該第一及 第一導電層之間，其作為一介電層；以及 一咼電壓閘極，鄰近該電容器，包括： 一第一氧化層； 該氮化矽（ShlSU)層的一第二部分； —第二氧化層；以及 該氮化矽（Si3N4) —導電層，設置於該第一氧化層、 層的該第二部分及該第二氧化層之上。 19.一種半導體元件的製造方法，包括： 提供一基板； 0503-A32446TWFl/chiaulin 17 1362110 第96127977號申請專利範圍修正本 上 100年5月6日修正替換頁 升^成電各器於該基板上，其步驟包括： 形成一第一導電層； 形成一硼阻障層的一第一部分於該第一導電層之 形成一第二導電層於該硼阻障層的該第一部分之 上，其中該硼阻障層的該第一部分作為一介電層；以及 同時形成一高電壓閘極於該電容器附近，其 電壓閘極包括該硼阻障層的一第二部分，以及二；； 於該硼阻障層的該第二部分之上。 曰 20.如申請專利範圍第19項所述之半導體元件的製 &方法，其中該硼阻障層包括氮化矽（SbNd。 止2L如申請專利範圍第19項所述之半導體元件的製 =中該硼阻障層包括氮氧化㈣帥抑、氮氧 化_^2)、氮氧化鋅(Zn〇yNz)、碳 化矽（SixOyNz)之至少一稀姑料，i 士 , 主乂種材枓，其中X為任何之正整數， y及z為任何之非負整數。 22. 如申請專利範圍第19項所述之半導體元件的製 法’其中該高閘極更包括-第-氧化層及一第 二氧化層，且兩者以該硼阻障層的該第二部分隔離。 23. 如申請專利範圍第19項所述之半導體元件的製 w法’其中該電容器之雜障層及 阻障層由—單一程序沉積而成。 2^.如申凊專利乾圍第19項所述之半導體元件的製 w万法，其中該硼阻障層為一薄膜。 0503-A32446TWF1/chiau|in 18 第96127977號申請專利範圍修正本 造方法，：中二利乾圍第19項所述之半導體元件的製 阻障層的厚度在1⑽至漏A之間。 造方法，專利範圍第19項所述之半導體元件的製 27 Λ 成一低電壓(LV)間極於該電容器附近。 ，告方法，甘請專利範圍第26項所述之半導體元件的製 W 、、中該低電閘極包括該硼阻障層的—第三部分。 、申Μ專利知圍第19項所述之半導體元件的製 这方法’其中該高電壓閘極形成於—Ρ型井上。 及如巾請專利範圍第19項所述之半導體元件的製 =法其中该電容器形成於一η型井上，且該高電壓 閘極形成於一 Ρ型井上。 ^ 3〇.如申請專利範圍第29項所述之半導體元件的製 造方法，更包括一低電壓閘極形成於一 ρ型井上。 31.如申請專利範圍第3〇項所述之半導體元件的製 ie方法，其中該η型井設置於該低電壓閘極之ρ型井及 該南電壓閘極之ρ型井之間。 0503-A32446TWFl/chiauIin 19 1362110
125 第96127977號圖式修正頁 100 ,
100
.126
第2F圖 .126
TW096127977A 2006-09-05 2007-07-31 Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof TWI362110B (en)

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Publication number Priority date Publication date Assignee Title
US7960810B2 (en) 2006-09-05 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof
US9859732B2 (en) 2014-09-16 2018-01-02 Navitas Semiconductor, Inc. Half bridge power conversion circuits using GaN devices
US9571093B2 (en) 2014-09-16 2017-02-14 Navitas Semiconductor, Inc. Half bridge driver circuits
US9960154B2 (en) 2014-09-19 2018-05-01 Navitas Semiconductor, Inc. GaN structures
US9831867B1 (en) 2016-02-22 2017-11-28 Navitas Semiconductor, Inc. Half bridge driver circuits
DE102018106266A1 (de) 2017-06-30 2019-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-struktur und verfahren zu ihrer herstellung
US10431664B2 (en) 2017-06-30 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and methods thereof
CN113161230B (zh) * 2020-12-14 2022-05-17 安徽安芯电子科技股份有限公司 磷硼同步一次扩散缓变结芯片的扩散工艺

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4449224A (en) * 1980-12-29 1984-05-15 Eliyahou Harari Dynamic merged load logic (MLL) and merged load memory (MLM)
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
JPH0491469A (ja) * 1990-08-01 1992-03-24 Sharp Corp 不揮発性半導体メモリ
US5393691A (en) * 1993-07-28 1995-02-28 Taiwan Semiconductor Manufacturing Company Fabrication of w-polycide-to-poly capacitors with high linearity
US5338701A (en) * 1993-11-03 1994-08-16 Taiwan Semiconductor Manufacturing Company Method for fabrication of w-polycide-to-poly capacitors with high linearity
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JPH08125152A (ja) * 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
JP3415712B2 (ja) * 1995-09-19 2003-06-09 松下電器産業株式会社 半導体装置及びその製造方法
US6228708B1 (en) 1998-12-10 2001-05-08 United Microelectronics Corp. Method of manufacturing high voltage mixed-mode device
DE69841040D1 (de) * 1998-12-22 2009-09-17 St Microelectronics Srl Herstellungsverfahren von EEPROM mit Peripherie
JP2001085625A (ja) * 1999-09-13 2001-03-30 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US6466427B1 (en) * 2000-05-31 2002-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic capacitor structure compatible with copper containing microelectronic conductor layer processing
US6498377B1 (en) * 2002-03-21 2002-12-24 Macronix International, Co., Ltd. SONOS component having high dielectric property
US6853052B2 (en) * 2002-03-26 2005-02-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a buffer layer against stress
JP4451594B2 (ja) * 2002-12-19 2010-04-14 株式会社ルネサステクノロジ 半導体集積回路装置及びその製造方法
JP4085891B2 (ja) * 2003-05-30 2008-05-14 ソニー株式会社 半導体装置およびその製造方法
CN100352062C (zh) 2003-10-30 2007-11-28 上海集成电路研发中心有限公司 一种高介电常数材料栅结构及其制备方法
US7960810B2 (en) 2006-09-05 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof

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