12481^—^ 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製造方法，且特 別是有關於一種提高載子遷移率(Carrier Mobility)的半導 體元件及其製造方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device for improving carrier mobility and manufacturing thereof. method. [Prior Art]
金屬氧化半導體電晶體(Metal_〇xide Semiconductor Transistor ; MOS)夾著其耗電量非常小，並且適合高密度 的積集製造等諸多優點，為現今半導體製程中，最重要而 且應用最廣泛的一種基本的電子元件。隨著半導體的積隼 度(imegmtion)的提昇，金屬氧化半導體電晶體的尺寸亦隨 ^小。'然而，其尺寸縮減有其極限，因此，如何利用其 善載子遷移率的方法廣;==的應雜—以改 對N型金氧半導體電晶體而言，於且 有拉伸應力(Tensile Stress)之氮 ；；上方復盖一層具 應變是幕所皆知的—種方法。且^1力=道的拉伸 的電子遷移率增加的程度與氮 體電晶體上 氮化石夕膜之應力將可控制N型金氧半導二f成正比，因此 f率增加的程度，氮化石夕膜的拉S3!晶體上電子遷 越佳。 μ力越鬲，電子遷移率 然而，另—方而 膜的拉伸應力二;=體電晶體而言， •對_成二反：二下： 5 ：/g 12481版 fdoc 與P型金氧半導體電晶體的半導體元件，如何於增加氮化 石夕膜的拉伸應力而加強N型金氧半導體電晶體之電子^ =時，又可以減少p型金氧半導體電晶體電洞遷移‘ 的哀減，是目前極需克服的問題。 【發明内容】 的製=此其種半導趙元件 加快元件的運作輕。 郷㈣衣減， 本發明的另一目的是提供一種半導體元处 N型金氧半導體電晶體的電子遷移率，又可以減二 型金氧半導體電晶體電崎料的衰減之絲。〜 2明提種半導體元件的製造方法 曰曰體，此介電層具有第_拉伸應力 ^體包 光阻層，暴露出p型金氧半導二兩曰 ；土 &上形成 阻層為罩幕，對p型金氧半導2二曰曰體之介電層。以光 子植入製程，以使此部分之介電 ,:：：進仃離 層 中，第二拉伸應力小於第；力、有二:拉伸應力，其 從狎應力。然後，再移除光阻 法 依照本發明的較佳實施例所述之半導體 ^述於猶光阻祕鎌介 方 依照本發明的較佳實施例所述之半導體元件的製造方 6Metal Oxide Semiconductor Transistor (MOS) is the most important and widely used one in today's semiconductor manufacturing process because it has a very small power consumption and is suitable for high-density integrated manufacturing. Basic electronic components. As the semiconductor's imegmtion increases, the size of the metal oxide semiconductor transistor also decreases. 'However, its size reduction has its limits, therefore, how to use its good carrier mobility method; == should be mixed - to change the N-type MOS transistor, and there is tensile stress ( Tensile Stress); a method of covering a layer with strain is known. And the degree of increase in the electron mobility of the stretching of the ^1 force = channel is proportional to the stress of the nitride film on the nitrogen oxide crystal, which is proportional to the N-type oxy-halide semiconductor f, so the degree of increase of the f-rate, nitrogen The electrons on the S3! crystal of the fossil eclipse are better. The more the μ force, the electron mobility, however, the other side, the tensile stress of the film is two; = the body transistor, • the opposite of _ two: two: 5: / g 12481 version of fdoc and P-type gold oxygen How can the semiconductor component of a semiconductor transistor reduce the electron beam of the N-type MOS transistor by increasing the tensile stress of the nitride film and reduce the hole migration of the p-type MOS transistor? It is an issue that needs to be overcome at present. [Invention] The system=This kind of semi-conductive Zhao component speeds up the operation of components.四 (4) Clothing reduction, another object of the present invention is to provide an electron mobility of an N-type MOS transistor at a semiconductor element, and a reduction in attenuation of a MOS transistor. The method for manufacturing a semiconductor device is characterized in that the dielectric layer has a first tensile stress and a photoresist layer, and a p-type gold-oxygen semiconductor is exposed; a resist layer is formed on the soil & For the mask, a dielectric layer for p-type MOS semiconductor 2 bismuth. The photon implantation process is used to make the dielectric of this part:::: into the delamination layer, the second tensile stress is less than the first; the force, two: the tensile stress, and the 狎 stress. Then, the photoresist is removed according to a preferred embodiment of the present invention. The semiconductor device is fabricated according to a preferred embodiment of the present invention.
12481版<_ 更可—型金氧半導體電 極之表面形成金㈣、祕區以及間 對準石夕化物製程。^…成方法例如疋進行自行 法，較佳實施例所述之半導體元件的製造方 =之；丨笔層例如是碳化石夕層或是氮化石夕層。 法，㈣的錄實施觸述之半導體元件的製造方 上^^拉/申應力例如約是介於… 铸^ ’更可以域切層形成後進行熱處理 ...…驟例如是尖峰回火（spike anneal)、紫 =:(「—）、電子束回火(心 或 田射回火（laser anneal)。 依照本發明的較佳實施例所述之半導體元件的製造方 1 ’上述之離子植人製程所植人之摻質可以為錯（Ge)原 ^其植人的能量例如是5G〜撕eV’其植人的劑量例如 疋1x10〜lxl〇16個原子/平方公分。 、依照本發明的較佳實施例所述之半導體元件的製造方 法，上述離子植入製程所植入之摻質還可以 子、氬（AO原子錢（Xe)原子。 J京 I本奄明k出一種半導體元件，其係由基底、至少一 p 型金氧半導體電晶體與—N型金氧半導體電晶體以及介電 ^所構成。其中，P型金氧半導體電晶體以及金氧半 ‘脰電晶體係設置於基底中。介電層至少係設置於p裂金 7 I2481M ^f.doc/g 氧半導體電晶體以及N型金氧半導The 12481 version of the <_ more-type MOS semiconductor electrode forms gold (four), secret zone and inter-alignment process. The method is, for example, a method of manufacturing a semiconductor device according to the preferred embodiment, and the layer of the pen is, for example, a carbonized stone layer or a nitride layer. The method of (4) is carried out on the manufacturing side of the semiconductor component. The ^ / pull stress is, for example, about... The casting ^ ' can be heat treated after the formation of the domain layer. The step is, for example, a spike tempering ( Spike anneal), purple =: ("-), electron beam tempering (heart or field anneal). Manufacturing of a semiconductor device according to a preferred embodiment of the present invention 1 'The above ion implant The dopant of the human process may be the wrong (Ge) source, and the energy of the implant is, for example, 5G~ tearing eV', and its implant dose is, for example, 疋1x10~lxl〇16 atoms/cm 2 . In the method for fabricating the semiconductor device according to the preferred embodiment, the dopant implanted in the ion implantation process can also be a sub-argon or an argon (AO atomic (Xe) atom. J. I. , which is composed of a substrate, at least one p-type MOS transistor, an N-type MOS transistor, and a dielectric device, wherein the P-type MOS transistor and the MOS semi- 脰 脰 crystal system are arranged. In the substrate, the dielectric layer is at least set in p-cracked gold 7 I2481M ^f.doc/g Oxygen semiconductor transistor and N-type gold oxide semiconductor
N型金氧半導體電晶體上之介電層^=^其中位在 型金氧半導體電晶體上之介電層的拉伸應力-力大於位在P 依照本發明的較佳實施例所述之半導 匕括金屬魏物層設置於p型金 2 ’更可以 金氧料體電晶體之_區、&_===及N型 介佳實施例所述之半導體元件，上述之 "电層之材質可以是碳化石夕或氮化石夕。兀件上述之 型金== = =元件… 氬或氙。 兒㈢中例如疋摻雜有鍺、矽、 本發明因於形成高拉伸應力 =導體電晶體上之介電層進二 “早且可.型金氧半導體 ; 應力，因而得以於提高N )1电層的拉伸 率的同時，減少P型金體的電子遷移 減，達到增加科運作逮度體電洞遷移率的衰 易懂為=其他目的、特徵和優點能更明顯 ^下了文特舉車父佳貫施例，並配合所附圖式，作詳細說 【實施方式】 種半所料騎照本料—雛實施例之一 種丰V體几件的製造流程剖面圖。 請參照圖U，此方法係先提供—絲·。基底1〇〇 1248 f.doc/g 上至少已形成有p型金氧半導體雕 半導體電晶體12〇。p型全氧半1=31 型金氧 氧半導體w _ 體電晶體⑽料型金 ί ^之形成方法為熟知此項技術者_ 於此不λ述。兩電晶體之間可以 隔離結構102例如是藉由淺$ =£域減⑽⑽)製程或是其他合適之製程，而形ί 接著，請參照圖1Β，於基底100 =住Ρ型金氧半導體電晶體_及νΪ 金氧 m =2。，介電層13。具有第一拉伸應力。介=二 :化石夕或氮化石夕或其他具拉伸應力之材質。並 法是電浆增強型化學氣相沈積 氣的比例_ t彳=_魏與氮 ㈤Pa之間的氮化^膜找出拉伸應力約是介於〇.5〜 芦二卜：frr形成更可以是在沈積-層氮化賴 熱處理步驟，以控制其拉伸應力約 W、峰口火（.k a之間。其中，熱處理步驟例如是利用 j 峨1)、紫外線烘烤⑽⑽ing)、電 子束回火（E-beam anneal)或是 等技術來進行。 4W(Lanneal) 140, ^出p型金氧半導體電晶體110上之介電層i3〇。光阻 層140例如是正光阻，其例如是先以旋轉塗佈（_ 12481偷 wfd()e/g coating)方狀介電層⑽上形成絲㈣層(未圖示）， 再利用曝光顯影製程圖案化光阻材料層，形成光阻層刚。 繼而，請參照圖1D，以光阻層14〇為罩幕，; 氧半導體電晶體U0上之介電層13〇進行一離子植程 150。離子植入製程150所植入之推質例如是石夕⑻軒、 風㈤原子或氣㈤原子。另外，也可以植入錯（⑽ 摻質。植人鍺（Ge)原子的方式例如是控制植入能 里力在50〜200keV，植入劑量約係^⑺丨3〜〗心 方公分來進行離子植入。 原子/千 然後’請參照圖1E，P型金氧半導體電晶體ιι〇上 ”電層130在經過離子植入製程15〇之 被降低’接近啊’成為具有第二拉伸應力的= 130，。苴中，介帝恳，斤 〜”甩層 之第-θ 弟二拉伸應力遠小於介電層130 ^」伸應力。繼而，移除光阻層刚，移除的方法 〇疋以濕式去光阻或乾式去光阻的方式來進行。在一奋 移除光阻層⑽之後，更可以移除介電層13= 二電i 130 ’如圖1F所示，以便於後續其他製程，如自 打對準紗化物製程（self-aligned silidde)之進行。 n以下係針對利用上述方法所得之結構加以說明。浐泉 照圖1E，本發明之半導體元件係由基底ι〇〇、ρ型金= 導體電晶體11G、N型金氧半導體電晶體12G、介電層13〇 以及’I電I 130,所構成。兩電晶體可以是藉 搬而將魏隔開來。其中，p型金氧半導體電晶體= 以及N型金氧半導體電晶體12〇係設置於基底100中。介The dielectric layer on the N-type MOS transistor has a tensile stress-force greater than the position of the dielectric layer on the MOS transistor, as described in the preferred embodiment of the present invention. The semi-conducting layer includes a metal material layer disposed on the p-type gold 2', and may be a MOS region, a <==== and a semiconductor device described in the N-type embodiment, the above " The material of the electric layer may be carbon stone or nitrite. The above type of gold == = = component... Argon or helium. In the case of (3), for example, yttrium is doped with yttrium and ytterbium, and the present invention is formed by the high tensile stress = the dielectric layer on the conductor transistor enters the "early and sizable type MOS; stress, thereby improving N) At the same time of the tensile rate of the electric layer, the electron migration of the P-type gold body is reduced, and the decline of the mobility of the body hole is improved. The other purposes, characteristics and advantages can be more obvious. In particular, the car owner's example is applied in detail, and in conjunction with the drawings, a detailed description of the manufacturing process of the semi-finished material of the embodiment of the invention. Figure U, this method is first provided - silk. The substrate 1〇〇1248 f.doc/g has at least formed a p-type MOS semiconductor transistor 12〇. p-type all-oxygen half 1=31 type gold oxide The formation method of the oxygen semiconductor w _ bulk transistor (10) type gold ί ^ is well known to those skilled in the art _ which is not described herein. The isolation structure 102 between the two transistors is, for example, reduced by shallow (= 10) (10) (10) Process or other suitable process, and then ί, please refer to Figure 1Β, on the substrate 100 = Ρ type MOS The transistor _ and ν Ϊ gold oxide m = 2. The dielectric layer 13 has the first tensile stress. The medium = two: fossil or nitrite or other materials with tensile stress. The method is plasma enhanced. The ratio of chemical vapor deposition gas _t彳=_Wei and nitrogen (five) Pa between the nitriding film to find the tensile stress is about 〇.5~ 芦二卜: frr formation can be in the deposition-layer nitrogen The heat treatment step is controlled to control the tensile stress of about W, the peak fire (between .ka, wherein the heat treatment step is, for example, using j 峨1), the ultraviolet baking (10) (10) ing, and the electron beam tempering (E-beam anneal). Or a technique to perform. 4W (Lanneal) 140, the dielectric layer i3 on the p-type MOS transistor 110. The photoresist layer 140 is, for example, a positive photoresist, which is, for example, first spin-coated (_ 12481 steals wfd()e/g coating) A wire (four) layer (not shown) is formed on the square dielectric layer (10), and the photoresist layer is patterned by an exposure and development process to form a photoresist layer. Next, please refer to the figure. 1D, with the photoresist layer 14 as a mask; the dielectric layer 13 on the oxygen semiconductor transistor U0 performs an ion implantation process 150. The ion implantation process 1 The implants of 50 implants are, for example, Shi Xi (8) Xuan, Feng (5) atoms or gas (5) atoms. In addition, it is also possible to implant the wrong ((10) dopant. The way to implant the Ge atom is, for example, to control the implant energy. The force is 50~200keV, and the implantation dose is about ^(7)丨3~〗Xifang for ion implantation. Atomic/thousand then 'Please refer to Figure 1E, P-type MOS transistor ιι〇" on the electrical layer 130 After being subjected to the ion implantation process, it is reduced to 'close' to become the second tensile stress = 130. In the middle, the tensile stress of the first-theta is less than that of the first layer. The dielectric layer 130 is extended to stress. Then, the photoresist layer is removed, and the removal method is performed by wet photoresist or dry photoresist removal. After removing the photoresist layer (10), the dielectric layer 13 = two electrodes i 130 ' can be removed as shown in FIG. 1F to facilitate subsequent processes, such as self-aligned silidde. Go on. n The following is a description of the structure obtained by the above method. Referring to FIG. 1E, the semiconductor device of the present invention is composed of a substrate ι, a p-type gold = a conductor transistor 11G, an N-type MOS transistor 12G, a dielectric layer 13A, and an 'I-I 130. . The two transistors can be separated by the transfer. Among them, a p-type MOS transistor = and an N-type MOS transistor 12 are provided in the substrate 100. Jie
I2481i_/g 電層i3〇’係設置於p型金氧半導體電晶體11〇±， 層no則設置在N型金氧半導體電晶體12〇上，豆中位= n型金氧半導體電晶體12G上之介電層⑽的拉伸應 於位在p型金氧半導體電晶體UG上之介電層i3G，的拉 ，力’且介電層13〇’中例如是摻雜有鍺、硬、氬或氣等換 、上述實施例之製造方法’於1>型金氧半導體電晶體11〇 以及N型金氧半導體電晶體12〇上形成介電層別之後， 對p型金氧半導體電晶體11G上之介電層l3G進行離子植 ^製程ISO，此方法之步驟簡單，製程相當容易，且可有 效降低P型金氧半導體電晶體11G上介電層⑽，之拉伸應 1 因為具有拉伸應力介電層i3G之形成，而導致； 金氧半導體電晶體11G電洞遷料衰減的問題。 圖2A至圖2E所繪示為依照本發明另一較佳實施例之 一種半導體元件的製造流程剖面圖。 請參照圖2A，此方法係先提供基底2〇〇，基底2〇〇上 =至少是已形成有p型金氧半導體電晶體2ig以及N型 ^氧半導體電晶體220。其中，p型金氧半導體電晶體21〇 ^ N型金氧半導體電晶體22〇之形成方法為熟知此項技術 2所週知、’於此不贅述。兩電晶體之間可以是用隔離結構 播制來作為區隔。隔離結構2〇2例如是藉由淺溝渠隔離結 構4程、區域氧化(L〇c〇s)製程或是其他合適之製程，而 形成之。 此外’ P型金氧半導體電晶體210之源極區214a、汲 12481^4^/ 極區214b以及間極212之表面以及n型金氧半導體電晶 體220之源極區224a、汲極區224b以及閘極222之: 已形成金屬矽化物層225。金屬矽化物層225之形^ 例如是進行自行對準矽化物製程。 / 、接^，請參照圖2B，於基底2〇〇上形成介電層， 至少覆盖住P型金氧半導體電晶體21〇以及Μ 體電晶體220，此介電層23〇具有第一拉伸應力。^声 230，材質例如是碳切、氮切或其他適當之材料。】 I ==^的形成方法例如是電漿增強魏學氣相沈積 氣的比例等製程參數，製造出拉伸應力約 2.5GPa之間的氮化石夕膜。 心丨於0.5〜 声（ί二ft夕膜的形成更可以是在沈積—層氮化石夕臈 7行熱處理步驟，以控制其拉伸應力約 疋I Λ 之間。其中，熱處理步驟例如是_ 大峰回火（spikeanneal)、紫外線供烤（UVcudng)、㊆ ^：^r：amanneaI)"^ 異參照圖2C，於基底200上形成光阻層·， 暴路出Ph乳半導體電晶體210上之介電層23〇。光阻 層240例如是正光阻，其例如是以旋轉塗佈的方式在介㊉ 層230上形成-層光阻材料層（未圖示），再利用】 影製程圖案化光阻材料層，形成光 "' ' 繼而，請參照㈣，以光阻層24^幕，對ρ型金 12 I2481Mwf.d〇〇/g 氧半導體電晶體210上之介電層230進行一離子植入製程 250。離子植入製程250所植入之摻質例如是矽（s〇原子、 氬（Ar)原子或氙（xe)原子。另外，也可以植入鍺（G〇 ^子為摻質。植入鍺（Ge)原子的方式例如是控制植入能 量約在50〜200keV，植入劑量約為1χ1〇13〜1χ1〇16原子/平 方公分來進行離子植入。 然後，請參照圓2Ε，Ρ型金氧半導體電晶體上之介電 層230在經過離子植入製程25〇之後，其拉伸應力將被降 接近GGPa’成為具有第二㈣應力的介電層23〇，。 ，、中’介電層23〇’之第二拉伸應力遠小於介電層挪之 繼？ ’移除光阻層240 ’移除的方法例如是 々，'式光阻或乾式去光阻的方式來進行。 由上述製造方法所得之半導體元件，如圖2 …结構與前-實麵之不同在於··更包括 ^ 225設置於Ρ型金氧半導 、’蜀夕化物層 體雷日卿990 μΙΓ 以及Ν型金氧半導 曰日月丑0之源極區、汲極區與閘極之表面。 上述貫施例之製造方法，於ρ型 以及Ν型金氧半導體電晶體2=:體10 對Ρ型金氧半導體電晶體21〇上之介，之後， 入萝鋥250，卜卜古、η %層23〇進行離子植 衣私250’此方法之步驟簡單，製程相 效降低Ρ型金氧半導體電晶體2Η)上介電;^可有 力，避免因為具有拉伸應力介電層现“=伸應 型金氧半導體電晶體21〇電_ ^成，而導致Ρ 層230如為氮化石夕膜層，;：开^=，的問題。且介電 ，、形成於金屬矽化物層22s之上 13 方作為形成接觸窗開口時之崎終止層（C。祕Etch st〇p =taye〇之用，由於此膜層之應力影響，亦有提升載 子遷移率的效果。 入/虹所述，本發日胳p熟氧半物電晶體以及N型 至乳+導體電晶體上形成具拉伸應力之介電層之後，再對 ^型金氧半導體電晶體上之介電層進行離子植入製程。豆 二=單，且可以降低P型金氧半導體電晶體上介電層： =應力’進而減少P型金氧半導體電晶體電洞遷移率的 衣減。本發明所提出之元件結構，於提升n型金氧 電:遷移率的同時’尚得以減少P型金氧半導體 =曰曰Μ洞遷移率的衰減’而達到提高元件運作速度 果0 3本發明已以較佳實施例揭露如上，然其並非用以 二2丄任何熟習此技藝者，在不脫離本發明之精神 ^巳圍内，^可作些許之更軸潤飾，因此本發明 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ' 、，圖1Α至圖1F所繪示為依照本發明一較佳實施例之一 種半導體元件之製造流程剖面圖 圖2A至圖2E所繪示為依照本發明另 一種半導體元件之製造流程剖面圖。 【主要元件符號說明】 1⑻、200 :基底 102、202 ··隔離結構 ‘較佳實施例之 I248144w,doc/g 110、210 : P型金氧半導體電晶體 120、220 : N型金氧半導體電晶體 130、130’、230、230’ ：介電層 140、240 :光阻層 150、250 :離子植入製程 225 :金屬矽化物層 212、222 :閘極 214a、224a :源極區 214b、224b · >及極區I2481i_/g Electrical layer i3〇' is set in p-type MOS transistor 11〇±, layer no is placed on N-type MOS transistor 12〇, bean medium = n-type MOS transistor 12G The stretching of the upper dielectric layer (10) is applied to the dielectric layer i3G located on the p-type MOS transistor UG, and the force 'and the dielectric layer 13' is, for example, doped with germanium, hard, After the argon or gas is replaced, the manufacturing method of the above embodiment is performed on the dielectric layer 11 of the 1> type oxynitride transistor 11 〇 and the N-type MOS transistor 12 ,, the p-type MOS transistor is formed. The dielectric layer l3G on the 11G is subjected to the ion implantation process ISO. The steps of the method are simple, the process is relatively easy, and the dielectric layer (10) on the P-type MOS transistor 11G can be effectively reduced, and the stretching should be 1 because of pulling The formation of the tensile stress dielectric layer i3G causes the problem of the metal oxide semiconductor crystal 11G hole migration. 2A to 2E are cross-sectional views showing a manufacturing process of a semiconductor device in accordance with another preferred embodiment of the present invention. Referring to FIG. 2A, the method first provides a substrate 2, and the substrate 2 is at least = a p-type MOS transistor 2ig and an N-type oxy-semiconductor transistor 220 have been formed. The method for forming a p-type MOS transistor 21 〇 ^ N type MOS transistor 22 is well known in the art, and will not be described herein. The two transistors can be broadcasted by an isolation structure as a partition. The isolation structure 2〇2 is formed, for example, by a shallow trench isolation structure 4 process, a regional oxidation (L〇c〇s) process, or other suitable process. Further, the source region 214a, the 汲12481^4^/polar region 214b, and the surface of the interpole 212 of the P-type MOS transistor 210 and the source region 224a and the drain region 224b of the n-type MOS transistor 220 And the gate 222: A metal telluride layer 225 has been formed. The shape of the metal telluride layer 225 is, for example, a self-aligned telluride process. Referring to FIG. 2B, a dielectric layer is formed on the substrate 2, covering at least the P-type MOS transistor 21A and the NMOS transistor 220. The dielectric layer 23 has the first pull. Extensive stress. ^ Sound 230, the material is, for example, carbon cut, nitrogen cut or other suitable material. The formation method of I ==^ is, for example, a process parameter such as the ratio of plasma enhanced Wei Xue vapor deposition gas, and a nitride nitride film having a tensile stress of about 2.5 GPa is produced. The heart palpitations are 0.5~ (the formation of the film can be performed in a 7-row heat treatment step of depositing a layer of nitride to control the tensile stress between about 疋I 。. The heat treatment step is, for example, _ Spiralanneal, ultraviolet-cured (UVcudng), seven ^:^r:amanneaI)"^Differently referring to FIG. 2C, a photoresist layer is formed on the substrate 200, and the phrasing is performed on the Ph-emulsion semiconductor transistor 210. The dielectric layer 23 is. The photoresist layer 240 is, for example, a positive photoresist. For example, a layer of photoresist layer (not shown) is formed on the dielectric layer 230 by spin coating, and the photoresist layer is patterned by a photo process. Light "' ' Then, please refer to (4), and perform an ion implantation process 250 on the dielectric layer 230 on the p-type gold 12 I2481Mwf.d〇〇/g oxygen semiconductor transistor 210 with a photoresist layer. The dopant implanted in the ion implantation process 250 is, for example, germanium (s〇 atom, argon (Ar) atom or xenon (xe) atom. Alternatively, it may be implanted with germanium (G〇^ is a dopant. Implantation锗) The (Ge) atom is, for example, controlled to implant energy at about 50 to 200 keV, and implanted at a dose of about 1χ1〇13~1χ1〇16 atoms/cm 2 for ion implantation. Then, please refer to circle 2Ε, Ρ type gold After the dielectric layer 230 on the oxy-semiconductor transistor is subjected to the ion implantation process, the tensile stress will be lowered to be close to GGPa' to become the second (four) stress dielectric layer 23 〇, . The second tensile stress of layer 23〇' is much smaller than that of the dielectric layer? The method of removing the photoresist layer 240' is, for example, 々, 'type photoresist or dry photoresist removal. The semiconductor device obtained by the above manufacturing method, as shown in FIG. 2, is different from the front-solid surface in that it is included in the Ρ-type gold-oxygen semiconductor, the 蜀 化物 层 layer body Lei Riqing 990 μΙΓ and the Ν type The surface of the source, bungee and gate of the gold-oxide semi-conducting 曰 丑 ugly 0. The method is based on the p-type and Ν-type MOS transistor 2=: body 10 on the Ρ-type MOS transistor 21〇, and then into the radish 250, the Bubgu, the η% layer 23〇 for the ion The process of planting 250' is simple, the process phase effect reduces the dielectric of the 金-type MOS transistor 2Η); ^ can be powerful, avoiding the dielectric layer with tensile stress The transistor 21 is electrically formed, resulting in the problem that the germanium layer 230 is a nitride layer, and the dielectric layer is formed on the metal germanide layer 22s as a contact. The opening of the window when the window is open (C. Secret Etch st〇p = taye〇, due to the stress of the film layer, there is also the effect of improving the mobility of the carrier. In / rainbow, the hair of the hair After forming a dielectric layer with tensile stress on the mature oxygen half-oxide and the N-type to the milk + conductor transistor, the ion implantation process is performed on the dielectric layer on the MOS transistor. Single, and can reduce the dielectric layer on the P-type MOS transistor: = stress 'and thus reduce P-type MOS semiconductor The reduction of the mobility of the body cavity. The element structure proposed by the present invention achieves the n-type MOS: mobility while reducing the attenuation of the P-type MOS semiconductor = cavity mobility. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the invention is defined by the scope of the appended claims. [FIG. 1A to FIG. 1F illustrates a semiconductor in accordance with a preferred embodiment of the present invention. Cross-sectional view of the manufacturing process of the components. Figs. 2A to 2E are cross-sectional views showing the manufacturing process of another semiconductor device in accordance with the present invention. [Description of main component symbols] 1(8), 200: substrate 102, 202 · Isolation structure 'I248144w of preferred embodiment, doc/g 110, 210: P-type MOS transistor 120, 220: N-type MOS semiconductor Crystals 130, 130', 230, 230': dielectric layers 140, 240: photoresist layers 150, 250: ion implantation process 225: metal telluride layers 212, 222: gates 214a, 224a: source regions 214b, 224b · > and polar regions
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