TWI278939B - A microelectronic device and method of fabricating the same - Google Patents

A microelectronic device and method of fabricating the same Download PDF

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Publication number
TWI278939B
TWI278939B TW094123526A TW94123526A TWI278939B TW I278939 B TWI278939 B TW I278939B TW 094123526 A TW094123526 A TW 094123526A TW 94123526 A TW94123526 A TW 94123526A TW I278939 B TWI278939 B TW I278939B
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Taiwan
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manufacturing
microelectronic device
substrate
stress layer
microelectronic
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TW094123526A
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Chinese (zh)
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TW200618120A (en
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Steve Ming Ting
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Taiwan Semiconductor Mfg
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Provided is a method for manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drain region. A strained layer may be formed over the substrate after introducing the dopants, and an annealing process may be performed after forming the strained layer.

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1278939 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件及其製造方法，特別是有關具有淺接 面之半導體元件及其製造方法。 【先前技術】 積體電路係利用製程方法在半導體基底上形成一個或是多個元件(例如 電路元件）。隨著製程及材料的演進，半導體元件持續的縮小其尺寸。舉例 來說，現行的半導體元件其線寬已達90nm或是更小。然而，半導體元件尺 寸的縮小會遇到許多需克服的問題。 目别，在積體電路尺寸縮小的技術上，已應用一種超淺接面之金氧半 琢效電sa體MOSFET ’以減少短通道效應。然而，接面厚度的減少會導致 南阻抗及低驅動電流。目此，f要有肋克社賴問題之積體電路元件 及製造方法。 【發明内容】 因此’根據上述之問題，本發明提供一種微電子元件及其製造方法， -匕括應力層’以解決習知技術接面厚度的減少導致高阻抗及低驅動電 流之問題。 為達成上述目的，本發明提供—種微f子元件之製造方法，其微電子 元件包括具有離面之轉縣底。首先，將摻_摻人基叙形成源極 區域和;及極區域。其後，形成應力層於部分之源極區域和沒極區域上。後 續’對基底進行回火製程。 為達成上述目的，本發賴供-種微電子元件之製造方法。首先，提 供-半導縣底，並進行離子雜步歡在轉體基底巾形赫雜區。接 下來在換雜區上形成應力層以增加半導體基底之固溶性5½續，進行回 ........ -- .,. 0503-A30932TWF(5.0) 5 1278939 火製程。 _ 為達成上述目的’本發明提供一種微電子元件，包括··基底、具有主 動摻雜濃度之摻雜區，其中主動摻雜濃度大體上大於或等於基底中摻雜物 之平衡溶解極限(ESL)及應力層，其具有最佳化之應力以增加基底中摻雜物 一 之平衡溶解極限(ESL)。 ' 【實施方式】 明參照第1圖，及後續的第2-7圖，本發明在一實施例中提供一種用 • 以使用應力達成超淺接面之微電子元件方法100。一般來說，兩個參數(接 面厚度和片電阻)交互平衡以達到預期的功能。為同時減少接面厚度和片電 阻，需增加摻雜濃度以達到較高之載子濃度。上述之方法10()可以用以解 決摻雜物固態溶解度所產生的問題。 第2-7圖係提供本實施例之微電子元件200的剖面圖(製程之中間步 驟）。此微電子元件200包括一基底210，及複數個絕緣區以定義出主動區 域(未繪示）。一閘極220形成在基底210上。此基底可包括複數個此閘極或 其它的結構特徵。此基底210可以為一半導體基底，例如單晶矽、多晶矽、 泰非晶矽、鍺和鑽石，或是複合半導體，例如碳化矽、砷化鎵，或合金半導 體，例如SiGe、GaAsP、AlMAs、AlGaAs、GalnP或是上述任意的組合。 ‘此外，上述之基底21〇亦可以為一本徵半導體，例如本徵石夕或包含蟲晶石夕 , 層之本徵石夕。 在半_基底和其上之雜構，例如雙井結構dual_well或是三井結構 triple-well㈤’可以形成有一絕緣層。在本發明之一實施例中，此絕緣層可 以為埋藏氧化層BOX，例如以佈植氧化技術SIM〇x，或是晶圓接合技術 形成的氧化層。此絕緣層亦可以是藉由熱氧化法、原子層沉積法、化 學氣相沉積法CTO、物理氣相沉積法PVD或其它製程所形成。此外，亦可 以採用化學顧研磨法以使上狀絕緣層_歡之厚度。另外，絕緣層 6 0503-A30932TWF(5.〇) 1278939 -可以例如為氧化物、氧化石夕、氮化石夕、氮氧化石夕、低介電材料、空氣間隙、 或上^之組合。絕緣層並不以本發明實施例所揭示為限定。 、隔、層了以採用區域氧化法L〇c〇s或是淺溝槽絕緣技術奶形成。區 -、氧化法可以為使關形罩幕層的氧化法。淺溝槽絕緣技術可以藉由钱刻 • P基底形成—溝槽，且之後在溝射填人絕緣材料，例如氧娜、氮化石夕、 氮氧化石夕、低介電材料、空氣間隙或上述之組合。此溝槽可以是具有多層 之結構，例如襯塾氧化層結合其上填入溝槽之氮化石夕。在一實施例中，上 STI結構可以採用以下的製程形成··首先，成長一墊氧化層，並形成 Φ 、CVD氮化層。其後，使用光阻和罩幕圖形化STI開口，在基底钱刻出 溝槽。接下來，選雜的成長—熱襯墊氧化層以改進溝槽之介面。後續， 在溝槽中填人CVD氧化物。最後，採用化學機械研磨法研磨及移除氮化物 以形成STI結構。 閘極220可更包括-閘電極222和—間極介電層224。此閘極介電層 224可以包括氧化梦、氮氧化石夕或是高介電材料(例如氧化铪、梦化給、石夕 氧化給、石夕氮氧化給、氧化錯、氧化銘、給氧銘合金、氧化石夕、五氧化纽 或上述之組合）。間極介電層224可以藉由熱氧化法、原子層沉積法助、 肇化學氣相沉積法CVD、物理氣相沉積法PVD所形成。酿介電層224亦可 以多層結構，例如以熱氧化法所形成之氧切為第—層，及採用高介電材 “料為第二層。此外，此閘極介電層224可以進行將熱氧化層氮化，或是回 - 火堆4之閘極介電層的步驟。 閘電極222可以經由-個或是多個低電阻之接面連接其上之内連線社 構。此閘電極222可以包括導電材料和多層結構。此閘電極222可以包括 梦、錯、其它導電材料或是上述之結合。舉例來說，導電材料可以包括摻 雜多晶石夕、多晶石夕錯、金屬、金屬石夕化物、金屬氮化物、金屬氧化物、夺 米碳管或上狀組合。金制可以包括銅m合金m、 鎳、始和銦。金射化物可以包括魏銅、概鶴、狐銘、雜麵、石夕 0503-A30932TWF(5.0) 1278939 -化鈦、石夕化组、石夕化鎳、石夕化始、石夕化翻或石夕化斜。閉電極瓜可以藉由 化學氣相沉積法CVD、物理氣相沉積法PVD、石夕化、f鍛或是原子層氣相 沉積法ALD所形成。其它的製程，例如多晶石夕之佈植、石夕化物之回火亦可 以應用在製造’之製程。此閘極可以是—雙結構，例如具有不同間極高 度之PM〇S及NMOS，或是PMOS和NMOS採用不同之材質。 請參照步驟110(圖1)和圖示3，基底21〇可以摻入雜質，其可以採用 '離子佈值的方法進行，以形成摻雜區咖、240分別作為源極和沒極。在一 實施例中，摻雜區230、240係分別為源極和汲極之輕摻雜區Ldd。 齡在一實施例中，摻雜區的厚度(例如，源極23〇和沒極24〇)可以是非常 的薄。舉例來說’摻雜區的厚度可以小於5〇〇埃。摻雜物的濃度可以是 lxl02()at〇ms/Cm3或是更高，且摻雜劑量可以介於5xl〇14at〇mg/cm2至 5xl015atoms/cm2 ° 在一實施例中，離子佈值可以採用電漿源離子佈值psiI，其可以稱為 電漿源離子浸入(plasma source ion i_ersion)。PSII可以包括將電極層暴露 在電漿源之製程，且將基底施加偏壓。進行PSII的製程可以包括單一或是 批次的晶圓反應器，其中直流或是交流電壓係施加在基底上。psn反應器 ,可以包括介於O.OlmTorr〜lOOOTorr的製程壓力。基底之溫度則可以介於 150〇C〜1100。〇高密度電漿可以藉由微波電子迴旋加速共振電漿ecr、 螺旋電漿(heliconplasma)、感應電偶電聚或是其它之高密度電漿源產生。電 漿則可以包括Ar、Η、N、Xe、0、As、B2H6、GeH4、P或其它雜質源。舉 例來說，螺旋電漿可以應用介於200W〜2500W之交流功率。施加電壓則可 以介於±200V-±5000V。 請參照步驟120和第4圖，一或是多個應力層25〇可以在雜質摻入基 底之後形成在基底上。此應力層250可以為一含氮層(例如氮化發、氧化梦、 氮氧化梦或是其它之摻雜矽）。此外，其亦可以包括氧祀贫或是碳化梦。在 一實例中，應力層250可以是一多層結構，例如一薄之氧化石夕層和一厚之 0503-A30932TWF(5.0) 8 1278939 ^層:糊力㈣之方㈣包括CVD、pyD、勘献熱氧化 法⑽成石夕} ’但本發明並不限於此。應力層25〇之厚度可以介於約 5nm〜·nm。應力層25〇的應力财时於2肌—2哪。 上述之應力層25G可以藉由例如沉積方法、沉積溫度、材料、結構和 調整應力層250之應力，以增加基底中雜質之固溶特性(例如瓣 2在魏底中之_性卜在其它實施例中，可以在形成應力層25〇之後 實施離子佈植(步驟110)。 在步驟130中’可在形成應力層25〇之後，於微電子元件挪上進行 鲁-蚊縣。此故餘_婦化及修復在離子佈植情產生之損壞。 上述之回火餘可吨括快速熱餘RTP、隨為餘卿、雷射回火 或是峰_火，_火溫度職定於回火製程。舉例來說，峰伽火之溫 度係"於1000 C〜11〇〇。〇，而固態蟲晶製程之溫度則約5〇〇〇c或是更低。 、當微電子播献指小錢接面或是域接面，謂要冑之換雜濃 度乂避免接面片電阻之減少。瞬間擴散效應enhaneed 則限繼面深度’以避免短通道效應。本發明實施例揭露可採職力層25〇 以增加基底之固溶性，減少回火製程之擴散，且改進淺接面之片電阻。舉 _例來說’硼佈植可以產生石夕裂縫及石夕空隙，以增加雜質之擴散。石夕裂缝可 以藉由壓應力層修補’而發空缺可以藉由張應力層修補。因為蝴瞬間擴散 效應TED係藉由石夕裂縫進行’應用一壓應力層至源極/沒極可以減少擴散和 -接面厚度。 請參照步驟140和第5'6圖，可移除部份應力層25〇，或將其完全移 除。在-實施例中，可藉由乾蝴移除部份應力層25G，以在.22〇兩側 形成間隙壁260、270，如第5圖所示。在另一實施例中，可以藉由濕侧 凡全移除應力層25G ’如第6圖所示。其後，可進行例如形成間隙壁、離子 佈植以形成深源極/汲極之製程。 本實施例之揭錢不限定於具有MQS 爾構之微電子元件 〇503-A30932TWF(5.0) 9 1278939 -200 ’且其可以包括任何含有高摻雜區之積體電路。舉例來說，在其它實施 4中此祕電子元件2〇〇可以包括可消除可程式唯讀記憶體聊傷晶胞、 ，子抹除絲敎舰EEPR〇M驗、雜賴記鋪SRAM 4胞、動態 隨機記憶體DRAM晶胞、單電子電驗或其它微電子元件。此微電子 70件200之幾何特徵可以介於5埃〜1·埃。此微電子元件2〇〇可以包括翅 片型場效應電晶體(^印。當然，本發明之揭露可包括任何型態之電晶 體，例如單閘極電晶體、雙閘極電晶體、三間極電晶體或是多閘極電晶體， 且其可以使用在許多不同之應用上，包括感應晶胞、記憶體晶胞、邏輯晶 φ 胞或其它。 第7圖係為本發明另一實施例之剖面圖。請參照第7圖，微電子元件 包括形成在半導體晶圓之第一型元件6〇〇和第二型元件7〇〇，其中第一型係 不同於第二型。舉例來說，第一型元件6〇〇可以是顺聊，而第二型元件 700可以是PMOS電晶體。 此NMOS電晶體600可以包括p型摻雜基底61〇。閘極62〇可以形成 在基底610上，其中閘極620尚包括閘電極622和閘極絕緣層泣4。源極 630和汲極640可以藉由離子佈植摻雜仏型摻雜物，例如磷或砷，形成。應 •力層650可以形成在包括源極63〇和汲極640之基底上。形成應力層650 的參數及條件可以包括沉積方法、沉積溫度、薄膜材料、薄膜結構、薄膜 厚度或其它參數。其可以用以調整應力層65〇之應力以增加基底中n_型摻 一 雜物之固溶限制。 類似於上，PMOS電晶體700可以包括N型摻雜基底710。閘極720 可以形成在基底710上，其中閘極72〇尚包括閘電極722和閘極絕緣層724。 源極730和没極740可以藉由離子佈植摻雜型掺雜物(例如硼)形成。應力 層750可以形成在包括源極730和汲極740之基底上。形成應力層750的 參數及條件可以包括沉積方法、沉積溫度、薄膜材料、薄膜結構、薄膜厚 度或其它參數。其可以用以調整應力層750之應力以增加基底中p-型摻雜 0503-A30932TWF(5.0) 10 1278939 .物之固溶限制。應力層650和應力層750所調整之應力可以不同，而形成 NMOS電晶體600及/或PMOS電晶體700之相關製程和材料可以實質相似 於先前所描述之微電子元件200。 第8圖係為本發明一實施例之微電子電路8〇〇之剖面圖。微電子電路 800包括複數個微電子元件200，600和7〇〇，其中該些微電子元件2〇〇，6〇〇 和700可以是大約相似。 ’ 積體電路咖可以包括-半導體基底，例如梦基底，其更包括p型摻 雜區802和N塑掺雜區804，兩者係由一隔絕結構8〇6分開。隔絕結構8〇6 #可以是一區域場氧化層L0C0S或是淺溝槽絕緣結構STI。一 NMOS電晶 體810係形成在P型摻雜區802，且一 PM〇s電晶體82〇係形成在n型摻 雜區SO^NMOS電晶體81〇可以包括閘極812、摻雜之源極814和汲 極816。源極814和汲極816之厚度可低於300埃。N型摻雜物可包括磷或 坤，且因為受應力的基底在回火的製程中可增加平衡溶解極限聰 solubility limit，ESL)，摻雜物的濃度可高於在無應力基底^ N型摻雜物之 平娜解極限。NMOS電晶體可更包括一間隙壁818，其可以為經移除部份 之應力層。PMOS電晶體820可包括閘極822、源極824、p型之沒極826。 _源極824何極826之厚度可低於300埃。p型摻雜物可包括♦且因為受 應力的基底如火㈣財可增加平娜解極限㈣綱啦⑽臟办 limit，ESL)，摻雜物的濃度可高於在無應力基底之p鮮雜物之平衡溶解 .極限。NMOS f晶體可更包括一間隙壁828，其可以為經移除部份之應力 層。間隙壁818和間隙壁828可包括不同之材料，因此兩者具有不同之應 力型態(張應力或是廢應力）。間隙壁818和828可分別具有原應力層所遺留 下來的應力。上述之卩猶壁結射包括氫财、氧财、氮氧化梦、碳化 石夕或其組合，且其可以為一多層結構。 此積體電路兀件800更包括一或是多層位於微電子元件81〇、腿上之 、’’邑緣層830、84〇。第-絕緣層83〇(其本身可包括多層絕緣層)可藉由平坦化 〇503-A30932TWF(5.0) 11 1278939 以達雖於《子元件wo、82G上之讀上平坦之表面。在—實施例中， 元件810包括一 NMOS電晶體且元件82〇包括_ pM〇s電晶體。 、此積體電路元件_亦可包括蚊内連線結構咖⑽如傳統之介層插 塞或接觸窗）’和水平内連線結構_。内連線結構85〇可以延伸穿過—或 是多層絕緣層⑽、840 ’且内連線_可沿著_或是多層絕緣層83〇、_ 延伸。在-實施例中’内連線結構850、86〇可以具有雙鑲嵌結構，且其形 成之方式包括藉由侧或其它方式來圖案化絕緣層83G、84()及依序填入導 電材料(例如鋁、鎢、鈕、氮化鈕、鈦、氮化鈦、鋼或始）。 • 本發明並不限於M0S電晶體。其可以應職具初參雜區之半導體基底 上’或是其它應用。例如，掺雜區源極、摻雜多晶梦閘極、汲極、捧雜多 晶矽電阻、MOS電曰曰曰體、CMOS電晶體、雙載子電晶體、高功率電晶體或 其它之摻雜區，其中摻雜物之溶解度可增加以達成高摻雜濃度。 在形成應力層之後，可進行一或是多個回火製程，以活化或是修復基 底在經由離子佈植破壞後之晶格結構。上述之回火製程可以包括快速熱製 程RTP、固態磊晶製程SPE、雷射回火或是峰值回火。因為平衡溶解極限 (equilibriumsolubilitylimit)可以藉由應力層增加，在回火之後基底可以具有 _ 高於ESL之摻雜濃度，且其高於不包含應力層之基底。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與 • 潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係顯示本發明微電子元件之一實施例之流程圖。 第2-7圖係提供本發明微電子元件之一實施例方法之示意圖。 第8圖係為本發明之一實施例之微電子電路之剖面圖。 〇503-A30932TWF(5.0) 12 1278939 【主要元件符號說明】 200〜微電子元件； 222〜閘電極； 230〜源極； 250〜應力層； 600〜NMOS電晶體； 620〜閘極； 624〜閘極絕緣層； 640〜沒極； 700〜PMOS電晶體； 720〜閘極； 724〜閘極絕緣層； 740〜汲極； 802〜P型掺雜區； 806〜隔絕結構； 820〜PMOS電晶體； 814〜源極； 818〜間隙壁； 824〜源極； 828〜間隙壁； 850〜垂直内連線結構； 220〜閘極； 224〜閘極介電層； 240〜汲極； 260、270〜間隙壁； 610〜P型摻雜基底； 622〜閘電極； 630〜源極； 650〜應力層； 710〜N型摻雜基底； 722〜閘電極； 730〜源極； 750〜應力層； 804〜N型摻雜區； 810〜NMOS電晶體； 812〜閘極； 816〜汲極； 822〜閘極； 826〜P型之汲極； 830、840〜絕緣層； 860〜水平内連線結構 0503-A30932TWF(5.0) 13BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a shallow junction and a method of fabricating the same. [Prior Art] An integrated circuit uses a process method to form one or more components (e.g., circuit components) on a semiconductor substrate. As processes and materials evolve, semiconductor components continue to shrink in size. For example, current semiconductor components have line widths of up to 90 nm or less. However, the reduction in the size of semiconductor components encounters many problems to be overcome. In view of the technology in which the size of the integrated circuit is reduced, an ultra-shallow junction of a gold-oxide half-effect sa-type MOSFET ’ has been applied to reduce the short-channel effect. However, a reduction in junction thickness results in a south impedance and a low drive current. In view of this, f must have the integrated circuit components and manufacturing methods of the problem. SUMMARY OF THE INVENTION Therefore, in accordance with the above problems, the present invention provides a microelectronic component and a method of fabricating the same, including a stressor layer to solve the problem of high impedance and low drive current caused by a reduction in the thickness of the junction of the prior art. In order to achieve the above object, the present invention provides a method of fabricating a micro-f sub-element, the microelectronic element comprising an off-counter. First, the doped-incorporated group forms the source region and the polar region. Thereafter, a stress layer is formed on a portion of the source region and the gate region. Subsequent tempering process on the substrate. In order to achieve the above object, the present invention provides a method of manufacturing a microelectronic component. First, provide the bottom of the semi-conducting county, and carry out the ion-mixed step in the base of the swivel base. Next, a stress layer is formed on the impurity-changing region to increase the solid solution property of the semiconductor substrate. The process is continued........-., 0503-A30932TWF(5.0) 5 1278939 Fire process. In order to achieve the above object, the present invention provides a microelectronic component comprising: a substrate, a doped region having an active doping concentration, wherein the active doping concentration is substantially greater than or equal to the equilibrium solubility limit of the dopant in the substrate (ESL) And a stress layer having an optimized stress to increase the equilibrium solubility limit (ESL) of the dopant in the substrate. [Embodiment] Referring to Fig. 1, and subsequent Figs. 2-7, the present invention provides, in one embodiment, a microelectronic component method 100 for achieving an ultra-shallow junction using stress. In general, the two parameters (junction thickness and sheet resistance) are balanced to achieve the desired function. In order to simultaneously reduce the junction thickness and the sheet resistance, it is necessary to increase the doping concentration to achieve a higher carrier concentration. The above method 10() can be used to solve the problems caused by the solid solubility of the dopant. Figures 2-7 are cross-sectional views (intermediate steps of the process) of the microelectronic device 200 of the present embodiment. The microelectronic component 200 includes a substrate 210 and a plurality of insulating regions to define an active region (not shown). A gate 220 is formed on the substrate 210. The substrate can include a plurality of such gates or other structural features. The substrate 210 may be a semiconductor substrate such as single crystal germanium, polycrystalline germanium, germanium amorphous germanium, germanium and diamond, or a composite semiconductor such as tantalum carbide, gallium arsenide, or an alloy semiconductor such as SiGe, GaAsP, AlMAs, AlGaAs. , GalnP or any combination of the above. ‘In addition, the above-mentioned substrate 21〇 may also be an intrinsic semiconductor, such as the intrinsic stone eve or the inclusion of the sarcophagus, the intrinsic stone eve of the layer. The insulating layer may be formed on the semi-substrate and the heterostructure thereon, such as a dual well structure dual_well or a triple well structure triple-well (five). In one embodiment of the invention, the insulating layer can be a buried oxide layer BOX, such as an oxide layer formed by implantation oxidation technology SIM〇x, or wafer bonding technology. The insulating layer may also be formed by thermal oxidation, atomic layer deposition, chemical vapor deposition CTO, physical vapor deposition PVD or other processes. In addition, it is also possible to use a chemical grinding method to make the thickness of the upper insulating layer. Further, the insulating layer 6 0503-A30932TWF (5. 〇) 1278939 - may be, for example, a combination of an oxide, a oxidized stone, a nitride, a nitrous oxide, a low dielectric material, an air gap, or a combination thereof. The insulating layer is not limited by the disclosure of the embodiments of the present invention. The partitions and layers are formed by using the regional oxidation method L〇c〇s or shallow trench insulation technology. Zone - The oxidation process can be an oxidation process for the off-mask layer. The shallow trench insulation technique can be formed by the groove of the P-P substrate, and then implanted in the trench, such as oxyna, nitrite, nitrous oxide, low dielectric material, air gap or the above The combination. The trench may be of a multi-layered structure, such as a lining oxide layer in combination with a nitride nitride filled into the trench. In one embodiment, the upper STI structure can be formed by the following process: First, a pad oxide layer is grown, and a Φ, CVD nitride layer is formed. Thereafter, the STI opening is patterned using photoresist and mask, and the trench is engraved on the substrate. Next, a hybrid growth-hot pad oxide layer is selected to improve the trench interface. Subsequently, a CVD oxide is filled in the trench. Finally, the nitride is ground and removed by chemical mechanical polishing to form an STI structure. The gate 220 may further include a gate electrode 222 and an inter-electrode layer 224. The gate dielectric layer 224 may include oxidized dreams, nitrous oxide oxide or high dielectric materials (for example, cerium oxide, dreaming, cerium oxidation, shixi nitrogen oxidation, oxidation, oxidation, oxygen supply). Ming alloy, oxidized stone eve, pentoxide or a combination of the above). The inter-electrode dielectric layer 224 can be formed by thermal oxidation, atomic layer deposition assisted, rhodium chemical vapor deposition (CVD), or physical vapor deposition (PVD). The brewing dielectric layer 224 can also have a multi-layer structure, for example, an oxygen cut formed by thermal oxidation as a first layer, and a high dielectric material as a second layer. Further, the gate dielectric layer 224 can be performed. The thermal oxide layer is nitrided, or the step of returning to the gate dielectric layer of the fire stack 4. The gate electrode 222 can be connected to the interconnect structure via one or more low resistance junctions. The electrode 222 may include a conductive material and a multilayer structure. The gate electrode 222 may include a dream, a fault, other conductive materials, or a combination thereof. For example, the conductive material may include doped polycrystalline lithi, polycrystalline, Metal, metal cerium, metal nitride, metal oxide, carbon nanotube or super combination. Gold may include copper m alloy m, nickel, beginning and indium. The gold alloy may include Wei copper, crane, Fox Ming, Miscellaneous, Shi Xi 0503-A30932TWF(5.0) 1278939 - Titanium, Shi Xihua, Shi Xihua Nickel, Shi Xihua, Shi Xihua or Shi Xihua. Chemical vapor deposition CVD, physical vapor deposition PVD, Shi Xihua, f forging or atom The vapor deposition method is formed by ALD. Other processes, such as polycrystalline lithography and tempering of the lithograph, can also be applied to the manufacturing process. The gate can be a double structure, for example, having different interpoles. The height of PM〇S and NMOS, or PMOS and NMOS are different materials. Please refer to step 110 (Fig. 1) and Figure 3, the substrate 21〇 can be doped with impurities, which can be carried out by the method of 'ion cloth value. To form a doped region, 240 as a source and a dipole, respectively. In one embodiment, the doped regions 230, 240 are respectively a source and a drain-light doped region Ldd. In an embodiment, The thickness of the doped region (eg, source 23 〇 and 没 24 〇) can be very thin. For example, the thickness of the doped region can be less than 5 〇〇. The concentration of the dopant can be lxl02() At〇ms/Cm3 or higher, and the doping amount may be from 5xl〇14at〇mg/cm2 to 5xl015atoms/cm2 °. In one embodiment, the ion cloth value may be a plasma source ion cloth value psiI, which may It is called plasma source ion i_ersion. PSII can include exposing the electrode layer to The process of the slurry source and biasing the substrate. The process of performing the PSII may include a single or batch wafer reactor, wherein a direct current or alternating voltage is applied to the substrate. The psn reactor may include between The process pressure of OlmTorr~lOOOTorr. The temperature of the substrate can be between 150〇C and 1100. The high-density plasma can be accelerated by microwave electron cyclotron resonance plasma ecr, spiral plasma (heliconplasma), inductive galvanic coupler. Or other high-density plasma sources. The plasma may include Ar, Η, N, Xe, 0, As, B2H6, GeH4, P or other sources of impurities. For example, spiral plasma can be used with AC power between 200W and 2500W. The applied voltage can range from ±200V to ±5000V. Referring to steps 120 and 4, one or more stress layers 25A may be formed on the substrate after the impurities are incorporated into the substrate. The stressor layer 250 can be a nitrogen-containing layer (e.g., nitrided, oxidized, oxidized, or otherwise doped). In addition, it can also include oxygen depletion or carbonization dreams. In one example, the stressor layer 250 can be a multilayer structure, such as a thin oxidized stone layer and a thick 0503-A30932TWF (5.0) 8 1278939 ^ layer: paste force (four) square (four) including CVD, pyD, survey Thermistive oxidation method (10) is formed into a stone eve} but the invention is not limited thereto. The thickness of the stressor layer 25 can be between about 5 nm and about nm. The stress level of the stress layer 25〇 is 2 muscle-2. The stress layer 25G described above can increase the solid solution characteristics of the impurities in the substrate by, for example, a deposition method, a deposition temperature, a material, a structure, and a stress of the stress-regulating layer 250 (for example, the smear of the stalk 2 in the Wei dynasty in other implementations) In the example, the ion implantation may be performed after the stress layer 25 is formed (step 110). In step 130, after the stress layer 25 is formed, the micro-electronic component may be moved to the Lu-Mosquito County. The damage caused by the maternalization and repair in the ion cloth. The above tempering can include the rapid thermal RTP, followed by Yu Qing, laser tempering or peak _ fire, _ fire temperature is set in the tempering process For example, the temperature of the peak gamma fire is "at 1000 C~11 〇〇. 〇, and the temperature of the solid worm crystal process is about 5 〇〇〇 c or lower. When the microelectronics broadcast refers to small money. The junction or the domain junction is said to be a mixed concentration, which avoids the reduction of the junction resistance. The instantaneous diffusion effect enhances the secondary depth to avoid the short channel effect. The embodiment of the invention discloses the exploitable layer 25〇 to increase the solid solubility of the substrate and reduce the diffusion of the tempering process, and Into the shallow junction of the sheet resistance. For example, 'boron implants can produce Shishi cracks and Shishi voids to increase the diffusion of impurities. Shishi cracks can be repaired by compressive stress layer' and vacancies can be used The tensile stress layer is repaired. Because the instantaneous diffusion effect of the TED system is performed by using the Shihe crack, the application of a compressive stress layer to the source/no-pole can reduce the diffusion and the junction thickness. Please refer to steps 140 and 5'6. The partial stress layer 25 can be removed or completely removed. In the embodiment, the partial stress layer 25G can be removed by dry butterfly to form spacers 260, 270 on both sides of the .22 crucible. As shown in Fig. 5. In another embodiment, the stress layer 25G' can be completely removed by the wet side as shown in Fig. 6. Thereafter, for example, spacers can be formed, and ion implantation can be performed to form a deep The source/drain process is not limited to the microelectronic component 〇503-A30932TWF(5.0) 9 1278939 -200' having MQS structure and it may include any integrated body containing a highly doped region. Circuitry. For example, in other implementations 4, the secret electronic component 2 can include an erasable Programmable read-only memory for cell, EMPR〇M test, miscellaneous SRAM 4 cell, dynamic random memory DRAM cell, single electron detector or other microelectronic components. The geometrical features of the microelectronics 70 200 may be between 5 angstroms and 1 angstrom. The microelectronic component 2 〇〇 may comprise a finned field effect transistor (of course, the disclosure of the invention may include any type A transistor, such as a single-gate transistor, a double-gate transistor, a three-pole transistor, or a multi-gate transistor, and which can be used in many different applications, including sensing cells, memory cells, logic The crystal φ cell or the like. Fig. 7 is a cross-sectional view showing another embodiment of the present invention. Referring to Fig. 7, the microelectronic component includes a first type element 6 〇〇 and a second type element 7 形成 formed on a semiconductor wafer, wherein the first type is different from the second type. For example, the first type element 6A can be a slap, and the second type element 700 can be a PMOS transistor. This NMOS transistor 600 can include a p-type doped substrate 61A. A gate 62A may be formed on the substrate 610, wherein the gate 620 further includes a gate electrode 622 and a gate insulating layer. Source 630 and drain 640 may be formed by ion implantation of a cerium-type dopant such as phosphorus or arsenic. The force layer 650 may be formed on a substrate including the source 63 and the drain 640. The parameters and conditions for forming the stressor layer 650 may include deposition methods, deposition temperatures, film materials, film structures, film thicknesses, or other parameters. It can be used to adjust the stress of the stressor layer 65 to increase the solid solution limit of the n-type dopant in the substrate. Similar to the above, the PMOS transistor 700 can include an N-type doped substrate 710. The gate 720 may be formed on the substrate 710, wherein the gate 72 further includes a gate electrode 722 and a gate insulating layer 724. Source 730 and dipole 740 can be formed by ion implanting a dopant dopant such as boron. A stressor layer 750 can be formed on the substrate including the source 730 and the drain 740. The parameters and conditions for forming the stressor layer 750 may include deposition methods, deposition temperatures, film materials, film structures, film thicknesses, or other parameters. It can be used to adjust the stress of the stressor layer 750 to increase the solid solution limit of the p-type doping 0503-A30932TWF(5.0) 10 1278939 in the substrate. The stresses tuned by the stressor layer 650 and the stressor layer 750 can be different, and the associated processes and materials for forming the NMOS transistor 600 and/or the PMOS transistor 700 can be substantially similar to the microelectronic component 200 previously described. Figure 8 is a cross-sectional view of a microelectronic circuit 8A according to an embodiment of the present invention. Microelectronic circuit 800 includes a plurality of microelectronic components 200, 600 and 7 〇〇, wherein the microelectronic components 2 〇〇, 6 〇〇 and 700 can be approximately similar. The integrated circuit can include a semiconductor substrate, such as a dream substrate, which further includes a p-type doped region 802 and an N-plastic doped region 804, both separated by an isolation structure 8〇6. The isolation structure 8〇6 # can be a regional field oxide layer L0C0S or a shallow trench isolation structure STI. An NMOS transistor 810 is formed in the P-type doping region 802, and a PM〇s transistor 82 is formed in the n-type doping region SO^ NMOS transistor 81, which may include a gate 812 and a doped source. 814 and bungee 816. Source 814 and drain 816 may have a thickness of less than 300 angstroms. The N-type dopant may include phosphorus or Kun, and because the stressed substrate may increase the equilibrium solubility limit in the tempering process, the concentration of the dopant may be higher than that in the unstressed substrate. The limit of the dopant of the dopant. The NMOS transistor can further include a spacer 818, which can be a stressed portion of the removed portion. The PMOS transistor 820 can include a gate 822, a source 824, and a p-type immersion 826. The thickness of the source 824 He 826 can be less than 300 angstroms. The p-type dopant may include ♦ and because the stressed substrate such as fire (four) can increase the flat-solution limit (four), (10) dirty limit, ESL), the concentration of the dopant can be higher than the unstressed substrate The balance of impurities is dissolved. Limit. The NMOS f crystal may further include a spacer 828 which may be a removed portion of the stressor layer. The spacers 818 and spacers 828 may comprise different materials such that the two have different stress patterns (tension or waste stress). The spacers 818 and 828 may each have a stress left by the original stress layer. The above-mentioned ruthenium walling includes hydrogen, oxygen, nitrogen oxide dream, carbon carbide or a combination thereof, and it may be a multi-layer structure. The integrated circuit component 800 further includes one or more layers of the microelectronic element 81, the legs, and the ''lasting layers 830, 84'. The first insulating layer 83 (which may itself include a plurality of insulating layers) can be planarized by 〇503-A30932TWF(5.0) 11 1278939 to achieve a flat surface on the sub-element wo, 82G. In an embodiment, component 810 includes an NMOS transistor and component 82A includes a _pM〇s transistor. The integrated circuit component _ may also include a mosquito interconnect structure (10) such as a conventional via plug or contact window) and a horizontal interconnect structure. The interconnect structure 85A may extend through - or a plurality of insulating layers (10), 840' and the interconnects may extend along the _ or the plurality of insulating layers 83, _. In the embodiment, the interconnect structures 850, 86A may have a dual damascene structure and are formed by patterning the insulating layers 83G, 84() sidewise or otherwise and sequentially filling the conductive material ( For example, aluminum, tungsten, button, nitride button, titanium, titanium nitride, steel or the beginning). • The invention is not limited to MOS transistors. It can be used on the semiconductor substrate of the initial doping area or other applications. For example, doped region source, doped polycrystalline dream gate, drain, doped polysilicon resistor, MOS transistor, CMOS transistor, bipolar transistor, high power transistor or other doping The region in which the solubility of the dopant can be increased to achieve a high doping concentration. After the stressor layer is formed, one or more tempering processes can be performed to activate or repair the lattice structure of the substrate after destruction by ion implantation. The above tempering process may include rapid thermal process RTP, solid state epitaxial process SPE, laser tempering or peak tempering. Since the equilibrium solubility limit can be increased by the stress layer, the substrate can have a doping concentration higher than ESL after tempering, and it is higher than the substrate not including the stress layer. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is obvious to those skilled in the art that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing an embodiment of a microelectronic component of the present invention. 2-7 are schematic views of a method of providing an embodiment of the microelectronic component of the present invention. Figure 8 is a cross-sectional view of a microelectronic circuit in accordance with one embodiment of the present invention. 〇503-A30932TWF(5.0) 12 1278939 [Main component symbol description] 200~microelectronic component; 222~gate electrode; 230~source; 250~stress layer; 600~NMOS transistor; 620~gate; 624~gate Very insulating layer; 640~ immersed; 700~PMOS transistor; 720~ gate; 724~ gate insulating layer; 740~dip; 802~P type doped region; 806~isolated structure; 820~PMOS transistor ; 814 ~ source; 818 ~ spacer; 824 ~ source; 828 ~ spacer; 850 ~ vertical interconnect structure; 220 ~ gate; 224 ~ gate dielectric layer; 240 ~ bungee; 260, 270 ~ spacer; 610~P type doped substrate; 622~ gate electrode; 630~ source; 650~ stress layer; 710~N type doped substrate; 722~ gate electrode; 730~ source; 750~ stress layer; 804~N-doped region; 810~NMOS transistor; 812~gate; 816~dip; 822~gate; 826~P-type drain; 830,840~insulation; 860~horizontal interconnect Structure 0503-A30932TWF(5.0) 13

Claims (1)

1278939 第94123526號申請專利範圍修正本. 一"'一”〜〜期^5.11 13 十、申請專利範圍： 忙^丨月加修(更)馬本 1· 一種微電子元件之製造方法，其微電子元件包括一具有一淺接面之半 導體基底，該方法包括： 將摻雜物摻入一基底以形成一源極區域和一汲極區域； 形成應力層於部分之該源極區域和沒極Εΐ域上，其中該應力層直接 接觸該源極區域和該汲極區域；及 對該基底進行一回火製程。 2·如申請專利範圍第1項所述之微電子元件之製造方法，其中該微電子 元件包括金氧半場效電晶體。 3.如申請專利範圍第2項所述之微電子元件之製造方法，其中該淺接面 之厚度大體上為100埃〜500埃。 4·如申請專利範圍第1項所述之微電子元件之製造方法，其中將摻雜物 摻入該基底之步驟包括一離子佈植製程。 5·如申請專利範圍第1項所述之微電子元件之製造方法，其中該摻雜物 包括棚。 6·如申請專利範圍第1項所述之微電子元件之製造方法，其中該摻雜物 包括鱗。 7·如申請專利範圍第1項所述之微電子元件之製造方法，其中該摻雜物 包括珅。 8.如申請專利範圍第1項所述之微電子元件之製造方法，其中該摻雜物 之濃度大於或等於lxl〇2〇atoms/em3。 9·如申請專概15第1項所述之微電子元件之製造方法，其中將摻雜物 換入該基底包括形成一源極和没極之輕摻雜LDD區域。 1〇·如申睛專利範園第1項所述之微電子元件之製造方法，其中形成镇 應力層係採用化學氣相沉積法CVD。 η·如申請專利範園第1項所述之微電子元件之製造方法，其中形成錄 0503-A30932TWF2/wayn( 14 1278939 第94123526號申請專利範圍修正本 修正日期·· 95.1U3 應力層係採用物理氣相沉積法PVD。 12·如申請專利範圍第1項所述之微電子元件之製造方法，其中該應力 層包括氮化石夕。 13.如申請專利範圍第1項所述之微電子元件之製造方法，其中該應力 層包括氮氧化石夕。 14·如申請專利範圍第1項所述之微電子元件之製造方法，其中該應力 層係和基底之材料一致。 15·如申請專利範圍第1項所述之微電子元件之製造方法，其中該應力 層之應力介於_2GPa-+2GPa。 16.如申請專利範圍第1項所述之微電子元件之製造方法，其中該回火 之溫度介於500。(：〜ll〇〇〇c。 17·如申請專利範圍第丨項所述之微電子元件之製造方法，其中該回火 製程包括採用快速熱回火製程。 18·如申請專利範圍第1項所述之微電子元件之製造方法，其中該回火 製程包括固態磊晶製程SPE。 19·如申請專利範圍第1項所述之微電子元件之製造方法，其中該回火 製程包括峰值回火製程。 20·如申請專利範圍第1項所述之微電子元件之製造方法，其中該回火 製程包括雷射回火製程。 21.如申請專利範圍第1項所述之微電子元件之製造方法，尚包括在回 火製程後，移除部份之應力層。 。 22·如申請專利範圍第21項所述之微電子元件之製造方法，其中移匕部 份該應力層係在一閘極兩侧形成間隙壁。 23·如申請專利範圍第22項所述之微電子元件之製造方法，其中立 份之應力層係採用乾钱刻。 “ P 24·如申請專利範圍第1項所述之微電子元件之製造方法，尚包括在回 0503-A30932TWF2/wayne 15 1278939 第 94123526 號申請專利範圍修正本 修正日期：95.11.13 火製程後，大體上移除應力層。 25.如申請專利範圍第24項所述之微電子元件之製造方法，移除該應力 層係採用濕钱刻。 26·如申請專利範圍第1項所述之微電子元件之製造方法，尚包括一間 極位於該基底上，且該閘極包括一閘電極和一閘極介電層。 27. 如申請專利範圍第1項所述之微電子元件之製造方法，其中該半導 體基底係選自於下列族群之組合：石夕、錯、鑽石、碳化石夕、坤化鎵、、 GaAsP、AlInAs、AlGaAs、GalnAs、GalnP 和 GalnAsP 〇 28. —種微電子元件之製造方法，包括： 提供一半導體基底； 進行一離子佈植步驟以在該半導體基底中形成一摻雜區； 在該摻雜區上形成一應力層以增加該半導體基底之固溶性，其中該麻 力層直接接觸該源極區域和該汲極區域；及 進行一回火製程。 29. 如申請專利範圍第28項所述之微電子元件之製造方法，其中該回火 製程之溫度介於5〇〇〇C〜1100〇C。 30·如申請專利範圍第28項所述之微電子元件之製造方法，其中該播雜 物之濃度大於或等於lxl〇2Gat〇ms/cm3。 31·如申請專利範圍第28項所述之微電子元件之製造方法，其中該應力 層包括氮化石夕 32·如申請專利範圍第28項所述之微電子元件之製造方法，其中該應力 層包括氮氧化石夕。 33·如申請專利範圍第28項所述之微電子元件之製造方法，其中該應力 層之應力介於-2GPa〜+2GPa。 34·—種微電子元件，包括： 一基底； 16 0503-A30932TWF2/wayne 1278939 修正曰期：95.11.13 第94123526號申請專利範圍修正本 -摻雜區，具有-主動摻雜濃度，其中該主動摻雜濃度大體上大於或 等於該基底中摻雜物之平衡溶解極限(ESL);及 -應力層，具有最佳化之應力以增加該基底中摻雜物之平衡溶解極限 (ESL)，且直接接觸該摻雜區。 35.如申請專利範圍第34項所述之微電子元件，其中該應力層包括氧化 矽、氮化矽、氮氧化矽、碳化矽或上述之組合。 36·—種微電子元件之製造方法，其微電子元件包括一具有一淺接面之 半導體基底，該方法包括： 將摻雜物摻入一基底以形成一源極區域和一没極區域； 形成一應力層’直接接觸遠源極區域和沒極區域表面；及 在形成該應力層之後，及對該微電子元件進行更進一步擊孝。之斤參 該基底進行一回火製程。 、王之則’對 0503-A30932TWF2/wayne 171278939 No. 94132526 Application for revision of patent scope. One "'one'~~ period^5.11 13 X. Patent application scope: Busy ^丨月修修(more) Maben1· A manufacturing method of microelectronic components, The microelectronic component includes a semiconductor substrate having a shallow junction, the method comprising: doping a dopant into a substrate to form a source region and a drain region; forming a stress layer in the portion of the source region and not In the polar region, wherein the stress layer directly contacts the source region and the drain region; and performing a tempering process on the substrate. 2. The method for manufacturing a microelectronic device according to claim 1, The method of manufacturing the microelectronic device of claim 2, wherein the shallow junction has a thickness of substantially 100 angstroms to 500 angstroms. The method of manufacturing a microelectronic device according to claim 1, wherein the step of incorporating the dopant into the substrate comprises an ion implantation process. 5. The microelectronic device according to claim 1 Manufacturing The method of manufacturing a microelectronic device according to claim 1, wherein the dopant comprises a scale. 7. The micro as described in claim 1 The manufacturing method of the electronic component, wherein the dopant comprises ruthenium. The method of manufacturing the microelectronic component according to claim 1, wherein the dopant concentration is greater than or equal to lxl〇2〇atoms/em3 9. The method of manufacturing the microelectronic device of claim 1, wherein the exchanging the dopant into the substrate comprises forming a source and a immersed lightly doped LDD region. The method for manufacturing a microelectronic device according to the first aspect of the invention, wherein the formation of the town stress layer is by chemical vapor deposition CVD. η· The manufacturing method of the microelectronic device as described in claim 1 , Forming Record 0503-A30932TWF2/wayn (14 1278939 No. 9413226 Application No. Revised Revision Date·· 95.1U3 The stress layer is PVD by physical vapor deposition method. 12· As described in item 1 of the patent application scope Manufacturer of electronic components The method of manufacturing a microelectronic device according to the above aspect of the invention, wherein the stress layer comprises arsenic oxide. 14. The scope of claim 1 The method for manufacturing a microelectronic device, wherein the stress layer is in accordance with the material of the substrate. The method for manufacturing a microelectronic device according to claim 1, wherein the stress of the stress layer is between _2 GPa- The method of manufacturing a microelectronic device according to claim 1, wherein the temperature of the tempering is between 500. (: ll 〇〇〇 〇〇〇 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The method for manufacturing a microelectronic device, wherein the tempering process comprises a solid state epitaxial process SPE. The method of manufacturing a microelectronic device according to claim 1, wherein the tempering process comprises peak tempering The method of manufacturing a microelectronic component according to claim 1, wherein the tempering process comprises a laser tempering process. 21. The manufacture of the microelectronic component according to claim 1 The method further includes removing a portion of the stress layer after the tempering process. 22. The method of manufacturing a microelectronic device according to claim 21, wherein the stress layer is transferred to a gate A method for manufacturing a microelectronic device according to the invention of claim 22, wherein the stress layer of the standing portion is dry-cut. "P 24 · as claimed in claim 1 Micro-electricity The manufacturing method of the component is also included in the back of 0503-A30932TWF2/wayne 15 1278939. Patent No. 94132526. The scope of the patent is amended. The date of revision: 95.11.13 After the fire process, the stress layer is substantially removed. 25. If the patent application is in the 24th item In the manufacturing method of the microelectronic device, the method for manufacturing the microelectronic device according to claim 1, further comprising a pole on the substrate. The gate electrode includes a gate electrode and a gate dielectric layer. 27. The method of fabricating a microelectronic device according to claim 1, wherein the semiconductor substrate is selected from the group consisting of: , wrong, diamond, carbon carbide, gallium, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, and GalnAsP 〇28. A method of manufacturing a microelectronic component, comprising: providing a semiconductor substrate; performing an ion implantation step Forming a doped region in the semiconductor substrate; forming a stress layer on the doped region to increase solid solution of the semiconductor substrate, wherein the hemp layer directly contacts the source The region and the bungee region; and a tempering process. 29. The method of manufacturing a microelectronic device according to claim 28, wherein the temperature of the tempering process is between 5 〇〇〇C and 1100 〇 The method for manufacturing a microelectronic device according to claim 28, wherein the concentration of the broadcast is greater than or equal to lxl〇2Gat〇ms/cm3. 31. As described in claim 28 The method of manufacturing a microelectronic device, wherein the stress layer comprises a method of manufacturing a microelectronic device according to claim 28, wherein the stress layer comprises arsenic oxide. 33. The method of fabricating a microelectronic device according to claim 28, wherein the stress of the stress layer is between -2 GPa and +2 GPa. 34·—Microelectronic components, including: a substrate; 16 0503-A30932TWF2/wayne 1278939 Revised period: 95.11.13 Patent No. 94132526 modified patent-doped region with active doping concentration, wherein the active The doping concentration is substantially greater than or equal to the equilibrium solubility limit (ESL) of the dopant in the substrate; and the stress layer has an optimized stress to increase the equilibrium solubility limit (ESL) of the dopant in the substrate, and Direct contact with the doped region. The microelectronic component of claim 34, wherein the stressor layer comprises cerium oxide, cerium nitride, cerium oxynitride, cerium carbide or a combination thereof. 36. A method of fabricating a microelectronic device, the microelectronic device comprising a semiconductor substrate having a shallow junction, the method comprising: doping a dopant into a substrate to form a source region and a gate region; Forming a stress layer 'directly contacting the surface of the far source region and the gate region; and after forming the stress layer, and further tampering the microelectronic component. The substrate is subjected to a tempering process. , 王之则' to 0503-A30932TWF2/wayne 17
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