TWI346336B - Memory controller - Google Patents

Memory controller

Info

Publication number
TWI346336B
TWI346336B TW096125345A TW96125345A TWI346336B TW I346336 B TWI346336 B TW I346336B TW 096125345 A TW096125345 A TW 096125345A TW 96125345 A TW96125345 A TW 96125345A TW I346336 B TWI346336 B TW I346336B
Authority
TW
Taiwan
Prior art keywords
memory controller
controller
memory
Prior art date
Application number
TW096125345A
Other languages
English (en)
Other versions
TW200814056A (en
Inventor
Hiroshi Sukegawa
Takeshi Nakano
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200814056A publication Critical patent/TW200814056A/zh
Application granted granted Critical
Publication of TWI346336B publication Critical patent/TWI346336B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW096125345A 2006-07-14 2007-07-12 Memory controller TWI346336B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006194804A JP4945183B2 (ja) 2006-07-14 2006-07-14 メモリコントローラ

Publications (2)

Publication Number Publication Date
TW200814056A TW200814056A (en) 2008-03-16
TWI346336B true TWI346336B (en) 2011-08-01

Family

ID=39077226

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096125345A TWI346336B (en) 2006-07-14 2007-07-12 Memory controller

Country Status (3)

Country Link
US (2) US7558148B2 (zh)
JP (1) JP4945183B2 (zh)
TW (1) TWI346336B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849224B1 (ko) * 2007-02-01 2008-07-31 삼성전자주식회사 메모리 카드 시스템의 메모리 카드에 전원을 공급하는 방법및 메모리 카드 시스템
US7460398B1 (en) * 2007-06-19 2008-12-02 Micron Technology, Inc. Programming a memory with varying bits per cell
JP4534211B2 (ja) * 2007-12-26 2010-09-01 マイクロン テクノロジー， インク． 信頼性が改善された多値セルメモリデバイス
US7949821B2 (en) * 2008-06-12 2011-05-24 Micron Technology, Inc. Method of storing data on a flash memory device
JP2009301691A (ja) * 2008-06-17 2009-12-24 Renesas Technology Corp 不揮発性半導体記憶装置
US7920430B2 (en) * 2008-07-01 2011-04-05 Qimonda Ag Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
US7983078B2 (en) * 2008-09-24 2011-07-19 Sandisk Technologies Inc. Data retention of last word line of non-volatile memory arrays
JP2010134992A (ja) * 2008-12-04 2010-06-17 Powerchip Semiconductor Corp 不揮発性半導体記憶装置とその書き込み方法
US8412880B2 (en) * 2009-01-08 2013-04-02 Micron Technology, Inc. Memory system controller to manage wear leveling across a plurality of storage nodes
JP5259481B2 (ja) * 2009-04-14 2013-08-07 株式会社東芝 不揮発性半導体記憶装置
JP5912844B2 (ja) * 2011-05-31 2016-04-27 株式会社半導体エネルギー研究所 プログラマブルロジックデバイス
JP2013254537A (ja) 2012-06-06 2013-12-19 Toshiba Corp 半導体記憶装置及びコントローラ
KR20160006343A (ko) * 2014-07-08 2016-01-19 에스케이하이닉스 주식회사 반도체 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
DE102016115272A1 (de) * 2016-08-17 2018-02-22 Infineon Technologies Ag Speicher mit unterschiedlichen zuverlässigkeiten
US9940995B1 (en) * 2017-01-31 2018-04-10 Intel Corporation Methods and apparatus for reusing lookup table random-access memory (LUTRAM) elements as configuration random-access memory (CRAM) elements

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100259972B1 (ko) * 1997-01-21 2000-06-15 윤종용 메모리 셀당 2개 이상의 저장 상태들을 갖는 불휘발성 반도체 메모리 장치
JP3890647B2 (ja) * 1997-01-31 2007-03-07 ソニー株式会社 不揮発性半導体記憶装置
US6180454B1 (en) * 1999-10-29 2001-01-30 Advanced Micro Devices, Inc. Method for forming flash memory devices
JP4165990B2 (ja) 1999-12-20 2008-10-15 Ｔｄｋ株式会社 メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びに、フラッシュメモリへのデータの書き込み方法
JP3893005B2 (ja) 2000-01-06 2007-03-14 富士通株式会社 不揮発性半導体記憶装置
JP3741258B2 (ja) 2000-03-31 2006-02-01 シャープ株式会社 半導体記憶装置およびその救済方法
US7023739B2 (en) * 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
JP4398750B2 (ja) * 2004-02-17 2010-01-13 株式会社東芝 Ｎａｎｄ型フラッシュメモリ
JP2005285184A (ja) 2004-03-29 2005-10-13 Toshiba Corp 不揮発性半導体記憶装置
US7457156B2 (en) * 2004-09-02 2008-11-25 Micron Technology, Inc. NAND flash depletion cell structure
US7170785B2 (en) * 2004-09-09 2007-01-30 Macronix International Co., Ltd. Method and apparatus for operating a string of charge trapping memory cells
JP4991131B2 (ja) 2005-08-12 2012-08-01 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
JP4945183B2 (ja) 2012-06-06
US7558148B2 (en) 2009-07-07
US20080052447A1 (en) 2008-02-28
JP2008021394A (ja) 2008-01-31
TW200814056A (en) 2008-03-16
US20090241012A1 (en) 2009-09-24
US8107301B2 (en) 2012-01-31

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees