1-345292 九、發明說明： 【發明所屬之技術領域】 本發明係有關於捲帶式半導體封裝構造，特別係有 關於一種可改善角隅引腳斷裂之捲帶式半導體封裝構 造。 【先前技術】 捲帶式半導體封裝構造，例如捲帶式承載封裝（tape carrier package，TCP)與薄膜覆晶封裝（Chip-On-Film package，COF)，係具有厚度薄化與輕量化的優點，而 普遍運用在電子產品中。捲帶式半導體封裝構造係利 用一具有微間距引腳之薄膜基板作為晶片載體，並以 内引腳接合方式與晶片結合，以提供晶片與基板之間 的電氣通路和機械支撐。然而其作為晶片載體之基板 在熱膨脹係數上仍與半導體材質的晶片有所不同，導 致在熱循環試驗或實際運算時會產生内應力，通常應 力集中在晶片接合區一側邊兩端之部分引腳，即對應 至晶片之角隅，導致特定部位易有引腳斷裂或接合不 良。 請參閱第1及2圖所示，一種習知捲帶式半導體封 裝構造100包含一基板1 10、一晶片120以及一封膠 體1 3 0。該基板1 1 0係具有一可撓性介電層1 1 1及複數 個引腳1 1 2，該可撓性介電層1 1 1係具有一晶片接合區 1 13，例如貫穿該可撓性介電層 1 1 1之裝置孔（device hole)，該些引腳 1 12之内端係延伸至該晶片接合區 5 1345292 1 1 3。該晶片1 2 0係具有一主動面1 2 1以及複數個 於該主動面121之凸塊122，該些凸塊122係接 些引腳1 1 2之内端。該封膠體1 3 0係形成於該晶 合區113，以密封該些凸塊122。然而在實際封裝 中，溫度變化會產生内應力，特別是位在該晶片 區1 1 3長邊兩側之引腳1 1 2會遭受較大應力而為 集中區域，導致引腳112與其接合之凸塊122界 0 生斷裂（請參閱第1圖所示），或是引起引腳112 離。 【發明内容】 本發明之主要目的係在於提供一種捲帶式半 封裝構造，藉由金屬補強網位於可撓性介電層之 集中處且接合至晶片，能分散原集中於角隅處兩 腳之内應力，避免角隅引腳剝離或斷裂之問題， 進捲帶式半導體封裝構造之產品可靠性。 # 本發明的目的及解決其技術問題是採用以下 方案來實現的。依據本發明，一種捲帶式半導體 構造主要包含一基板、一晶片以及一封膠體。該 係具有一可撓性介電層、複數個引腳以及至少一 補強網，該基板係界定有一晶片接合區，該些引 該金屬補強網係形成於該可撓性介電層上並延伸 晶片接合區内，其中該金屬補強網係位於該晶片 區之角隅並包含有複數個虛引腳以及至少一連接 些虛引腳之桁架條（truss bar)。該晶片係設置於該 形成 合該 片接 產品 接合 應力 面產 之剝 導體 應力 側引 以增 技術 封裝 基板 金屬 腳與 至該 接合 在該 晶片 6 1345292 接合區，該晶片係具有複數個凸塊與複數個虛凸塊， 以分別接合於該些引腳及該些虛引腳。該封膠體係形 成於該晶片接合區，以密封該些凸塊。此外，另揭示 上述捲帶式半導體封裝構造所使用之基板。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述的捲帶式半導體封裝構造中，該桁架條係可 斜向連接至少一虛引腳。 在前述的捲帶式半導體封裝構造中，該桁架條之兩 端係可各斜向連接一虛引腳，而呈z形。 在前述的捲帶式半導體封裝構造中，連接在兩相鄰 虛引腳之間之複數個桁架條係可呈X形。 在前述的捲帶式半導體封裝構造中，在兩相鄰虛引 腳之間更可連接有一接合條。 在前述的捲帶式半導體封裝構造中，該基板可另具 有一防銲層，其係局部覆蓋該些引腳與該金屬補強網。 在前述的捲帶式半導體封裝構造中，複數個金屬補 強網係可位於該些引腳之兩側。 在前述的捲帶式半導體封裝構造中，該晶片接合區 係可為一裝置孔。 在前述的捲帶式半導體封裝構造中，該晶片接合區 係可由一防銲層之一開孔所界定。 在前述的捲帶式半導體封裝構造中，該晶片之該些 虛凸塊係不具有訊號傳遞功能。 7 1345292 【實施方式】 依據本發明之第一具體實施例，揭示一種捲帶式半 導體封裝構造。第3圖係為該捲帶式半導體封裝構造 之截面示意圖。第4圖係為該捲帶式半導體封裝構造 透視其封膠體之頂面示意圖。第5圖係為該捲帶式半 導體封裝構造沿第4圖5 - 5線剖切之截面示意圖。第6 圖係為該捲帶式半導體封裝構造中一基板之頂面示意 圖。第7圖係為該捲帶式半導體封裝構造中一晶片之 主動面示意圖。 請參閱第3及4圖所示，一種捲帶式半導體封裝構 造200主要包含一基板210、一晶片220以及一封膠 體 230。 該基板2 1 0係具有一可撓性介電層2 1 1、複數個引 腳2 1 2以及至少一金屬補強網2 4 0。其中，該可撓性 介電層211係界定有一晶片接合區213,該些引腳212 與該金屬補強網 240係形成於該可撓性介電層 2 1 1 上，可直接形成或利用一黏著層（圖未繪出）達到黏 接，並延伸至該晶片接合區213内，其中該些引腳212 係具有電性傳遞的功能，如訊號連接、電源或接地等 等。該金屬補強網240係位於該晶片接合區2 1 3之角 隅（請參閱第4圖所示）。通常該可撓性介電層2 1 1之 材質可選用聚亞醯胺（polyimide，PI)、聚醋（polyester, PET)或其他材料。 在本實施例中，該捲帶式半導體封裝構造2 0 0係為 8 1345292 捲帶式承載封裝（tape carrier paCkage，TCP)型態，也 就是說，該晶片接合區2 1 3係為〆裝置孔（圖未繪出）， 其係貫通該基板210之可撓性介電層211。在不同實 施例中，該捲帶式半導體封裝構邊200亦可應用於薄 膜覆晶封裝（COF)。 此外’請參閱第5及6圖所示，該金屬補強網240 係包含有複數個虛引腳24 1以及至少一連接在該些虛 引腳241之桁架條242(truss bar)，以提供内應力之分 散功能。較佳地，在兩相鄰虛引腳2 41之間更可連接 有一接合條243，以增加凸塊接合面積，提升結合強 度。在本實施例中，複數個金屬補強網24〇係排列於 該可撓性介電層211之預期應力集中處，一般係可位 於該些引腳2 1 2之兩側，即接近於該晶片接合區2 i 3 之角隅，以分散原施加於該些引腳212之角隅處之内 應力’避免該些引腳212斷裂或/與剝離。該些虛引腳 241係為直條狀，通常該些虛引腳241係為額外附設 且無電性功能的引腳。在本實施例中，該桁架條242 係可斜向連接至少一虛引腳241。該桁架條242之兩 端係可各斜向連接一虛引腳241，而呈z形。尤佳地， 請再參閱第6圖所示，藉由增加桁架條242之數量， 連接在兩相鄰虛引腳24 1之間之複數個桁架條242係 可呈X形。較佳地，如第5圖所示，該基板21〇可另 具有一防銲層214，其係局部覆蓋該些引腳212與該金 屬補強網240，用以增加該金屬補強網240之貼附性。 9 1-345292 . 請參閱第4及7圖所示，該晶片2 2 0係設置於該晶 片接合區213。配合參閱第3及5圖，該晶片220係 具有一主動面221、複數個凸塊222與複數個虛凸塊 223，以分別接合於該些引腳212及該些虛引腳241， 其中該些凸塊222與該些虛凸塊223係形成於該主動 面221。一般而言，該些凸塊222與該些引腳212之 鍵合界面的金屬組合係可為金/金、金/錫等。請再參閱 第7圖所示，該些虛凸塊223係位於該晶片220之該 主動面221之角隅處，該些虛凸塊223係可不具有訊 號傳遞功能。在不同實施例中，在每一角隅之虛凸塊 2 2 3除了矩形塊體，亦可為L形塊體。此外，該封膠 體23 0係形成於該晶片接合區2 1 3，以密封該些凸塊 222與該些虛凸塊223，並提供適當的封裝保護以防止 電性短路與塵埃污染。 因此，該金屬補強網240與該些虛凸塊223之接合 可作為内應力集中引起引腳斷裂前之保險機構，即使 該金屬補強網240之該些虛引腳241產生斷裂亦不會 影響該捲帶式半導體封裝構造200之電性連接傳輸。 此外，桁架條242之連接可以分散在該些虛引腳241 之内應力，不會有角隅引腳斷裂或/與剝離之問題，藉 以提高該捲帶式半導體封裝構造200之產品可靠性。 在本發明之第二具體實施例中，請參閱第 8及 9 圖，揭示另一種捲帶式半導體封裝構造，主要包含一基 板310、一晶片320以及一封膠體330，主要元件大致 10 1345292 與第一實施例相同。然在本實施例中，該捲帶式半導體 封裝構造係為薄膜覆晶封裝（Chip-On-Film package， COF)型態》該基板310係具有一可撓性介電層311、 複數個引腳3 1 2以及至少一金屬補強網3 4 0，該基板 3 1 0係界定有一晶片接合區3丨3，在本實施例中，由於 薄膜覆晶封裝型態，該晶片接合區3 13係可由一防銲 滑3 1 4之一開孔所界定。該防銲層3 1 4係局部覆蓋該 些引腳312與該金屬補強網34〇。 該些引腳312與該金屬補強網340係形成於該可撓 性介電層311上並延伸至該晶片接合區313内，其中 該金屬補強網3 4 0係位於該晶片接合區3 1 3之角隅並 包含有複數個虛引腳341以及至少一連接在該些虛引 腳341之街架條342(trussbar)。而該些引腳312與該 些虛引腳3 4 1延伸至該晶片接合區3 1 3内的部位仍貼 附於該可撓性介電層3丨丨。該防銲層3 1 4係形成於該 基板310上且覆蓋該些引腳312之一部份與該些虛引 腳341之一部份，能防止在晶片接合區313外之該些 引腳3 1 2外露被污染而短路。 該晶片320係設置於該晶片接合區3 13,該晶片320 係具有複數個形成於一主動面321之凸塊322與虛凸 塊323，其中該些凸塊322與該些虛凸塊323係用以 分別接合於該些引腳312及該些虛引腳341。另，該 封膠體3 3 0係形成於該晶片接合區3 1 3，以密封該些 凸塊322與虛凸塊323。因此，藉由該金屬補強網340 11 1345292 . 之位置與組成關係可以分散該捲帶式半導體封裝構造 中施加於特定引腳3 1 2之内應力，以減輕負載及避免 該些引腳 3 1 2在兩側的應力集中處發生斷裂或/與剝 離，以提昇產品可靠性。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本專業的技術人員，在不脫離本發明技術方案範圍 内，當可利用上述揭示的技術内容作出些許更動或修 飾為等同變化的等效實施例，但凡是未脫離本發明技 術方案的内容，依據本發明的技術實質對以上實施例 所作的任何簡單修改、等同變化與修飾，均仍屬於本 發明技術方案的範圍内。 【圖式簡單說明】 第1圖：習知捲帶式半導體封裝構造之截面示意圖。 第2圖：習知捲帶式半導體封裝構造之頂面示意圖。 第3圖：依據本發明之第一具體實施例，一種捲帶式 半導體封裝構造之截面示意圖。 第4圖：依據本發明之第一具體實施例，該捲帶式半 導體封裝構造透視其封膠體之頂面示意圖。 第5圖：依據本發明之第一具體實施例，該捲帶式半 導體封裝構造沿第4圖5 - 5線剖切之截面示 意圖。 第6圖：依據本發明之第一具體實施例，該捲帶式半 12 1345292 . 導體封裝構造中一基板之頂面示意圖。 第7圖.依據本發明之第一具體實施例，該捲帶式半 導體封裝構造中一晶片之主動面示意圖。 第8圖.依據本發明之第二具體實施例，另一種捲帶 式半導體封裝構造在封膠前且透視其可撓性 介電層之頂面示意圖。 第9圖.依據本發明之第二具體實施例，該捲帶式半 導體封裝構造沿第8圖9_9線剖切之截面示 意圖。 【主要元件符號說明】 1〇〇捲帶式半導體封裝構造 110 基板 111 可撓性介電層 112 引 腳 113 晶片接合 區 120 晶片 121 主動面 122 凸 塊 130 封膠體 200 捲帶式半 導體封裝構造 210 基板 211 可撓性介電層 212 引 腳 213 晶片接合 區 214 防銲層 220 晶片 221 主動面 222 凸 塊 223 虛凸塊 230 封膠體 240 金屬補強 網 241 虛引腳 242 枪 架條 243 接合條 310 基板 311 可撓性介電層 312 引 腳 313 晶片接合 區 314 防鲜層 13 1*345292 320晶片 321主動面 322凸塊323虚凸塊 ：330封膠體 340金屬補強網 341虛引腳 342桁架條1-345292 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a tape-and-reel semiconductor package structure, and more particularly to a tape-and-reel package structure which can improve corner pin breakage. [Prior Art] Tape and reel type semiconductor package structures, such as tape carrier package (TCP) and chip-on-film package (COF), have the advantages of thinner thickness and lighter weight. And is widely used in electronic products. The tape and reel type semiconductor package construction utilizes a film substrate having micro pitch pins as a wafer carrier and is bonded to the wafer by internal pin bonding to provide electrical path and mechanical support between the wafer and the substrate. However, the substrate as the wafer carrier still differs from the semiconductor material in the coefficient of thermal expansion, resulting in internal stresses generated during thermal cycling tests or actual calculations. Usually, stress is concentrated on the ends of one side of the wafer bonding region. The foot, that is, the corner 对应 corresponding to the wafer, causes the pin to be broken or poorly bonded at a specific portion. Referring to Figures 1 and 2, a conventional tape and reel type semiconductor package structure 100 includes a substrate 110, a wafer 120, and a gel 1130. The substrate 110 has a flexible dielectric layer 11 1 and a plurality of pins 1 1 2 , and the flexible dielectric layer 11 1 has a wafer bonding region 1 13 , for example, through the flexible The device holes of the dielectric layer 112 are extended to the wafer bonding region 5 1345292 1 1 3 . The wafer 120 has an active surface 1 2 1 and a plurality of bumps 122 on the active surface 121. The bumps 122 are connected to the inner ends of the pins 112. The encapsulant 130 is formed in the crystallized region 113 to seal the bumps 122. However, in the actual package, the temperature change will generate internal stress, especially the pin 11 2 located on both sides of the long side of the wafer region 1 1 3 will be subjected to a large stress and become a concentrated region, causing the pin 112 to be bonded thereto. The bump 122 has a zero break (see Figure 1), or causes the pin 112 to leave. SUMMARY OF THE INVENTION The main object of the present invention is to provide a tape and reel package structure in which a metal reinforcing mesh is located at a concentrated portion of a flexible dielectric layer and bonded to a wafer, and can be dispersed at a corner of the corner. The internal stress prevents the problem of peeling or breaking of the corner pin, and the product reliability of the tape-wound semiconductor package structure. # The object of the present invention and solving the technical problems thereof are achieved by the following schemes. According to the present invention, a tape and reel type semiconductor structure mainly comprises a substrate, a wafer, and a gel. The device has a flexible dielectric layer, a plurality of leads, and at least one reinforcing mesh. The substrate defines a die bonding region, and the metal reinforcing mesh is formed on the flexible dielectric layer and extends In the wafer bonding region, the metal reinforcing network is located at a corner of the wafer region and includes a plurality of dummy pins and at least one truss bar connecting the dummy pins. The wafer is disposed on the stripping conductor stress side of the bond forming surface of the sheet bonding product, and the bonding metal substrate of the bonding substrate is bonded to the bonding region of the wafer 6 1345292. The wafer system has a plurality of bumps and A plurality of dummy bumps are respectively bonded to the pins and the dummy pins. The encapsulation system is formed in the wafer bonding region to seal the bumps. Further, a substrate used in the tape-and-reel type semiconductor package structure described above is also disclosed. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the tape and reel type semiconductor package construction described above, the truss strip can be obliquely connected to at least one dummy pin. In the tape-and-reel semiconductor package structure described above, the ends of the truss strips may be obliquely connected to a dummy pin to have a z-shape. In the tape and reel type semiconductor package construction described above, the plurality of truss strips connected between two adjacent dummy pins may be X-shaped. In the tape-and-reel semiconductor package construction described above, a bonding strip is further connectable between two adjacent dummy pins. In the tape and reel type semiconductor package construction described above, the substrate may have a solder resist layer partially covering the pins and the metal reinforcing mesh. In the tape and reel type semiconductor package construction described above, a plurality of metal reinforcing mesh systems may be located on both sides of the pins. In the tape and reel type semiconductor package construction described above, the wafer bonding region can be a device aperture. In the tape and reel type semiconductor package construction described above, the wafer bonding region may be defined by an opening of one of the solder resist layers. In the tape and reel type semiconductor package construction described above, the dummy bumps of the wafer do not have a signal transfer function. 7 1345292 [Embodiment] According to a first embodiment of the present invention, a tape-and-reel semiconductor package structure is disclosed. Fig. 3 is a schematic cross-sectional view showing the tape-type semiconductor package structure. Fig. 4 is a schematic view showing the top surface of the tape-wound semiconductor package structure in perspective. Fig. 5 is a schematic cross-sectional view showing the tape-wound semiconductor package structure taken along line 5 - 5 of Fig. 4. Figure 6 is a top plan view of a substrate in the tape-and-reel semiconductor package construction. Figure 7 is a schematic illustration of the active side of a wafer in the tape and reel semiconductor package construction. Referring to FIGS. 3 and 4, a tape and reel package structure 200 mainly includes a substrate 210, a wafer 220, and a paste 230. The substrate 210 has a flexible dielectric layer 2 1 1 , a plurality of pins 2 1 2, and at least one metal reinforcing mesh 240. The flexible dielectric layer 211 defines a die bond region 213. The pins 212 and the metal reinforcement mesh 240 are formed on the flexible dielectric layer 21, and can be directly formed or utilized. The adhesive layer (not shown) is bonded and extends into the wafer bond area 213, wherein the pins 212 have electrical transfer functions such as signal connection, power or grounding, and the like. The metal reinforcement mesh 240 is located at the corner of the wafer bonding region 2 1 3 (see Figure 4). Generally, the flexible dielectric layer 21 1 may be made of polyimide, PI, or other materials. In this embodiment, the tape-and-reel package structure 200 is a 8 1345292 tape carrier type (Tape carrier paCkage, TCP) type, that is, the wafer bonding area 2 1 3 is a device. A hole (not shown) that penetrates the flexible dielectric layer 211 of the substrate 210. In various embodiments, the tape and reel semiconductor package edge 200 can also be applied to a thin film flip chip package (COF). In addition, as shown in Figures 5 and 6, the metal reinforcement network 240 includes a plurality of dummy pins 24 1 and at least one truss bar 242 connected to the dummy pins 241 to provide internal The dispersion function of stress. Preferably, a bonding strip 243 is further connected between the two adjacent dummy pins 2 41 to increase the bump bonding area and improve the bonding strength. In this embodiment, a plurality of metal reinforcing nets 24 are arranged in the desired stress concentration of the flexible dielectric layer 211, and generally can be located on both sides of the pins 21, 2, that is, close to the wafer. The corners of the land 2 i 3 are dispersed to impart internal stresses at the corners of the pins 212 to prevent the pins 212 from breaking or/and peeling. The dummy pins 241 are straight strips, and usually the dummy pins 241 are pins that are additionally attached and have no electrical function. In this embodiment, the truss strip 242 can be obliquely connected to at least one dummy pin 241. The two ends of the truss strip 242 can be obliquely connected to a dummy pin 241 to have a z-shape. More preferably, referring to Fig. 6, by increasing the number of truss strips 242, a plurality of truss strips 242 connected between two adjacent dummy pins 24 1 may be X-shaped. Preferably, as shown in FIG. 5, the substrate 21A may further have a solder resist layer 214 partially covering the pins 212 and the metal reinforcing net 240 for increasing the adhesion of the metal reinforcing net 240. Attached. 9 1-345292 . Referring to Figures 4 and 7, the wafer 220 is disposed in the wafer bonding region 213. Referring to FIGS. 3 and 5, the wafer 220 has an active surface 221, a plurality of bumps 222, and a plurality of dummy bumps 223 for bonding to the pins 212 and the dummy pins 241, respectively. The bumps 222 and the dummy bumps 223 are formed on the active surface 221 . In general, the metal combination of the bumps 222 and the bonding interfaces of the leads 212 may be gold/gold, gold/tin or the like. Referring to FIG. 7 again, the dummy bumps 223 are located at the corners of the active surface 221 of the wafer 220. The dummy bumps 223 may not have a signal transfer function. In various embodiments, the virtual bumps 2 2 3 at each corner may be L-shaped blocks in addition to the rectangular blocks. In addition, the encapsulant 230 is formed in the wafer bonding region 2 1 3 to seal the bumps 222 and the dummy bumps 223 and provide proper package protection to prevent electrical short circuits and dust pollution. Therefore, the bonding of the metal reinforcing net 240 and the dummy bumps 223 can serve as a safety mechanism before the internal stress concentration causes the pins to break, even if the dummy pins 241 of the metal reinforcing net 240 are broken, the The electrical connection of the tape and unwinding semiconductor package structure 200 is transmitted. In addition, the connection of the truss strips 242 can be dispersed within the dummy leads 241 without the problem of breakage or/and peeling of the corner pins, thereby improving the reliability of the product of the tape-and-reel package structure 200. In a second embodiment of the present invention, reference is made to FIGS. 8 and 9 to disclose another tape and reel type semiconductor package structure, which mainly includes a substrate 310, a wafer 320, and a colloid 330. The main components are approximately 10 1345292 and The first embodiment is the same. In this embodiment, the tape-and-reel package structure is a Chip-On-Film package (COF) type. The substrate 310 has a flexible dielectric layer 311 and a plurality of leads. The substrate 3 1 2 and the at least one metal reinforcing mesh 340 define a wafer bonding region 3 丨 3 . In the embodiment, the wafer bonding region 3 13 is It can be defined by one of the anti-welding slides 3 1 4 . The solder resist layer 3 14 partially covers the leads 312 and the metal reinforcing mesh 34 〇. The pins 312 and the metal reinforcing mesh 340 are formed on the flexible dielectric layer 311 and extend into the wafer bonding region 313, wherein the metal reinforcing mesh 340 is located in the wafer bonding region 3 1 3 The corner 隅 includes a plurality of dummy pins 341 and at least one truss bar 342 connected to the dummy pins 341. The pins 312 and the portions of the dummy pins 34 that extend into the die bond region 3 1 3 are still attached to the flexible dielectric layer 3 . The solder resist layer 314 is formed on the substrate 310 and covers a portion of the pins 312 and a portion of the dummy pins 341 to prevent the pins outside the wafer bonding region 313. 3 1 2 The exposed surface is contaminated and shorted. The chip 320 is disposed on the wafer bonding region 3-13. The wafer 320 has a plurality of bumps 322 and dummy bumps 323 formed on an active surface 321, wherein the bumps 322 and the dummy bumps 323 are For bonding to the pins 312 and the dummy pins 341, respectively. In addition, the encapsulant 3 30 is formed in the wafer bonding region 3 1 3 to seal the bumps 322 and the dummy bumps 323. Therefore, the position and composition relationship of the metal reinforcing mesh 340 11 1345292 can disperse the stress applied to the specific pin 3 1 2 in the tape-and-conductor package structure to reduce the load and avoid the pins 3 1 . 2 Breaking or/and peeling occurs at the stress concentration on both sides to improve product reliability. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to equivalent embodiments by using the above-disclosed technical contents without departing from the technical scope of the present invention. It is still within the scope of the technical solution of the present invention to make any simple modifications, equivalent changes and modifications to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional tape-and-reel type semiconductor package structure. Figure 2: Schematic diagram of the top surface of a conventional tape and reel type semiconductor package structure. Figure 3 is a cross-sectional view showing a tape-wound semiconductor package structure in accordance with a first embodiment of the present invention. Fig. 4 is a perspective view showing the top surface of the enveloping body of the tape reel package structure according to the first embodiment of the present invention. Fig. 5 is a cross-sectional view, taken along line 5 - 5 of Fig. 4, of the first embodiment of the present invention. Figure 6 is a top plan view of a substrate in a conductor package construction in accordance with a first embodiment of the present invention. Figure 7 is a schematic illustration of the active side of a wafer in the tape and reel package construction in accordance with a first embodiment of the present invention. Figure 8. In accordance with a second embodiment of the present invention, another ribbon-wound semiconductor package is constructed prior to encapsulation and is a perspective view of the top surface of the flexible dielectric layer. Figure 9 is a cross-sectional view, taken along line 9-9 of Figure 8, of the second embodiment of the present invention. [Main component symbol description] 1 〇〇 tape-and-reel semiconductor package structure 110 substrate 111 flexible dielectric layer 112 pin 113 wafer bonding region 120 wafer 121 active surface 122 bump 130 encapsulant 200 tape-and-reel semiconductor package structure 210 Substrate 211 Flexible Dielectric Layer 212 Pin 213 Wafer Bonding Area 214 Solder Mask 220 Wafer 221 Active Surface 222 Bump 223 Virtual Bump 230 Sealant 240 Metal Reinforcing Web 241 Virtual Lead 242 Gun Bar 243 Bonding Strip 310 Substrate 311 Flexible Dielectric Layer 312 Pin 313 Wafer Junction Area 314 Fresh-keeping Layer 13 1*345292 320 Wafer 321 Active Surface 322 Bump 323 Virtual Bump: 330 Sealant 340 Metal Reinforcing Net 341 Virtual Lead 342 Truss Strip
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