1295097 九、發明說明： 【發明所屬之技術領域】 本發明係有關於薄膜覆晶封農（Chip-On_Film packaging) 技術，特別係有關於一種薄膜覆晶封裝之多層電路捲帶結 構。 【先前技術】 薄膜覆晶封裝（Chip-On-Film，COF packaging)是一種能 取代捲帶承載封裝（Tape Carrier Package，TCP)的新一代技 術’除了晶片接合技術的進步之後，其餘製程大致相同，亦 能以捲帶對捲帶傳輸（reel-to-reel)方式移動適用薄膜覆晶封 裝之電路捲帶。通常需要薄膜覆晶封裝之晶片具有更微小的 尺寸與更多數量的凸塊（即輸出/輸入電極端），然而通常薄膜 覆晶封裝之電路捲帶僅為單層線路之結構，即所有引腳皆是 排列在同一層，故捲帶内引腳的設計空間有限並且受限於機 台精準度使引腳間距不能無限制縮小，故只能加大變更晶片 的尺寸或是僅可封裝較低解析度之顯示器驅動晶片。 如第1圖所示，習知的薄膜覆晶封裝構造係將一具有凸 塊11之晶片10覆晶接合至一單層電路捲帶1〇〇上，並令一 封膠體30形成於該晶片1〇與該單層電路捲帶i⑼之間，以 密封該些凸塊1卜如第2及3圖所示，該單層電路捲帶1〇〇 係具有複數個位於一覆晶接合區101兩侧之單排引腳12〇， 該些引腳120係形成在一介電層11〇上且被一防銲層所 局部覆蓋，該些引腳120顯露於該防銲層13〇之部位則作為 供該些凸塊U接合之&塊接合端121，通常其接合處係為金 5 1295097 -金（Au-Au)鍵合較為常見。由於該些凸塊接合端121係低於 該防婷層130’該防鲜層130係必須具有一尺寸略大於該覆 晶接合區101之開孔131(如第3圖所示），以顯露所有之該 些凸塊接合端121，否則該防銲層130在印刷時會流入該覆 晶接合區101而污染至該些凸塊接合端m，且會導致在覆 ’ 晶接合時該些凸塊11與該些凸塊接合端121無法順利鍵 ， 合。因此，該些引腳120位於該覆晶接合區ιοί内之部位是 Φ 被該開孔131全部裸露，當延伸長度越長，顯露部位也越多， 忒些引腳120容易在封裝製程中發生電性橋接與被微粒污染 之問題。故該些引腳120之可設計空間受限，無法封裝高解 析度與高性能COF產品之晶片。 我國專利公告第505315號「薄膜覆晶封裝構造」即揭示 一種薄膜覆晶封裝之單層電路捲帶，仍會遭遇上述相同之問 題另，我國專利公告第483070號「多層構造之軟性電路 板之製造方法」揭示一種可供覆晶接合之多層軟性電路板， _ 不同層之金屬配線是以内埋之金屬突起相互電性連接，供晶 片凸塊接合之表面顯露之金屬被膜仍是低於一位在最表面 之防銲層，配線複雜導致整體多層軟性電路板之成本甚高， 並且對於凸塊之鍵合力亦不佳。再者，我國專利證書號數第 M269571號「多晶片薄臈封|構造及其可撓性多層電路板」 揭示-種多層軟性電路板，在一介電層上下表面之兩線路層 :別可i、複數個aa片之覆晶接合與打線接合，無法整合作為 單-晶片之覆晶接合，無法接合具有矩陣排列或兩排以上排 列的凸塊之晶片。 6 1295097 【發明内容】1295097 IX. Description of the Invention: [Technical Field] The present invention relates to a chip-on-film packaging technology, and more particularly to a multilayer circuit ribbon structure of a film flip chip package. [Prior Art] Chip-On-Film (COF packaging) is a new generation technology that can replace the Tape Carrier Package (TCP). After the advancement of wafer bonding technology, the rest of the process is almost the same. It is also possible to move the circuit tape for a film flip chip package in a reel-to-reel manner. Generally, a wafer flip-chip package requires a smaller size and a larger number of bumps (ie, output/input electrode terminals). However, a circuit-wrap package usually has a single-layer line structure, that is, all leads. The feet are arranged in the same layer, so the design space of the pins in the tape is limited and limited by the precision of the machine, so that the pitch of the pins can not be reduced without limitation, so the size of the wafer can only be changed or only the package can be packaged. A low resolution display drives the wafer. As shown in FIG. 1, a conventional film flip-chip package structure is to flip-chip a wafer 10 having bumps 11 onto a single-layer circuit tape 1 and a gel 30 is formed on the wafer. 1〇 and the single-layer circuit tape i (9) to seal the bumps 1 as shown in FIGS. 2 and 3, the single-layer circuit tape 1 has a plurality of layers in a flip-chip bonding region 101 A single row of pins 12 两侧 on both sides, the pins 120 are formed on a dielectric layer 11 且 and partially covered by a solder mask layer, and the pins 120 are exposed on the solder resist layer 13 Then, as the <block joint end 121 for joining the bumps U, the joint is usually gold 5 1295097 - gold (Au-Au) bonding is more common. Since the bump bonding ends 121 are lower than the anti-Ting layer 130', the anti-fresh layer 130 must have an opening 131 slightly larger than the flip-chip bonding region 101 (as shown in FIG. 3) to reveal All of the bumps are joined to the end 121. Otherwise, the solder resist layer 130 may flow into the flip chip bonding region 101 during printing to contaminate the bump bonding ends m, and may cause the bumps during the over-grain bonding. The block 11 and the bump engaging ends 121 cannot be smoothly bonded. Therefore, the portions of the pins 120 located in the flip-chip bonding region Φ are all exposed by the opening 131. When the extension length is longer, the exposed portions are also more, and the pins 120 are easily formed in the packaging process. Electrical bridging and contamination by particles. Therefore, the design of these pins 120 is limited, and it is impossible to package wafers with high resolution and high performance COF products. China Patent Publication No. 505315 "Thin Film Flip-Chip Package Structure" discloses a single-layer circuit tape with a film-on-chip package, which still suffers from the same problems as described above. In addition, China Patent Publication No. 483070 "Multi-layered flexible circuit board" The manufacturing method discloses a multilayer flexible circuit board for flip chip bonding, _ metal wiring of different layers is electrically connected to each other by embedded metal protrusions, and the metal film exposed on the surface of the wafer bump bonding is still lower than one bit. At the outermost solder mask, the wiring is complicated, resulting in a high cost of the overall multilayer flexible circuit board, and the bonding force for the bumps is also poor. Furthermore, China Patent Certificate No. M269571 "Multi-Wafer Thin Film Sealing | Structure and Flexible Multilayer Circuit Board" discloses a multilayer flexible circuit board, two circuit layers on the upper and lower surfaces of a dielectric layer: i. The flip chip bonding and the wire bonding of a plurality of aa sheets cannot be integrated as a single-wafer flip-chip bonding, and a wafer having a matrix arrangement or two or more rows of bumps cannot be bonded. 6 1295097 [Summary content]
本發明之主要目的係在於提供一種薄膜覆晶封裝之多層 電路捲帶結構，利用一介電層係電性隔離複數個第一層引腳 與複數個第二層引腳，且該些第一層引腳與該些第二層引腳 各具有複數個對應之第一凸塊接合端與第二凸塊接合端，其 係形成於一覆晶接合區内且顯露於一防銲層之外，故能接合 一晶片之矩陣排列或多排（兩排以上）排列的凸塊，在内引腳 間距可縮小之製程能力内可以在覆晶接合區内增加凸塊接 合端之數量或間距，在現行捲帶引腳製作能力下使該多層電 路捲帶結構能應用於更高解析度或更高性能的c〇f(薄膜覆 晶封裝）產品。 本發明之次—目的係在於提供—種薄膜覆晶封裝之多層 電路捲帶結構，其中在不同層引腳之第_凸塊接合端與第二 凸塊接合端係為條狀且均具有突出於防銲層之高度，使得防 銲層能簡單印刷形成而不需要曝光顯影(無黃光製程)或是不 需要使用貼附之孔對位，故連接不同層引職突出之第一凸 塊接合端與第…接合端可達到該防銲層之低成本形成 又在覆晶接合時有利於凸塊之接合。 本發明之另—目的係在於提供—㈣膜覆晶封裝之多層 電路捲帶結構’其中該些第-層引腳與該些第二層引腳各且 有複數個第-外接合端與第二外接合端，如同第—凸塊接ς 端與第二凸塊接合端亦顯露於防 Α 口 玲心yri间一表面，可 封裝高密度顯示器驅動晶片。 ’、 依據本發明之—種薄膜覆晶封裝之多層電路捲帶結構， 1295097 其上表面係定義有一覆晶接合複數 於一第一入啻思1够 . 層引腳係形成 、、 "'層上，一第一介電層係形成於該第一介電層上The main purpose of the present invention is to provide a multilayer circuit ribbon structure of a thin film flip chip package, electrically separating a plurality of first layer pins and a plurality of second layer pins by using a dielectric layer, and the first The layer pins and the second layer pins each have a plurality of corresponding first bump bonding ends and second bump bonding ends formed in a flip chip bonding region and exposed outside a solder mask layer Therefore, it is possible to bond a matrix array of a wafer or a plurality of rows (two rows or more) of bumps, and the number or pitch of the bump joint ends can be increased in the flip chip bonding region in the process capability in which the inner lead pitch can be reduced. The multilayer tape and reel structure can be applied to higher resolution or higher performance c〇f (film flip chip) products under the current tape and lead pin fabrication capability. The second aspect of the present invention is to provide a multilayer circuit tape reel structure of a film flip-chip package in which the y-bump joint end and the second bump joint end of the different layer pins are strip-shaped and both have protrusions. At the height of the solder mask, the solder resist layer can be easily printed without the need for exposure and development (no yellow light process) or the use of the attached hole alignment, so the first bumps connected to different layers are highlighted. The joint end and the ... joint end can achieve low cost formation of the solder resist layer and facilitate bonding of the bumps during flip chip bonding. Another object of the present invention is to provide a multilayer circuit ribbon structure of a (four) film flip chip package, wherein the first layer pins and the second layer pins each have a plurality of first-outer joint ends and The two outer joint ends, like the first bump joint end and the second bump joint end, are also exposed on the surface of the tamper-proof yri, and can package the high-density display to drive the wafer. According to the present invention, a multi-layer circuit tape-and-reel structure of a film flip-chip package, 1295097, has a flip-chip bond on the upper surface of which a plurality of flip-chip bonding is sufficient for a first-in-one 啻1. layer pin formation, "' a first dielectric layer is formed on the first dielectric layer
並覆蓋該些第一層引腳，複數個第二層弓丨腳係形成於該；二 介電層上且與該些第一層引腳為電性隔離，—防銲二： 於該第二介電層上並覆蓋該些第二層引腳。其中二第二 2引腳與該些第二層引腳各具有複數個對應之第一Z塊接 口端與第二凸塊接合端，其係形成於該覆晶接合區内且 於該防銲層之外。 【實施方式】 依據本發明之一具體實施例，帛4圖係為一種薄膜覆曰 封裝構造之多層電路捲帶結構之截面示意圖，第5圖係為: 多層電路捲帶結構與一晶片結合之透視示意圖。 ^And covering the first layer of pins, a plurality of second layers of the legs are formed on the two dielectric layers and electrically isolated from the first layers of the pins, the solder resist 2: The second dielectric pins are covered on the second dielectric layer. The second second pin and the second layer pins each have a plurality of corresponding first Z block interface ends and second bump junction ends, which are formed in the flip chip bonding region and are in the solder resist Outside the layer. [Embodiment] According to an embodiment of the present invention, a 帛4 diagram is a schematic cross-sectional view of a multilayer circuit tape structure of a film-covered package structure, and FIG. 5 is a multi-layer circuit tape structure combined with a wafer. Perspective schematic. ^
如第5 ®所*，該多層電路捲帶結構2〇〇於在其上表面 係疋義有一覆晶接合區201，其尺寸約略等同一晶片Μ之主 動面（如第6園所示）。並且如第4圖所示，該多層電路捲帶 結構200係、包含有一第一介電層21〇、複數個第—層引腳 220、一第二介電層23〇、複數個第二層引腳24〇及一防銲層 25〇。其中該第一介電層210與該第二介電層23〇係作為該 些第-層引腳220與該些第二層引腳24q之載體，其材質可 為PI(P〇lyimide，聚醯亞胺）。該些第_層引腳22〇係形成於 該第—介電層21〇上，大部份之每一第一層引腳22〇係具有 一第一凸塊接合端221與一第一外接合端222。 該第二介電層230係形成於該第一介電層21〇上並覆蓋 該些第-層引腳220。該些第二層5丨腳24〇係形成於該第二 8 /1295097 介電層230上並且藉由該第二介電層23〇之間隔使該些第二 層引腳240與該些第一層引腳22〇為電性隔離。其中，大部 份之每一第二層弓丨腳24〇係具有一第二凸塊接合端241與一 第二外接合端242。 該防銲層250係形成於該第二介電層23〇上並覆蓋該些 第二層引腳240。其中，該些第一凸塊接合端221與該些第 二凸塊接合端241均係形成於該覆晶接合區2〇1内且顯露於 該防銲層250之外。此外，在本實施例中，該些第一外接合 > 端222與該些第二外接合端242係扇出狀分散並顯露於該防 銲層250之外，如同該些第一凸塊接合端221與該些第二凸 塊接合端241這般均顯露在該多層電路捲帶結構2〇〇之上表 面’以供封裝高密度顯示器驅動晶片2〇。 再如第4圖所示，較佳地，該些第一凸塊接合端221與 該些第二凸塊接合端241係為條狀且均具有突出於該防銲層 250之高度，例如可利用電鍍製程形成該些第一凸塊接合端 . 221與該些第二凸塊接合端241之增厚突出部位。因此，該 防輝層250能選用非感光性不導電油墨，以網板印刷或鋼板 印刷等方式簡單形成於該多層電路捲帶結構2〇〇之上表面 (即覆晶接合面），不需要曝光顯影（無黃光製程）以形成開孔 (如第5圖所示），或是不需要使用貼附方式的孔對位，即可 顯露預定面積之該些第一凸塊接合端221與該些第二凸塊接 合端241，並能防止該些第一凸塊接合端221與該些第二凸 塊接合端241間的橋接導致電性短路並能避免微粒污染至該 覆晶接合區201引起之電信干擾。故利用連接不同層引腳且 9 1295097 突出之第一凸塊接合端221與第二凸塊接合端241可達到該 防銲層250之低成本形成又在覆晶接合時有利於凸塊21之 内接腳接合。 如第5及6圖所示，一晶片20係具有矩陣排列或多排（兩 排以上）排列的凸塊2 1，可覆晶接合於該多層電路捲帶結構 200之該覆晶接合區201，該些凸塊21係接合至該些連接於 不同層引腳且突出之第一凸塊接合端221與第二凸塊接合端 241。在本實施例中，該些第一凸塊接合端221與該些第二 凸塊接合端241之增厚突出部位係為短條狀，其長度可略大 於該些凸塊21，而其寬度係可略小於該些凸塊2 1。並可點 塗或其它方式將一封膠體40形成於該多層電路捲帶結構 200與該晶片20之間，以製成一薄膜覆晶封裝構造（如第6 圖所示）。因此，在内引腳間距可縮小之製程能力内可以在 覆晶接合區201内增加凸塊接合端221、241之數量或間距， 即在同一覆晶接合區201之區域内可容納更多凸塊接合端 221、241之數量，使得該多層電路捲帶結構2〇〇能應用於更 高解析度或更高性能的COF(薄膜覆晶封裝）產品。或者，當 凸塊21接合端之數量固定時，引腳設計空間變大，故利用 位在不同層之第一層引腳22〇與第二層引腳24〇可使該些第 一凸塊接合端221與該些第二凸塊接合端241之間隔亦隨之 變大’不需要使用高精度機台即可進行覆晶接合作業。 以上所述，僅是本發明的較佳實施例而已，並非對本發 明作任何形式上的限制，雖然本發明已以較佳實施例揭露如 上然而並非用以限定本發明，任何熟悉本頊技術者，在不 .1295097 脫離本發明之中請專利範圍内，所作的任何簡單修改 性變化與修飾’皆涵蓋於本發明的技術範圍内。 ， 【圖式簡單說明】 第1圖：習知薄膜覆晶封裝構造之截面示意圖。 第2圖：習知薄膜覆晶封裝構造之電路捲帶結構之截面示意 圖- 第3圖 習知薄膜覆晶封裝構造之電路捲帶結構與晶片結合 之透視示意圖。 第4圖 第5圖 依據本發明之一較佳實施例，一種薄膜覆晶封裝構 造之多層電路捲帶結構之截面示意圖。 第6圖 依據本發明之一較佳實施例，該多層電路捲帶結構 與一晶片結合之透視示意圖。 依據本發明之一較佳實施例，一種薄膜覆晶封裝構 造使用該多層電路捲帶結構之截面示意圖。 主要元件符號說明】 10 晶片 11 凸塊 20 晶片 21 凸塊 30 封膠體 40 封膠體 100 單層電路捲帶 101 覆晶接合區 110 介電層 120 弓1腳 121 130 防銲層 131 開孔 200 210 多層電路捲帶結構 第一介電層 201 220 第一層引腳 221 第一凸塊接合端 222 121凸塊接合端 2 0 1覆晶接合區 11 1295097 230第二介電層 240第二層引腳 241第二凸塊接合端242第二外接合端 250防銲層As in Section 5*, the multilayer circuit tape structure 2 has a flip-chip bonding region 201 on its upper surface, which is approximately the same size as the active surface of the same wafer (as shown in Figure 6). And as shown in FIG. 4, the multilayer circuit tape structure 200 includes a first dielectric layer 21, a plurality of first layer pins 220, a second dielectric layer 23, and a plurality of second layers. Pin 24〇 and a solder mask 25〇. The first dielectric layer 210 and the second dielectric layer 23 are used as carriers of the first layer pins 220 and the second layer pins 24q, and the material thereof may be PI (P〇lyimide, poly Yttrium imine). The first _ layer pins 22 are formed on the first dielectric layer 21 ,, and each of the first layer pins 22 has a first bump bonding end 221 and a first outer layer. Engaged end 222. The second dielectric layer 230 is formed on the first dielectric layer 21 and covers the first layer pins 220. The second layer 5 pin 24 is formed on the second 8 /1295097 dielectric layer 230 and the second layer pins 240 are separated by the second dielectric layer 23 One layer of pins 22 is electrically isolated. Wherein, each of the second layer of the arching foot 24 has a second bump engaging end 241 and a second outer engaging end 242. The solder resist layer 250 is formed on the second dielectric layer 23 and covers the second layer pins 240. The first bump bonding ends 221 and the second bump bonding ends 241 are both formed in the flip chip bonding region 2〇1 and exposed outside the solder resist layer 250. In addition, in the embodiment, the first outer bonding ends 222 and the second outer bonding ends 242 are fan-shaped and dispersed outside the solder resist layer 250, like the first bumps. The bonding end 221 and the second bump bonding ends 241 are all exposed on the upper surface of the multilayer circuit tape structure 2 ' for packaging the high-density display to drive the wafer 2 . As shown in FIG. 4 , the first bump engaging ends 221 and the second bump engaging ends 241 are strip-shaped and each has a height protruding from the solder resist layer 250 , for example, The first bump bonding end 221 and the second bump bonding end 241 are formed by the plating process. Therefore, the anti-corrosion layer 250 can be selected from the non-photosensitive non-conductive ink, and is simply formed on the upper surface of the multilayer circuit tape structure 2 (ie, the flip-chip bonding surface) by screen printing or steel plate printing. Exposure development (no yellow light process) to form an opening (as shown in FIG. 5), or the hole alignment of the attachment method is not required, so that the first bump joint ends 221 of the predetermined area are exposed The second bumps are joined to the end 241, and the bridging between the first bump engaging ends 221 and the second bump engaging ends 241 is prevented from causing an electrical short circuit and particle contamination is prevented from being contaminated into the flip chip bonding region. Terrestrial interference caused by 201. Therefore, the low-cost formation of the solder resist layer 250 can be achieved by the first bump bonding end 221 and the second bump bonding end 241 which are connected to the different layer pins and 9 1295097, and the bump 21 is facilitated during the flip chip bonding. The inner feet are engaged. As shown in FIGS. 5 and 6, a wafer 20 having bumps 2 1 arranged in a matrix or in a plurality of rows (two rows or more) is flip-chip bonded to the flip chip bonding region 201 of the multilayer circuit tape structure 200. The bumps 21 are bonded to the first bump engaging end 221 and the second bump engaging end 241 which are connected to the different layer pins and protrude. In this embodiment, the thickened protruding portions of the first bump engaging end 221 and the second bump engaging ends 241 are short strips, and the length thereof may be slightly larger than the bumps 21, and the width thereof The system may be slightly smaller than the bumps 2 1 . A glue 40 may be formed between the multilayer circuit tape structure 200 and the wafer 20 by spotting or other means to form a thin film flip chip package structure (as shown in Fig. 6). Therefore, the number or pitch of the bump bonding ends 221, 241 can be increased in the flip chip bonding region 201 within the process capability in which the inner pin pitch can be reduced, that is, more convex can be accommodated in the region of the same flip chip bonding region 201. The number of block bonding ends 221, 241 allows the multilayer circuit tape structure 2 to be applied to higher resolution or higher performance COF (Film Foil Packaging) products. Alternatively, when the number of the bonding ends of the bumps 21 is fixed, the pin design space becomes large, so the first bumps can be made by using the first layer pins 22 and the second layer pins 24 of the different layers. The distance between the joint end 221 and the second bump joint ends 241 also increases. The flip chip bonding operation can be performed without using a high-precision machine. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The present invention has been disclosed in the preferred embodiments, but is not intended to limit the present invention. All of the simple modifications and modifications made in the scope of the present invention are not included in the technical scope of the present invention. [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view of a conventional film flip chip package structure. Fig. 2 is a schematic cross-sectional view showing a circuit ribbon structure of a conventional film flip chip package structure. Fig. 3 is a perspective view showing a circuit ribbon structure of a conventional film flip chip package structure in combination with a wafer. Fig. 4 is a cross-sectional view showing a multilayer circuit ribbon structure of a film flip chip package structure in accordance with a preferred embodiment of the present invention. Figure 6 is a schematic perspective view of the multilayer circuit ribbon structure in combination with a wafer in accordance with a preferred embodiment of the present invention. In accordance with a preferred embodiment of the present invention, a thin film flip chip package construction uses a cross-sectional schematic view of the multilayer circuit tape structure. Main component symbol description] 10 wafer 11 bump 20 wafer 21 bump 30 sealant 40 sealant 100 single layer circuit tape 101 flip chip junction 110 dielectric layer 120 bow 1 foot 121 130 solder mask 131 opening 200 210 Multilayer circuit tape structure first dielectric layer 201 220 first layer pin 221 first bump bonding end 222 121 bump bonding end 2 0 1 flip chip bonding region 11 1295097 230 second dielectric layer 240 second layer Foot 241 second bump joint end 242 second outer joint end 250 solder mask
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