JPH06168985A - Packaging structure of semiconductor element - Google Patents

Packaging structure of semiconductor element

Info

Publication number
JPH06168985A
JPH06168985A JP43A JP32010292A JPH06168985A JP H06168985 A JPH06168985 A JP H06168985A JP 43 A JP43 A JP 43A JP 32010292 A JP32010292 A JP 32010292A JP H06168985 A JPH06168985 A JP H06168985A
Authority
JP
Japan
Prior art keywords
semiconductor element
opening
film carrier
resin
flexibility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP43A
Other languages
Japanese (ja)
Inventor
Toshiaki Ishii
利昭 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP43A priority Critical patent/JPH06168985A/en
Publication of JPH06168985A publication Critical patent/JPH06168985A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To partially reinforce a film carrier having flexibility by building a layer of a reinforcing material to arrest flexibility around the resin cladding and on the cladding itself of the film carrier which comprises two or three highly flexible layers. CONSTITUTION:An opening 4a is formed in a preset part of a flexible film 4, upon which a group of lead wires 3a are formed with a conductor wiring 3 and part of it extending to the opening 4a, thereby forming a two-layer film carrier 9. Here, the size of the opening 4a is formed slightly larger than that of a semiconductor element 1 and, onto the opposite side of the surface on which this semiconductor 1 is mounted, a reinforcing material 6 having an opening 6a which is larger than that opening is glued with an adhesive 7 and fixed. As a result, high dimensional stability and improved flatness are obtained at the reinforced part.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、可撓性を有するフイル
ムキャリア上に半導体素子を一体に搭載するための実装
構造の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a mounting structure for integrally mounting a semiconductor element on a flexible film carrier.

【0002】[0002]

【従来の技術】近年、半導体素子を多数個使用するデバ
イス,機器の開発が促進されてきている。これらにおい
ては、その最終的な製品の仕様に応じて多数個のIC,
LSIを所定の面積を有する基板上に高密度にしかも薄
型に搭載する必要が生じてきている。
2. Description of the Related Art In recent years, development of devices and equipment using a large number of semiconductor elements has been promoted. In these, a large number of ICs, depending on the specifications of the final product,
It has become necessary to mount the LSI on a substrate having a predetermined area with high density and thinness.

【0003】従来の半導体素子の実装構造においては、
IC,LSIはDILやフラットパック型のパッケージ
にモールドされたものやフイルムキャリアを使用したT
ABにモールドするものが周知であり、実装時には周囲
のリード群から切断した半導体素子(集積回路)を比較
的厚い回路基板上に平面的に搭載していた。 このよう
に基板に対して平面的に半導体素子を実装する構造で
は、どうしても平面的な占有面積が大きくなる欠点があ
るため基板が大きなものとなる。そのため1枚の基板を
複数に分割しそれぞれの基板をフレキシブル基板によっ
て接続し、互いに積層配置構成とすること等によって占
有面積の解消を行っていた。
In a conventional semiconductor element mounting structure,
ICs and LSIs are molded in DIL or flat pack type packages, or T using a film carrier.
It is well known to mold to AB, and at the time of mounting, a semiconductor element (integrated circuit) cut from a peripheral lead group is planarly mounted on a relatively thick circuit board. In such a structure in which the semiconductor elements are mounted on the substrate in a plane, there is a drawback that the occupied area in a plane is inevitably large, so that the substrate becomes large. Therefore, one board is divided into a plurality of boards, each board is connected by a flexible board, and the boards are laminated to each other to eliminate the occupied area.

【0004】しかしながらこのような実装においては、
新たに回路基板を分割する工程やフレキシブル基板を接
続する工程が増えるため、前記半導体素子の実装工程も
含めて実装コストが上昇するとともに、それぞれの接続
時における信頼性を向上させることが難しくなる欠点を
有する。併せて、近年では集積回路の高集積化が進行し
ていることもあって前記半導体素子から引き出されるリ
ード群も多数となり、前記のようにパッケージにモール
ドされる実装構造はもとより、TABにモールドしたも
のから切り離して実装するものにおいても、信頼性を向
上させることは極めて困難である。
However, in such an implementation,
Since the steps of newly dividing the circuit board and connecting the flexible board are increased, the mounting cost including the mounting step of the semiconductor element is increased and it is difficult to improve the reliability at the time of each connection. Have. At the same time, in recent years, as the degree of integration of integrated circuits has advanced, the number of leads to be pulled out from the semiconductor element has become large, and not only the mounting structure that is molded in the package as described above but also the TAB is molded. It is extremely difficult to improve the reliability even in the case where the device is mounted separately from the device.

【0005】したがって近年において信頼性を向上させ
る実装構造として、前記TABにモールドする半導体素
子のフイルムキャリアをそのまま可撓性を有する印刷回
路基板として使用し、通常の印刷回路基板に接続した
後、随時折り曲げ形成するものが一部で採用されること
がある。
Therefore, in recent years, as a mounting structure for improving reliability, a film carrier of a semiconductor element molded in the TAB is used as it is as a printed circuit board having flexibility, and after being connected to an ordinary printed circuit board, it can be used at any time. Some of them are formed by bending.

【0006】[0006]

【発明が解決しようとする課題】前記TABそのもの
を、目的とする回路基板へ直接実装する構造では、フイ
ルムキャリアの復元しようとする自己弾性力によって上
記折り曲げ実装する際には所定の形状を維持することが
困難になる。そのため、折り曲げる際の曲率が大きく取
られ、フイルムキャリアの面積を必要以上に取られるこ
とがあった。上記欠点はフイルムキャリアを薄型化し、
自己弾性力を弱く設定した柔軟性のあるフイルムキャリ
アを用いれば、その曲率を小さいものとすることができ
るが、今度は半導体素子搭載部付近の平面度が維持し難
くなり寸法安定性がなく実装が困難になる。
In the structure in which the TAB itself is directly mounted on the intended circuit board, a predetermined shape is maintained when the TAB is mounted by the self-elasticity of the film carrier to restore it. Becomes difficult. Therefore, a large curvature may be required when the film is bent, and the film carrier may have an unnecessarily large area. The above-mentioned drawbacks make the film carrier thinner,
If a flexible film carrier with weak self-elasticity is used, its curvature can be made small, but this time it becomes difficult to maintain the flatness in the vicinity of the semiconductor element mounting part, and there is no dimensional stability. Becomes difficult.

【0007】本発明は上記欠点を除去するためのもので
あり、柔軟性を有するフイルムキャリアの部分的な補強
を図ることを目的とする。
The present invention is intended to eliminate the above-mentioned drawbacks, and an object of the present invention is to partially reinforce a flexible film carrier.

【0008】[0008]

【課題を解決するための手段】本発明は、少なくとも1
つの開孔部を有する可撓性を有するフイルムキャリア上
に形成され、前記開孔部へ突出するリード線群に半導体
素子の電極を接合し、半導体素子及びリード線群は樹脂
による被覆が行われる半導体素子の実装構造において、
前記可撓性を有するフイルムキャリアは柔軟性の高い2
層もしくはそれと同等の柔軟性のある3層で形成され、
該樹脂による被覆の周囲及び任意の箇所においては前記
の柔軟性を阻止する補強部材を積層することを特徴とす
る実装構造を提供するものである。
SUMMARY OF THE INVENTION The present invention comprises at least one
An electrode of a semiconductor element is bonded to a lead wire group formed on a flexible film carrier having two openings and protruding to the opening, and the semiconductor element and the lead wire group are covered with a resin. In the mounting structure of the semiconductor element,
The flexible film carrier has high flexibility.
It is formed of three layers or layers with flexibility equivalent to it,
It is intended to provide a mounting structure characterized in that a reinforcing member for preventing the flexibility is laminated around the coating with the resin and at an arbitrary position.

【0009】[0009]

【作用】本発明によれば、柔軟性のあるフイルムキャリ
アによって基板の折り曲げ実装が容易になるとともに、
半導体素子及びリード線群の樹脂被覆周囲に補強材を積
層することによって折り曲げた先の半導体素子周囲の部
分における平面度が向上するとともに外力に対する寸法
安定性も良好な結果を得ることができるものとなる。
According to the present invention, the flexible film carrier facilitates the bending and mounting of the substrate, and
By laminating the reinforcing material around the resin coating of the semiconductor element and the lead wire group, it is possible to improve the flatness in the bent portion around the semiconductor element and to obtain good dimensional stability against external force. Become.

【0010】[0010]

【実施例】以下、本発明の一実施例を示す。図1におい
て4は例えばポリイミド,ガラスエポキシ,ポリエステ
ル等のフイルムからなる可撓性フイルムであり、所定部
分に開口部4aが形成され、フイルム上には導体配線3
とこの導体配線3の一部が開口部4aに延長してリード
線群3aを形成し、2層型のフイルムキャリア9が形成
されている。リード線群3aには半導体素子1の電極部
へバンプ2を介して接合する。ここで該開口部4aの大
きさは半導体素子1よりもわずかに大きく形成し、この
半導体素子1取り付け面の反対側には該開口部よりも大
きな開口部6aを有する補強材6を接着剤7により張り
付け固定している。該半導体素子1及び補強材6の取り
付け後、両開口部4a,6aには樹脂5が充填され被覆
されるものである。
EXAMPLE An example of the present invention will be described below. In FIG. 1, reference numeral 4 denotes a flexible film made of, for example, a film of polyimide, glass epoxy, polyester or the like, an opening 4a is formed at a predetermined portion, and a conductor wiring 3 is formed on the film.
A part of the conductor wiring 3 extends into the opening 4a to form a lead wire group 3a, and a two-layer type film carrier 9 is formed. The lead wire group 3a is bonded to the electrode portion of the semiconductor element 1 via the bump 2. Here, the size of the opening 4a is formed slightly larger than that of the semiconductor element 1, and a reinforcing material 6 having an opening 6a larger than the opening is provided on the opposite side of the mounting surface of the semiconductor element 1 with an adhesive 7. It is attached and fixed by. After mounting the semiconductor element 1 and the reinforcing material 6, both openings 4a, 6a are filled with resin 5 and covered.

【0011】該補強材6は材料としてポリイミド,ガラ
スエポキシ,ポリエステル等のフイルム,ベーク板,ガ
ラスエポキシ,ガラス等の板材の他,絶縁材料が用いら
れる、また接着剤7と合わせてポリイミド,ポリエステ
ル等のテープを用いても同等の効果を得ることができ
る。樹脂5は封止用樹脂であり、一般的には純度の高い
エポキシ系樹脂が用いられる。
The reinforcing material 6 is made of a film such as polyimide, glass epoxy, polyester or the like, a plate material such as a baking plate, glass epoxy or glass, or an insulating material. In addition to the adhesive 7, polyimide, polyester or the like is used. The same effect can be obtained by using the tape. The resin 5 is a sealing resin, and generally an epoxy resin having high purity is used.

【0012】また他の実施例として図2を示す。図面に
おいて図1と共通部分には同一符号を付与する。図2に
おいて4は可撓性フイルムであり、開口部4aを形成
し、フイルム上には導体配線3を構成しその一部は開口
部4aに延長してリード線群3aを形成し2層型のフイ
ルムキャリア9を構成する。リード線群3aには半導体
素子1の電極部へバンプ2を介して接合する。ここで該
開口部4aの大きさは半導体素子1よりもわずかに大き
く形成し、この半導体素子1取り付け面の反対側には前
記補強材6の代わりに補強樹脂8を印刷あるいは転写に
より構成する。該半導体素子1及び補強樹脂8の構成
後、両開口部4a,6aには樹脂5が充填され被覆され
るものである。
FIG. 2 shows another embodiment. In the drawing, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 2, reference numeral 4 denotes a flexible film, which has an opening 4a formed therein, a conductor wiring 3 is formed on the film, and a part of the conductive wiring 3 extends to the opening 4a to form a lead wire group 3a. The film carrier 9 of FIG. The lead wire group 3a is bonded to the electrode portion of the semiconductor element 1 via the bump 2. Here, the size of the opening 4a is formed slightly larger than that of the semiconductor element 1, and a reinforcing resin 8 is formed by printing or transferring instead of the reinforcing material 6 on the side opposite to the mounting surface of the semiconductor element 1. After the semiconductor element 1 and the reinforcing resin 8 are formed, both openings 4a and 6a are filled and covered with the resin 5.

【0013】該補強樹脂8としては導体配線3と直接接
触するために、エポキシ系,シリコン系,ポリイミド
系,ブタジエン系等の組成を用いることができ、これは
ソルダーレジストを代用してもよいものである。
Since the reinforcing resin 8 is in direct contact with the conductor wiring 3, a composition such as an epoxy type, a silicon type, a polyimide type or a butadiene type can be used, which may be replaced by a solder resist. Is.

【0014】尚、上記実施例では、一般的なフェースア
ップボンディングにおいての例を提示したがこれに限定
されるものではなく、フェースダウンボンディングの際
においては可撓性フイルム4に対して補強材6(補強樹
脂8)は当該実施例の逆側に配置してもよい。
In the above embodiment, an example of general face-up bonding is presented, but the present invention is not limited to this. In face-down bonding, the reinforcing material 6 is added to the flexible film 4. The (reinforcing resin 8) may be arranged on the opposite side of the embodiment.

【0015】更に該補強材6(補強樹脂8)を構成する
部分は半導体素子1実装のための開口部4a周辺に限定
するものではなく、他の実装体の配設時にその背面側に
構成しても有効なものである。
Further, the portion forming the reinforcing material 6 (reinforcing resin 8) is not limited to the periphery of the opening 4a for mounting the semiconductor element 1, but is formed on the back surface side when mounting another mounting body. But it is effective.

【0016】前記両実施例におけるフイルムキャリアは
2層構造のものを提示しその厚みは通常可撓性フイルム
が50μm以下,導体配線が15μm〜35μmとなり極
薄で柔軟性を有するものであるが、現在主流となってい
る可撓性フイルムと導体配線とその両者を張り付ける接
着層を有する3層構造のフイルムキャリアでも現在の7
5μm〜125μmの厚みを可撓性フイルムの薄肉化等に
より全体が50μm程度まで薄くできれば上記2層構造
の可撓性フイルムと同等の柔軟性を有するため、これに
限定することなしに代用することも可能である。
The film carrier in both of the above-mentioned embodiments is presented as a two-layer structure, and the thickness is usually 50 μm or less for the flexible film and 15 μm to 35 μm for the conductor wiring, which is extremely thin and flexible. The current mainstream is a three-layer film carrier having a flexible film, conductor wiring, and an adhesive layer for adhering both of them.
If the total thickness of 5 μm to 125 μm can be reduced to about 50 μm by thinning the flexible film, etc., it has the same flexibility as that of the above-mentioned two-layer structure flexible film. Is also possible.

【0017】[0017]

【発明の効果】以上のように、本発明によれば可撓性フ
イルム上に形成した導体配線,リード群上に半導体素子
を直接搭載し、TABフイルム基板を構成して液晶表示
パネル等に折り曲げた状態で直接構成することができる
ため電極の接続工程数を削減することができ配線距離を
短くすることもできて信頼性の高い実装構造を提供する
ことができ、この柔軟性のあるフイルムキャリアの所定
部分に補強材6(補強樹脂8)を構成し、当該部分を強
化することにより補強部分以外では従来と同様に高い柔
軟性を有し容易に折り曲げすることができるため、補強
部分では高い寸法安定性と平面度が向上し、実装自由度
が高く、実装面積の小さい実装構造を実現することがで
きるものである。
As described above, according to the present invention, the semiconductor element is directly mounted on the conductor wiring and the lead group formed on the flexible film, and the TAB film substrate is formed to be bent on the liquid crystal display panel or the like. The flexible film carrier can reduce the number of electrode connection processes, shorten the wiring distance, and provide a highly reliable mounting structure. The reinforcing material 6 (reinforcing resin 8) is formed in a predetermined portion of the above, and by strengthening the portion, the portion other than the reinforcing portion has high flexibility and can be easily bent, so that the reinforcing portion is high. The dimensional stability and the flatness are improved, the mounting flexibility is high, and the mounting structure having a small mounting area can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体素子の実装構造の一実施例
を示す断面図。
FIG. 1 is a sectional view showing an embodiment of a semiconductor element mounting structure according to the present invention.

【図2】本発明による半導体素子の実装構造の他の実施
例を示す断面図。
FIG. 2 is a sectional view showing another embodiment of the mounting structure of the semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1 半導体素子 3 導体配線 3a リード線群 4 可撓性フイルム 4a 開口部 5 樹脂 6 補強材 6a 開口部 7 接着剤 8 補強樹脂 1 Semiconductor Element 3 Conductor Wiring 3a Lead Wire Group 4 Flexible Film 4a Opening 5 Resin 6 Reinforcing Material 6a Opening 7 Adhesive 8 Reinforcing Resin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも1つの開孔部を有する可撓性
を有するフイルムキャリア上に形成され、前記開孔部へ
突出するリード線群に半導体素子の電極を接合し、半導
体素子及びリード線群は樹脂による被覆が行われる半導
体素子の実装構造において、 前記可撓性を有するフイルムキャリアは柔軟性の高い2
層もしくはそれと同等の柔軟性のある3層で形成され、
該樹脂による被覆の周囲及び任意の箇所においては前記
の柔軟性を阻止する補強部材を積層することを特徴とす
る半導体素子の実装構造。
1. A semiconductor element and a lead wire group, wherein an electrode of a semiconductor element is joined to a lead wire group formed on a flexible film carrier having at least one hole portion and protruding into the hole portion. In a semiconductor element mounting structure in which resin coating is performed, the flexible film carrier has high flexibility.
It is formed of three layers or layers with flexibility equivalent to it,
A mounting structure for a semiconductor element, characterized in that a reinforcing member for preventing the flexibility is laminated around the resin coating and at an arbitrary position.
【請求項2】 前記補強部材がポリイミド,ガラスエポ
キシ,ポリエステル等のフイルム素材、またはベーク
板,ガラスエポキシ,ガラス等の板材、またはポリイミ
ド,ポリエステル等のテープ、またはエポキシ系,シリ
コン系,ポリイミド系、ブタジエン系等の樹脂により形
成したことを特徴とする特許請求項の範囲第1項記載の
半導体素子の実装構造。
2. The reinforcing member is a film material such as polyimide, glass epoxy, polyester or the like, a bake plate, a plate material such as glass epoxy, glass or the like, a tape such as polyimide or polyester, an epoxy type, a silicon type, a polyimide type, The mounting structure for a semiconductor element according to claim 1, wherein the mounting structure is formed of a resin such as a butadiene resin.
JP43A 1992-11-30 1992-11-30 Packaging structure of semiconductor element Pending JPH06168985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP43A JPH06168985A (en) 1992-11-30 1992-11-30 Packaging structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP43A JPH06168985A (en) 1992-11-30 1992-11-30 Packaging structure of semiconductor element

Publications (1)

Publication Number Publication Date
JPH06168985A true JPH06168985A (en) 1994-06-14

Family

ID=18117732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP43A Pending JPH06168985A (en) 1992-11-30 1992-11-30 Packaging structure of semiconductor element

Country Status (1)

Country Link
JP (1) JPH06168985A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462412B2 (en) 2000-01-18 2002-10-08 Sony Corporation Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
KR100747393B1 (en) * 2003-04-25 2007-08-07 미쓰이 긴조꾸 고교 가부시키가이샤 Film carrier tape for mounting electronic part, process for producing the same, and screen for solder resist coating
WO2007119608A1 (en) * 2006-03-31 2007-10-25 Nec Corporation Printed circuit board, packaging board, and electronic device
JPWO2007058096A1 (en) * 2005-11-18 2009-04-30 日本電気株式会社 Mounting board and electronic equipment

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462412B2 (en) 2000-01-18 2002-10-08 Sony Corporation Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
KR100747393B1 (en) * 2003-04-25 2007-08-07 미쓰이 긴조꾸 고교 가부시키가이샤 Film carrier tape for mounting electronic part, process for producing the same, and screen for solder resist coating
JPWO2007058096A1 (en) * 2005-11-18 2009-04-30 日本電気株式会社 Mounting board and electronic equipment
JP5088138B2 (en) * 2005-11-18 2012-12-05 日本電気株式会社 Mounting board and electronic equipment
US8625296B2 (en) 2005-11-18 2014-01-07 Nec Corporation Mount board and electronic device
US8913398B2 (en) 2005-11-18 2014-12-16 Nec Corporation Mount board and electronic device
WO2007119608A1 (en) * 2006-03-31 2007-10-25 Nec Corporation Printed circuit board, packaging board, and electronic device
US8119924B2 (en) 2006-03-31 2012-02-21 Nec Corporation Wiring board, packaging board and electronic device

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