TWI344199B - Inter-connecting structure for semiconductor device package and method of the same - Google Patents
Inter-connecting structure for semiconductor device package and method of the same Download PDFInfo
- Publication number
- TWI344199B TWI344199B TW096131727A TW96131727A TWI344199B TW I344199 B TWI344199 B TW I344199B TW 096131727 A TW096131727 A TW 096131727A TW 96131727 A TW96131727 A TW 96131727A TW I344199 B TWI344199 B TW I344199B
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- Prior art keywords
- substrate
- die
- semiconductor package
- interconnect structure
- package structure
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description
99 九、發明說明: 【發明所屬之技術領域】 線封tr有關一種半導體封裝,特別是關於—種内連 【先前技術】 高效能積體電路封裝已是熟知的技術。 積體電路封裝之改昱以媒斗甘拍+ 系而求趨使 制m k升錢及電性效能並降低尺寸及 半導體元件領域中,元件之密度持續增加, ==小。高密度元件之封裝或交互連接技術的需 增加,以符合上述情況。一般而言,在覆晶接合 銲錫凸塊陣列係形成於晶粒表面上。銲錫凸塊之 用銲錫化合材料配置於銲錫罩幕層,以產生所需 塊之圖案。晶粒封裝之功能包含電源分配、訊號分 =二::、保護及支撐等。由於半導體結構趨向複雜化, “專統技術,例如導線架封裝、軟性封裝、剛性 =術,已無法達成於晶粒上產生具有高密度元件之小型晶 封裝提供相對於封裝表面區域之高密度連 旋式訊號路徑,傳統結構具有高阻抗以及不 ^熱,因此導致較差散熱能力。隨著封裝密度之增加, 將内部元件產生之熱導出益形重要。 覆晶技術為電性連接晶粒至黏合基板(例如印刷電路 電I㈣連接晶粒技術,晶粒主動面受制於複數 :°知技㈣位於晶片旁側)。電訊連接位於覆 1344199 I > r. aa=主動表面上以作為端點,凸塊包含錫球以及/或銅、金 使知"其機械與電性遠掠於其4 ' / θ 連接於基板之上。位於增層後之錫球14 「有凸塊高度約為5(M。。微米,晶粒!。反轉配置於基板
L表面’其凸塊12對準基板之接觸塾15,填充材料U j /凸鬼12如第一圖所不。若為錫球14,其將被焊於基 =妾合塾16上’錫接合成本不高,但當基於熱機械應力所 致毀損或孔洞時’其會增加阻抗。此外,錫球為錫合金 $成,以鉛為基礎之材質將因為環保意識且會產生有毒物 質之釋放而不再受到歡迎。一般,填充材質被用以降低介 於晶片與基板間熱膨脹所產生之熱應力。 再者,由於一般封裝技術必須先將晶圓上之晶粒分割 =個別晶粒,再將晶粒分別封裝,因此上述技術之製程; 分費時。因為晶粒封裝技術與積體電路之發展有密切關 聯’因此封裝技術對於電子元件之尺寸要求越來越高。基 於上述之理由,現今之封裝技術已逐漸趨向採用球閘陣列 鲁封裝(BGA)、覆晶球閘陣列封裝、晶片尺寸封裝、晶圓級 封裝之技術。應可理解「晶圓級封裝(WLp)」指晶圓上所 有封裝及交互連接結構,如同其他製程步驟,係於切割為 個別晶粒之前進行。一般而言,在完成所有配裝製程或封 裝製程之後,由具有複數半導體晶粒之晶圓中將個別半導 體封裝分離。上述晶圓級封裝具有極小之尺寸及良好之 性。 美國專利旒第6,271,469號所揭露之具有増層(build up layer)之封裝結構便遇到上述熱膨脹係數不匹配之問 6 1344199 ·
V 題’如第二圖所示。此電子封裝包含晶粒1〇2,具有主動 面,金屬接觸墊103位於主動表面。封裝膠體112配置於 晶粒102周遭。其中所述之封裝膠體至少具有—表面大致 上與晶粒主動表面相當平整。第一介電層118配置於封裝 膠體m與晶粒102之上。至少—導電層124配置於第—t 介電層118之上。導電層124連接晶粒之主動面。第二介 電層126以及第三介電層136分別形成於晶粒1〇2之上。 介層穿孔132形成於第二介電層126中以利於搞合導電層 124。接合塾134連接介層穿孔132以及锡球n 曰 上述技術牽涉過多堆疊增層形成於晶粒表面上。1不 只需要平坦化增層步驟,更須高精度之光微影設備以^成 =裝步驟,但其也易於毀損晶粒表面。主要在於欠缺 層於晶粒與錫球間’因此此架構造成低良率以及可靠度問 題。 因此:本發明提供一種具有内連結構之覆晶結構已克 服上述問題以提供較佳可靠度。 【發明内容] 本=之一目的係在於提供一種擴散式晶圓級封裝 (fan-out WLP),其具有 ’ 數匹配。 円良丰以及良好熱膨脹係 本發明之另-目的係在於提供一種封裝 構,以增進可靠度與減小裝置之體積。 本*fX明揭露—種本墓辦#爿* 上故 含:一A +導體封A結構之内連線結構,包 基板,具有預先製作之導線於其中;—晶粒,具有 1344199 • · « ♦ v. ·接觸墊於主動表面;一黏合材質,將該晶粒黏合於該基板 -之上,其中該基板包含通孔貫穿該基板以及該黏合材質; V電材質填充於該通孔以利於連接該接觸墊以及該導線。 更包含核心黏膠位於該晶粒背面與該黏合材質上,以及導 電凸塊耦合该導線;支撐基板位於該核心黏膠之上。導體 層位於該核心黏膠及/或該晶粒背面之上。其中該導體層包 含銅箔、濺鍍或電鍍之銅/鎳/金合金。其中更包含斜頂結 構之封膜單元,位於該晶粒以及該黏合材質之上,斜頂結 構之角度約為水平面起30_60度。其中該封膜單元為液態 化合物或封膠化合物。 :種形成半導體封裝之内連線結構之方法,包含: 提供一基板具有電路或導線位於其中; 形成點合材質於其上; 以微對位之置放裝置將晶粒配置於該黏合材質之上, 以覆晶方式配置; • ^成核〜黏膠於•背面,於填入該晶粒週遭空隙; 形成通孔於該基板以曝露接觸墊; 以物理氣相沉積或化學氣相沉積製作金屬種子層於該 接觸墊上; 形成光阻於該晶粒之上; 以電鍍製程製作導電枒暂仏e7丨丄 〒电何貝於该通孔中,以形成該内連 線結構並與該接觸墊耦合。 更包含熱處理該黏合枒暂, 何質’在曝路出金屬墊之後包含 清潔該金屬墊。JL中兮人β ^ 八甲名金屬導電包含Ti/Cu,Cu/Au 8 1344199 • l w 、-Cu/Nl/Au或Sn/Ag/Cu。完成内連結構後更包含去除光阻 • 以及回蝕刻該金屬層。 ” 【實施方式】 本發明將配合其較佳實施例與後附之圖式詳述於下。 應可理解,本發明中之較佳實施例係僅用以說明,而非用 以限定本發明。此外,除文中之較佳實施例外,本發明亦 可廣泛應用於其他實施例,並且本發明並不限定於任何實 施例,而應視後附之申請專利範圍而定。 • 本發明揭露一種半導體封裝之結構,包含基板、導線、 以及金屬内連線結構,如第三圖所示。 ’’ 第三圖係為本發明基板100之截面,基板1〇〇可以為 金屬、玻璃、陶瓷、塑膠、PCB或ρι。厚度約為4〇, 微米。可為多層結構基板,晶粒1〇5藉由黏合材質ιι〇黏 於其上,黏合材質110其具有彈性以吸收熱應力。黏著材 質110得只覆蓋晶粒大小之區域。内連線結構i i 5回填形 ⑩成於基板1 00内之通孔,得藉由雷射鑽孔製作。内連線結 構115耦合到晶粒之預定接觸金屬墊! 〇8,其材質可為鋁 墊、銅墊或其他金屬,其係於形成增層後製作。導線 配至於基板之底部或上部表面,且耦合到内連線結構 115。導電凸塊125耦合至導線12〇之末端。 第三圖所示,導線12〇形成於基板底下(或内部卜例 如,導線120以金、銅、銅鎳或類似材質組成。可以藉由 電鍍技術、塗佈或蝕刻方法製作。銅電鍍程序持續進行直 到所遇之厚度。導線120延伸出承載晶粒之區域,核心黏 9 1344199 • >
膠層(core paste material)130, 且覆蓋晶粒、基板或黏合材質 物、矽膠或環氧樹脂構成。 例如彈性核心黏膠層係填充 110。可以藉由樹脂、化合 參閱第四圖,其顯示另一實施例,支撐基板135貼附 於核心黏膠層(core paste material) 13〇,以提供封裝體之支 撐、,另一例為導體層140塗佈或覆蓋於核心黏膠層㈣上 作為散熱it。可以藉由銀膠枯合銅㈣片製作、麵技術、 電鍍銅/鎳/金製作導體層140,如第五圖所示。 Φ參㈣六圖’封膜單^ 145係利用液態化合物或封勝 化合物:代核心黏膠層130。晶粒高度約為5〇_2〇〇微米, 自封膜单7G 145至晶粒表面尺寸大約3(Μ〇()微米。基板與 枯著材質厚度合計大約4(Μ⑼微米。因此整個封裝體之厚 度約為大約120-400微米。值得注意者係為封膜單元145 具有斜頂,傾斜結構之角度θ約為3〇_6〇度,進而提供較 佳之散熱路控。 參閱第七® ’基板(圓或矩形)〗⑼具有電路形成於其 内’黏合材質(較好為具有彈性以吸收熱應力’基於熱膨服 係數介於基板與以粒不匹配問題)nG,塗佈於基板,隨 之熱處理該黏合材質11G。晶粒1G5以微對準裝置置放於 土板100之上了步驟為自晶粒背面印刷或塗佈核心黏 膠層"0。導體層140 一般則是則是利用面板壓合技術 (panel bonding)使其與晶粒背面相互結合。隨之执處理以 形成“Panel wafer” ,如第七圖所示。下—步驟為使用雷 射穿孔技術鑿穿通孔(亦可於面板壓合前實施),以及形成 1344199 金屬種子層,隨後採用光阻形成通孔及連接至基板電路。 隨後去除光阻後’使用電鑛及敍刻種子層以利於製作内連 線結構115。需注意者金屬墊可為鋁墊或其他金屬墊,通 孔區域非為製作凸塊之區域,參第八圖以及第九圖。 隨後,凸塊置於基板之上,且加以紅外線熱流步驟以 製作傳輸終端結構,如第十圖所示。執行面板級(Panenevel) 測試以及切割所述(PI)基板以及核心黏膠層以分離個別單 體。 第十一圖係為根據本發明之内連線結構之一實施例, 其包含晶粒105,具有金屬接觸墊1〇2位於主動表面,黏 合材質110位於晶粒105底面,具有預製電路之基板1〇〇 用以承載晶粒105,以及通孔結構115形成於基板内,導 電材質經由通孔結冑115搞合至晶& 1G5之金屬接觸塾 102以聯繫基板電路。 本發明提供簡單之製程,無需傳統增層結構於卩扣引 wafer level内(增層意謂電路’其預先製作於基板以預防在 增^過程中損壞晶片)。且本發明無須對準工具,對準圖案 通常=於基板表面於製作電路過程中。晶粒主動面貼附於 基板彈性黏合層’本發明無須底部填充材質,且本發明具 =電路之PI基板採大面積面板。且本發明採用簡易塗佈乾 "光阻’而非溼式光阻’以形成導電材質於通孔區域。晶 Ϊ = ΐ裝於t中,只需開孔金屬電區域,因此主動心 極m 此*構不但低成本且高良率’且封裝體之尺寸 、(…須錫球高度’石夕晶圓易於研磨至非常薄而不會受限 11 1344199 I · 於錫球尚度因素之考慮)。 :=藉由採用彈性黏合層做為緩衝層以釋放應 二ί 靠度。填充金屬(鋼或錫)全覆蓋通孔,以 強化機械力。其顯示於基板2方向無熱應力衝擊,盆盘目 =層=術=不同。介於ΡΙ基板與PCB母板之熱膨脹 ’其>肖除㈣題’因此’相較於傳統技術 明有效克服熱管理問題。 本發明以較佳實施例說明如上’然其並非用以限定本 t明所主張之專利權制圍。其專㈣護範圍當視後附之 :凊專利範圍及其等同領域而定。凡熟悉此領域之技蔹 ^在不脫離本專利精神或範圍内,所作之更動或潤錦, f屬於本發明所揭示精神下所完成之等效改變或設計,且 應包含在下述之申請專利範圍内。 【圖式簡單說明】 第一圖係為根據先前技術之剖面示意圖。 第一圖係為根據先前技術之剖面示意圖。 第二圖係為根據本發明之剖面示意圖。 第四圖係為根據本發明之剖面示意圖。 第五圖係為根據本發明之剖面示意圖。 第六圖係為根據本發明之示意圖。 第七至十圖係為根據本發明之製程示意圖。 第十圖係為根據本發明之内連結構剖面示意圖。 【主要元件符號說明】 先前技搞ί 12 1344199 I t 晶粒10、填充材料11、凸塊12、基板13、錫球14、 接觸墊15、基板接合墊16、晶粒102、金屬接觸墊103、 封裝膠體112、第一介電層118、導電層124、第二介 電層126、介層穿孔132、接合墊134、第三介電層136、 錫球13 8 本發明 基板100、晶粒105、接觸金屬墊108、黏合材質110、 内連線結構115、導線120、導電凸塊125、核心黏膠 130、支撐基板135、導體層140、封膜單元145
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Claims (1)
1344199 I » ,.十、申請專利範圍: ' 1 · 一種半導體封裝結構之内連線結構,包含: ' 一基板,具有預先製作之導線於其中; --晶粒’具有接觸塾於主動表面,該主動表面 係斩下; 一黏合材質,形成於該基板之上,而該晶粒黏合 於該黏合材質之上,其中該基板包含通孔貫穿 該基板以及該黏合材質以裸露該接觸墊; • 導電材質填充於該通孔以作為内連線結構並 連接該接觸墊以及該導線。 2.如請求項 1所述之半導體封裝結構之内連線 結構,更包含核心黏膠位於該晶粒與該黏合材 質上,以及包含導電凸塊耦合該導線。 I 3.如請求項 2所述之半導體封裝結構之内連線 結構,更包含支撐基板位於該核心黏膠之上。 4. 如請求項 2所述之半導體封裝結構之内連線 結構,更包含導體層位於該核心黏膠之上。 5. 如請求項 4所述之半導體封裝結構之内連線 結構,其中該導體層包含銅箔、濺鍍或電鍍之 銅/鎳/金合金。 14 1344199 « · 6. 如請求項 1所述之半導體封裝結構之内連線 結構,其中更包含斜頂結構之封膜單元,位於 該晶粒、以及該黏合材質之上。 7. 如請求項 6所述之半導體封裝結構之内連線 結構,其中更包含斜頂結構之角度約為3 0 - 6 0 度。 8. 如請求項 6所述之半導體封裝結構之内連線 結構,其中該封膜單元包含液態化合物或封膠 化合物。 9. 一種形成半導體封裝結構之内連線結構之方 法,包含: 提供一基板具有電路於其中; ^ 形成黏合材質於該基板之上; 以微對位之置放裝置將晶粒配置於該黏合材 質之上,以覆晶方式配置; 形成核心黏膠於該晶粒背面,與填入該晶粒週 遭空隙; 形成通孔於該基板以暴露接觸墊; 以物理氣相沉積或化學氣相沉積製作金屬種 子層於該接觸墊上; 15 1344199 t 0 形成光阻於該晶粒之上; 以電鍍製程製作金屬導體於該通孔中,以形成 該内連線結構與該接觸墊耦合。 10. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法,更包含熱處理該黏合材質。 11. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法,更包含在曝露金屬墊之後清 潔該金屬塾。 12. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法,其中該金屬種子層包含 Ti/Cu, Cu/Au, Cu/Ni/Au 或 Sn/Ag/Cu。 13. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法,更包含去除光阻以及回蝕刻 該金屬層。 16
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US11/773,993 US20090008777A1 (en) | 2007-07-06 | 2007-07-06 | Inter-connecting structure for semiconductor device package and method of the same |
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JP (1) | JP2009033153A (zh) |
KR (1) | KR20090004775A (zh) |
CN (1) | CN101339928B (zh) |
DE (1) | DE102008031358A1 (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI492344B (zh) * | 2013-04-09 | 2015-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8446243B2 (en) * | 2008-10-31 | 2013-05-21 | Infineon Technologies Austria Ag | Method of constructing inductors and transformers |
TW201131705A (en) * | 2010-03-03 | 2011-09-16 | Advanced Chip Eng Tech Inc | Conductor package structure and method of the same |
US20130181227A1 (en) * | 2012-01-12 | 2013-07-18 | King Dragon International Inc. | LED Package with Slanting Structure and Method of the Same |
US20130214418A1 (en) * | 2012-01-12 | 2013-08-22 | King Dragon International Inc. | Semiconductor Device Package with Slanting Structures |
CN102867759B (zh) * | 2012-08-17 | 2015-04-29 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
US9331038B2 (en) | 2013-08-29 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor interconnect structure |
US9859265B2 (en) * | 2014-06-06 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and methods of forming the same |
US10043769B2 (en) * | 2015-06-03 | 2018-08-07 | Micron Technology, Inc. | Semiconductor devices including dummy chips |
KR102492733B1 (ko) | 2017-09-29 | 2023-01-27 | 삼성디스플레이 주식회사 | 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법 |
US11404365B2 (en) * | 2019-05-07 | 2022-08-02 | International Business Machines Corporation | Direct attachment of capacitors to flip chip dies |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069407A (en) * | 1998-11-18 | 2000-05-30 | Vlsi Technology, Inc. | BGA package using PCB and tape in a die-up configuration |
US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
US6271469B1 (en) | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US6569712B2 (en) * | 2001-10-19 | 2003-05-27 | Via Technologies, Inc. | Structure of a ball-grid array package substrate and processes for producing thereof |
SG115455A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
US20040088855A1 (en) * | 2002-11-11 | 2004-05-13 | Salman Akram | Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods |
US7309622B2 (en) * | 2005-02-14 | 2007-12-18 | Stats Chippac Ltd. | Integrated circuit package system with heat sink |
US20070096285A1 (en) * | 2005-11-02 | 2007-05-03 | Chin-Tien Chiu | Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor die |
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2007
- 2007-07-06 US US11/773,993 patent/US20090008777A1/en not_active Abandoned
- 2007-08-27 TW TW096131727A patent/TWI344199B/zh active
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- 2008-07-04 SG SG200805063-5A patent/SG148987A1/en unknown
- 2008-07-07 KR KR1020080065321A patent/KR20090004775A/ko not_active Application Discontinuation
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TWI492344B (zh) * | 2013-04-09 | 2015-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
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KR20090004775A (ko) | 2009-01-12 |
TW200903763A (en) | 2009-01-16 |
US20090008777A1 (en) | 2009-01-08 |
JP2009033153A (ja) | 2009-02-12 |
CN101339928B (zh) | 2011-04-06 |
DE102008031358A1 (de) | 2009-01-08 |
SG148987A1 (en) | 2009-01-29 |
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