TWI320574B - Address buffer and method for buffering address in semiconductor memory apparatus - Google Patents

Address buffer and method for buffering address in semiconductor memory apparatus

Info

Publication number
TWI320574B
TWI320574B TW096102207A TW96102207A TWI320574B TW I320574 B TWI320574 B TW I320574B TW 096102207 A TW096102207 A TW 096102207A TW 96102207 A TW96102207 A TW 96102207A TW I320574 B TWI320574 B TW I320574B
Authority
TW
Taiwan
Prior art keywords
address
semiconductor memory
memory apparatus
buffering
buffer
Prior art date
Application number
TW096102207A
Other languages
English (en)
Other versions
TW200735123A (en
Inventor
Sang-Kwon Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200735123A publication Critical patent/TW200735123A/zh
Application granted granted Critical
Publication of TWI320574B publication Critical patent/TWI320574B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW096102207A 2006-03-09 2007-01-19 Address buffer and method for buffering address in semiconductor memory apparatus TWI320574B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060022335A KR100695289B1 (ko) 2006-03-09 2006-03-09 반도체 메모리 장치의 어드레스 버퍼 및 어드레스 버퍼링방법

Publications (2)

Publication Number Publication Date
TW200735123A TW200735123A (en) 2007-09-16
TWI320574B true TWI320574B (en) 2010-02-11

Family

ID=38478769

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096102207A TWI320574B (en) 2006-03-09 2007-01-19 Address buffer and method for buffering address in semiconductor memory apparatus

Country Status (5)

Country Link
US (1) US7450463B2 (zh)
JP (1) JP5124136B2 (zh)
KR (1) KR100695289B1 (zh)
CN (1) CN101034587B (zh)
TW (1) TWI320574B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100904479B1 (ko) * 2007-06-27 2009-06-24 주식회사 하이닉스반도체 반도체 메모리장치 및 이의 어드레스 입력방법
KR100620645B1 (ko) * 2004-04-13 2006-09-13 주식회사 하이닉스반도체 동기 및 비동기 병용 모드 레지스터 세트를 포함하는ｐｓｒａｍ
EP2153328B1 (en) * 2007-05-25 2011-08-10 Freescale Semiconductor, Inc. Data processing system, data processing method, and apparatus
JP5262246B2 (ja) * 2008-03-31 2013-08-14 富士通セミコンダクター株式会社 半導体記憶装置およびメモリシステム
CN102681822B (zh) 2011-03-17 2016-06-15 中兴通讯股份有限公司 一种处理器地址缓冲管理的实现装置及方法
KR20130050852A (ko) * 2011-11-08 2013-05-16 에스케이하이닉스 주식회사 어드레스 디코딩 방법과 이를 이용한 반도체 메모리 장치
CN103137187B (zh) * 2011-11-28 2015-12-09 上海华虹宏力半导体制造有限公司 一种sram的旁路结构
KR20190121121A (ko) * 2018-04-17 2019-10-25 에스케이하이닉스 주식회사 반도체장치
US11132307B2 (en) 2018-05-25 2021-09-28 Rambus Inc. Low latency memory access

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107465A (en) 1989-09-13 1992-04-21 Advanced Micro Devices, Inc. Asynchronous/synchronous pipeline dual mode memory access circuit and method
JPH05342881A (ja) * 1992-06-04 1993-12-24 Nec Corp 記憶回路
US5592685A (en) * 1992-10-07 1997-01-07 Digital Equipment Corporation Synchronous/asynchronous partitioning of an asynchronous bus interface
KR960032662A (ko) * 1995-02-15 1996-09-17 구자홍 동기/비동기 버스 접속장치
US6128700A (en) * 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same
FI104858B (fi) * 1995-05-29 2000-04-14 Nokia Networks Oy Menetelmä ja laitteisto asynkronisen väylän sovittamiseksi synkroniseen piiriin
JP3244035B2 (ja) * 1997-08-15 2002-01-07 日本電気株式会社 半導体記憶装置
US6058451A (en) * 1997-12-22 2000-05-02 Emc Corporation Method and apparatus for refreshing a non-clocked memory
JPH11238380A (ja) 1998-02-19 1999-08-31 Ricoh Co Ltd 半導体メモリ回路
US6658544B2 (en) * 2000-12-27 2003-12-02 Koninklijke Philips Electronics N.V. Techniques to asynchronously operate a synchronous memory
US6920524B2 (en) * 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
JP2005108327A (ja) 2003-09-30 2005-04-21 Toshiba Corp 半導体集積回路装置及びそのアクセス方法
KR100620645B1 (ko) 2004-04-13 2006-09-13 주식회사 하이닉스반도체 동기 및 비동기 병용 모드 레지스터 세트를 포함하는ｐｓｒａｍ
KR100521048B1 (ko) * 2004-04-20 2005-10-11 주식회사 하이닉스반도체 슈도 스태틱램의 동작모드 제어방법 및 제어회로, 이를구비한 슈도 스태틱램 및 그의 동작모드 수행방법
JP2005342881A (ja) 2004-05-07 2005-12-15 Nitta Haas Inc 研磨パッド、研磨方法および研磨装置
US7245552B2 (en) * 2005-06-22 2007-07-17 Infineon Technologies Ag Parallel data path architecture

Also Published As

Publication number Publication date
TW200735123A (en) 2007-09-16
JP5124136B2 (ja) 2013-01-23
US20070211555A1 (en) 2007-09-13
KR100695289B1 (ko) 2007-03-16
US7450463B2 (en) 2008-11-11
JP2007242212A (ja) 2007-09-20
CN101034587B (zh) 2011-12-21
CN101034587A (zh) 2007-09-12

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees