TWI319614B - Bond pad structure - Google Patents

Bond pad structure

Info

Publication number
TWI319614B
TWI319614B TW095142417A TW95142417A TWI319614B TW I319614 B TWI319614 B TW I319614B TW 095142417 A TW095142417 A TW 095142417A TW 95142417 A TW95142417 A TW 95142417A TW I319614 B TWI319614 B TW I319614B
Authority
TW
Taiwan
Prior art keywords
bond pad
pad structure
bond
pad
Prior art date
Application number
TW095142417A
Other languages
English (en)
Other versions
TW200802753A (en
Inventor
Jong Chen
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200802753A publication Critical patent/TW200802753A/zh
Application granted granted Critical
Publication of TWI319614B publication Critical patent/TWI319614B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
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    • H01L2924/1901—Structure
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    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
TW095142417A 2006-06-19 2006-11-16 Bond pad structure TWI319614B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/455,090 US7459792B2 (en) 2006-06-19 2006-06-19 Via layout with via groups placed in interlocked arrangement

Publications (2)

Publication Number Publication Date
TW200802753A TW200802753A (en) 2008-01-01
TWI319614B true TWI319614B (en) 2010-01-11

Family

ID=38860739

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095142417A TWI319614B (en) 2006-06-19 2006-11-16 Bond pad structure

Country Status (3)

Country Link
US (1) US7459792B2 (zh)
CN (1) CN100505225C (zh)
TW (1) TWI319614B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680511B (zh) * 2018-11-23 2019-12-21 南亞科技股份有限公司 半導體結構及其製造方法
US10734338B2 (en) 2018-11-23 2020-08-04 Nanya Technology Corporation Bonding pad, semiconductor structure, and method of manufacturing semiconductor structure

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US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7934189B2 (en) * 2008-01-25 2011-04-26 Infineon Technologies Ag Method of making an integrated circuit including simplifying metal shapes
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8058707B1 (en) * 2008-03-03 2011-11-15 Xilinx, Inc. Semiconductor devices having redundant through-die vias and methods of fabricating the same
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
EP2105959A3 (fr) 2008-03-28 2011-03-02 STMicroelectronics (Crolles 2) SAS Procédé de formation de niveaux d'interconnexion d'un circuit intégré
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) * 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
KR20100060309A (ko) * 2008-11-27 2010-06-07 주식회사 동부하이텍 반도체 소자
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8748305B2 (en) * 2009-11-17 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for semiconductor devices
US20110161905A1 (en) * 2009-12-31 2011-06-30 Lorentz Solution, Inc. Layout Electromagnetic Extraction For High-Frequency Design And Verification
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
TWI412108B (zh) * 2011-01-03 2013-10-11 Himax Tech Ltd 接合墊結構以及積體電路晶片
CN102593069A (zh) * 2011-01-13 2012-07-18 奇景光电股份有限公司 接合垫结构以及集成电路芯片
JP5819218B2 (ja) * 2012-02-23 2015-11-18 ルネサスエレクトロニクス株式会社 半導体装置
US9236342B2 (en) * 2013-12-18 2016-01-12 Intel Corporation Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
US20150245548A1 (en) * 2014-02-26 2015-08-27 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
KR102435128B1 (ko) * 2015-09-16 2022-08-24 삼성전기주식회사 인쇄회로기판
CN108269776A (zh) * 2016-12-30 2018-07-10 应广科技股份有限公司 焊垫下电路结构及其制造方法
CN112687677A (zh) * 2019-10-18 2021-04-20 凌通科技股份有限公司 整合静电放电电路的焊垫以及使用其的集成电路

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FR2824954A1 (fr) * 2001-05-18 2002-11-22 St Microelectronics Sa Plot de connexion d'un circuit integre
JP3757143B2 (ja) * 2001-10-11 2006-03-22 富士通株式会社 半導体装置の製造方法及び半導体装置
JP3779243B2 (ja) * 2002-07-31 2006-05-24 富士通株式会社 半導体装置及びその製造方法
CN2641824Y (zh) * 2003-06-24 2004-09-15 威盛电子股份有限公司 复合式芯片构装基板
US7323784B2 (en) * 2005-03-17 2008-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Top via pattern for bond pad structure
JP4378352B2 (ja) * 2005-04-28 2009-12-02 キヤノン株式会社 周期構造体の製造方法
KR100790998B1 (ko) * 2006-10-02 2008-01-03 삼성전자주식회사 셀프 얼라인 더블 패터닝법을 사용한 패드 패턴 형성 방법 및 셀프 얼라인 더블 패터닝법을 사용한 콘택홀 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680511B (zh) * 2018-11-23 2019-12-21 南亞科技股份有限公司 半導體結構及其製造方法
US10734338B2 (en) 2018-11-23 2020-08-04 Nanya Technology Corporation Bonding pad, semiconductor structure, and method of manufacturing semiconductor structure

Also Published As

Publication number Publication date
US7459792B2 (en) 2008-12-02
US20070290361A1 (en) 2007-12-20
CN101093820A (zh) 2007-12-26
TW200802753A (en) 2008-01-01
CN100505225C (zh) 2009-06-24

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