TWI306370B - Coreless thin substrate with embedded circuits in dielectric layer and method for manufacturing the same - Google Patents

Description

1306370 IX. Description of the Invention: The present invention relates to a multilayer circuit board, and more particularly to a coreless thin substrate in which a wiring is fitted to a dielectric layer and a method of manufacturing the same. [Prior Art] Multi-layer boards are used in various types of electronic products as electrical signal transmission, power supply, and ground connection. With the miniaturization of electronic products, it is hoped that multilayer boards will become thinner and denser. Generally, a multi-layer circuit board can be classified into a laminating type and a build-up according to its manufacturing process. The so-called superimposing method is to combine a plurality of circuit boards composed of a bohed layer and a surface wiring layer through a thermal lamination step, and combine them into a multi-layer circuit board, and on the circuit boards. An insulating layer that is not completely polymerized is provided between them. The so-called layering method is in a core layer

An insulating layer and a plating circuit layer are formed by layer-by-layer printing on the circuit board of the surface wiring layer. Whether it is a laminated or layered type, it is necessary to use at least one circuit board containing a core "layer as a laminated monomer or a build-up carrier, so that the multilayer circuit board has a thick thickness. And since the surface of the core layer is one An uneven surface, so that the circuit layer formed on the core layer may also have an uneven If shape, and after forming a plurality of layers of the core layer, the insulating layer and the circuit layer layer by layer, the thickness of the multilayer circuit board cannot be controlled, and The surface of the multi-layer circuit board is not flat. For example, the national patent number 1236324 "the circuit board insulation layer structure and the method for forming the circuit board using the same" has disclosed the related laminated multi-type 1306370-layer circuit board and the build-up multilayer. Circuit board. In addition, National Patent Publication No. 585016 "Multiple-Layering Method and Structure of Printed Circuit Board" discloses a multilayer printed circuit board which is formed by mixing and stacking layers, but in the above-mentioned known multilayer circuit board structure The core layer must be used, and the lines are all embossed on the surface of the core layer, which has a detrimental effect on the thinning and flattening of the circuit board.

Figure 1 is a schematic cross-sectional view of a conventional laminated multi-layer circuit board. The multilayer circuit board 100 is composed of a plurality of core substrates i i thermally stacked, and an insulating layer 12 is disposed between the core substrates 110. Each core substrate 110 includes a core layer ln and a plurality of circuit layers 112 and 113 protruding from an upper surface and a lower surface of the core layer 111. The core substrate 110 is electrically connected by the via holes 14 in a core substrate 110. The same core substrate 110 is provided with circuit layers 112, 113. In the thermal lamination process, the insulating layer i 2 is an incompletely polymerized material layer (ie, B stage) to adhere to the core substrates 110, and the insulating layer 120 flows to fill the inner layer wiring layer.丨2, 113 and the gap between the via holes 114. However, the thickness of the insulating layer 120 for electrically insulating different core substrates 110 is uncontrollable. In addition, the conventional thermal stacking industry only achieves the mechanical bonding of different core substrates 110. After the thermal lamination, there is no electrical connection between the different core substrates 110, and a uniform perforation forming step is required to form a suitable through hole. 13A, the through hole 130 penetrates the core substrate 110 and the insulating layer 12, and a metal layer is plated in the through hole 130 to electrically connect the core substrates 110. Finally, the core substrate 110 is electrically connected. The outer side surfaces each form a solder mask 140 to form the multilayer circuit board. As a result, the manufacturing process of the multilayer circuit board 1QGg] of the conventionally-incorporated 1306370 is complicated, resulting in an increase in manufacturing cost and a thick thickness. SUMMARY OF THE INVENTION The main object of the present invention is to provide an n-th thin substrate in which a line is embedded in a dielectric layer, and a method of manufacturing the same, which utilizes a plurality of first patterned dielectric layers embedded with a plurality of lines And a second patterned dielectric layer having at least one embedded conductive element; wherein:

The second patterned dielectric layer is disposed between the first patterned dielectric layers: and electrically conductively turns the lines of the first patterned dielectric layers with the conductive elements to omit the conventional thermal layer The through-hole process after the combination has a thinner and flatter appearance. The second objective of the present invention is to provide a coreless thin substrate with a line embedded in a dielectric layer, a manufacturing method thereof, and a line fitting structure thereof, wherein the first patterned dielectric layers can be negative images (negative The ink-printing layer of the nozzle has a pattern image and the same layer of the same layer, so that the lines are embedded in the first patterned dielectric layers, and the first patterned dielectric layers The thickness of the lines and the lines embedded in the first patterned dielectric layers are such that the lines are barely exposed on the upper surface of the first patterned dielectric layers and a lower surface to facilitate the electrical connection of the lines and the conductive elements during thermal bonding without the need for complicated substrate processing steps. According to the present invention, a coreless thin substrate in which a wiring is embedded in a dielectric layer mainly includes a plurality of patterned-first patterned dielectric layers and a 1306370 to a second patterned dielectric with a conductive component. Electrical layer. The second patterned dielectric layer is disposed between the first patterned dielectric layers and is thermally laminated to enable the conductive elements to electrically conduct the first patterned dielectrics. I have these 'lines. Therefore, it is possible to omit the conventional through-hole process after thermal lamination and to have a thinner and flatter appearance. [Embodiment] An embodiment of the present invention is described below. As shown in FIG. 2, a coreless thin substrate 2 in which a wire is embedded in a dielectric layer mainly includes a plurality of first patterned dielectric layers 210 and at least one second patterned dielectric layer 220. The second patterned dielectric layer 22 is disposed between the first patterned dielectric layers 210. Each of the first patterned dielectric layers 21 is embedded with a plurality of lines 211, and the lines 211 are connectable to a plurality of interconnect pads 212 that are also embedded in the first patterned dielectric layers 210. . In addition, the first outermost patterned dielectric layer 21 is embedded with a plurality of first-outer pads 213 connecting the line IP paths 211. The first patterned dielectric layer 21 is relatively flat, because the wires 2, the interconnect pads 212, and the first external pads 213 are embedded in the first patterned dielectric layer 210. One of the upper surface 214 and the lower surface 215. In order to accurately form the embedded circuit 2 11, the first patterned dielectric layer 2 can be a negative image inkjet printing layer, and the pattern image is located on the same layer. The lines 211 are reversed, and the material thereof may be selected from non-conductive inks such as ρι (polyimine), PET, etc., or non-conductive pastes, and has multi-stage aging characteristics. And the lines 211 and the interconnects 212

9 1306370 and the first pad 2 ί 3 can be - positive image (pQsiti... _ (four) inkjet printing layer, the material can be selected with conductive ink, and the conductive ink can be composed of high content of fine conductive particles and A resin-based polymerization agent, wherein the conductive particles are selected from the group consisting of (4), copper powder, carbon powder or other (tetra) polymer, etc. #. The thickness of the first-patterned dielectric layer 2! The thicknesses of the lines 211, the interconnect pads 212, and the first external pads 213 of the first patterned dielectric layer 210 are uniform, and the thickness is about 8 to 5 μm, so that the The lines 211, the interconnect pads 212 and the first external pads 213 can be exposed on the upper surface 214 and the lower surface 215 of the first patterned dielectric layer 21 (as shown in FIG. 3C). The exposed surface 216) is electrically conductively connected to the upper and lower layers. The second patterned dielectric layer 220 is embedded with a plurality of conductive elements 221 electrically electrically connected to the first patterned dielectric layers. The lines 211 of the electrical layer 210. The conductive elements are selected from the group consisting of a conductor inspection, a money through hole and an inner connection pad. First, if a plated through hole is selected, it is preferable that the W conductive ink fills the hole, and the conductive elements are exposed on the upper surface 222 and the lower surface 223 of the first patterned dielectric layer 22. The material of the member 221 can be a conductive ink or a conductive metal. In the embodiment, the conductive elements 221 can be embedded in a plastic state, and the second patterned dielectric layer 220 can be embedded with other lines (not shown). And the lines should be unconnected or overlapped with the lines 211 of the first patterned dielectric layer 210 to prevent short circuit. Preferably, the second patterned dielectric layer 220 is a negative ink jet printing layer defining the positions and sizes of the conductive elements 221 in a predetermined manner such that the conductive elements 221 are aligned with the interconnections of the 1306370 first patterned dielectric layers 210 Pad 212 or the first external pads 213. The second patterned dielectric layer 22 can be selected from non-conductive ink or non-conductive glue (NCP or NCF, Non_Conductive Paste/Film). Preferably, 'second patterning The dielectric layer 22 can be a non-conductive glue, and the curing shrinkage can enhance the conductive elements The member 221 is in electrical contact with the interconnect pads 212 or the first external pads 213 of the first patterned dielectric layer 210.

The coreless thin substrate 200 may further include a first solder mask layer 241 formed on the first patterned dielectric layer 21 of the outermost layer, and at least partially exposed the first external pads 213. A first plating layer 251 is formed on one of the exposed surfaces of the first external pads 213. Preferably, the coreless thin substrate 200 further includes a third patterned dielectric layer 230 disposed on an outer side of the second patterned dielectric layer 22 and fitted with a plurality of second external connections. Pad 23 i. A second solder mask layer 242 is formed on the second patterned dielectric layer 230' and at least partially exposes the second outer turns 23 1 . A second plating layer 252 is formed on the exposed surface of the second external contacts 23 1 . Therefore, the coreless thin substrate 2 does not require a core layer and the embossed wiring has a thinner and flatter appearance. In addition, compared with the conventional laminated multi-layer circuit board, the coreless thin substrate 200 can achieve mechanical bonding and electrical conduction between the upper and lower layers when the thermal lamination is performed, and the through hole forming operation is not required after the thermocompression bonding. The process simplifies and reduces the cost of manufacturing' and has more space and flexibility in the layout and design of the circuit. The manufacturing method of the coreless thin substrate 200 is as follows: 11 1306370 As shown in FIG. 3A, the first patterned dielectric layer 21 is formed by inkjet printing on the carrier 31〇1, the first pattern. The dielectric layer 21 is an inkjet printing layer of a negative image, wherein the carrier 31 can be preferably a thermal release fUm to facilitate peeling of the process. During ink jet printing, the first patterned dielectric layer 2 is liquid coated in stage A and then prebaked to achieve partial polymerization such that the first patterned dielectric layer 210 becomes a b-stage characteristic. As shown in FIG. 3B, a plurality of lines 211 can be formed by inkjet printing, and the lines 211 are an inkjet printing layer of a positive image, which is fitted to the first patterning. Within the gap of the dielectric layer 210. Next, the transfer carrier 310 is removed as shown in FIG. 3C to form the first patterned dielectric layer 21A with the lines m interposed. Therefore, a patterned dielectric layer having various line variations can be fabricated by the above process. As shown in FIG. 4A, a second patterned dielectric layer 22 is formed by inkjet printing on another carrier 320, and the second patterned dielectric layer 22 is negative image (negative image). ) the inkjet printing layer. As shown in Fig. 4B, a plurality of via elements 221 are formed in the spaces of the second patterned dielectric layer 22A. The carrier 320 is removed to form the second patterned dielectric layer 220 with the conductive elements 22ι. As shown in FIG. 5A, the first patterned dielectric layer 21 and the second patterned dielectric layer 220 are thermally laminated in an environment of heating and pressing, wherein the first patterned dielectric layer 21 and the second patterned dielectric layer 220 are thermally laminated. The second patterned dielectric layer 22 is disposed between the first patterned dielectric layers 210. As shown in FIG. 5B, the first patterned dielectric layer 210 and the second patterned dielectric layer 22 12 1306370 can be completely polymerized. The lines 211 of the dielectric layer 21 are electrically patterned by the conductive elements 221 . . Finally, the coreless thin substrate 200 can be formed by forming the solder mask layers 241, 242 and the electric ore layers 25, 252 described above. The scope of the invention is defined by the scope of the invention, and the scope of the invention is intended to be embraced by the invention.

Any changes and modifications made within the scope. [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional laminated multi-layer circuit board. Fig. 2 is a cross-sectional view showing a coreless (tetra) type substrate in which a wiring is embedded in a dielectric layer in accordance with an embodiment of the present invention. 3A to 3C are diagrams showing a first patterned dielectric layer in which one of the coreless thin substrates is embedded in the inkjet printing process according to one embodiment of the present invention. A schematic view of the section in the middle. 4 to 4: A cross-sectional schematic view of a second patterned dielectric layer of a coreless thin substrate in which a conductive element is embedded in a forming process according to an embodiment of the present invention. Sections 5 to 5: A schematic cross-sectional view of the coreless thin substrate in a thermal lamination process according to a specific embodiment of the present invention. [Main component symbol description]

13 1306370

100 multilayer circuit board 110 core substrate 111 core layer 113 circuit layer 114 via hole 120 insulating layer 130 through hole 200 coreless thin substrate 210 first patterned dielectric layer 211 line 212 interconnect pad 214 upper surface 215 lower surface 220 Second patterned dielectric layer 221 conductive element 222 upper surface 230 third patterned dielectric layer 241 first solder mask layer 242 first metallurgy - fresh mask layer 251 first plating layer 252 second plating layer 310 carrier 320 carrier 112 140 213 216 223 231 circuit layer solder mask first outer pad bare surface lower surface second outer pad

14

Claims (1)

1306370 Case No. 95111566 Application for the month of the patent: η ν> Corrected the repair (Η) original 丨f Κ~卜 I A line is embedded in the dielectric layer ~ the coreless plate ΐ ϋ.ϋ反—,· contains: plural a first-patterned dielectric layer having a plurality of lines embedded therein; and at least one second patterned dielectric layer member; 'the system is embedded with a plurality of conductive elements=the second patterned dielectric layer The conductive elements are disposed between the first patterned electrical layers, and the conductive elements of the patterned dielectric layer electrically conduct the lines of the first patterned dielectric layers. 2. The coreless thin substrate of the dielectric layer of the first embodiment of the patent application, wherein the first patterned cold dielectric layer and the second patterned dielectric layer are thermally laminated Combine. 3. The coreless thin substrate of the dielectric layer according to the first aspect of the invention, wherein the first patterned dielectric layer is an ink jet printing layer. 4. A non-cardioid thin substrate in which a line as described in claim 3 is fitted to a dielectric layer, wherein the ink jet printing layer is a negative image ink jet printing layer. 5' The coreless thin substrate in which the wiring described in the first aspect of the patent application is fitted to the dielectric layer, wherein the missing line is an ink jet printing layer. 6. The non-plate thin substrate in which the circuit of the fifth embodiment of the patent application is embedded in the dielectric layer, wherein the lines are ink jet printing layers of a positive image. 7. If the application of the patent scope is the first line of the household, the line is embedded in the dielectric layer, no. 1306370, No. 95111566, the modified core board, the second patterned dielectric layer is a black jet column. Printed layer. 8. The coreless thin substrate of the dielectric layer is embedded in the dielectric layer according to the first aspect of the invention, wherein the thickness of the first patterned dielectric layer is corresponding to the thickness of the lines. For consistency. 9. The non-loyal thin substrate of the circuit of claim 8, wherein the lines are exposed on an upper surface and a lower surface of the first patterned dielectric layer. The coreless thin substrate of the dielectric layer is embedded in the dielectric layer, wherein the conductive components are exposed on an upper surface and a lower surface of the second patterned dielectric layer. . i. The coreless thin substrate in which the wiring according to the above-mentioned claim is embedded in the dielectric layer, wherein the second patterned dielectric layer is a non-conductive adhesive. 12. The coreless thin substrate of the dielectric layer according to the invention of claim 3, wherein the conductive elements are selected from one of a conductor plug, a plated through hole and an inner connecting pad. 13. The coreless thin substrate of the dielectric layer according to the first aspect of the invention, wherein the first patterned dielectric layer of the outermost layer is more fused to the plurality of connecting lines. External pads. 14. The coreless thin substrate of the dielectric layer according to claim 11 of the Shenqing patent scope, further comprising a solder mask layer formed on the outermost layer of the first patterned dielectric layer And at least partially revealing the external pads. 16 1306370 Doc. No. 95111566 月 Amendment The thin plate substrate of the circuit described in claim 14 is embedded in the dielectric layer, and further comprises a plating layer formed on the subsequent outer pads. The coreless thin substrate embedded in the dielectric layer according to the first aspect of the invention, further comprising a third patterned dielectric layer on an outer side of the second patterned dielectric layer. And a plurality of external pads are fitted. The non-angered thin-film substrate in which the circuit described in claim 16 is embedded in the dielectric layer, and further includes a solder mask layer formed on the third patterned dielectric layer and at least partially exposed. Some external pads. For example, the thin-plateless substrate of the dielectric layer is embedded in the dielectric layer, and the electro-acoustic layer is formed on the external pads. A method for manufacturing a coreless/seeking substrate in which a wiring is embedded in a dielectric layer, comprising: providing a plurality of first patterned dielectric layers, having a plurality of lines embedded therein; providing at least one second patterned dielectric a plurality of conductive layers; and a plurality of thermally conductive layers of the first patterned dielectric banks, wherein the second-patterned dielectric dielectric Π/糸 is set in the whistle-unloading & First patterning; between the electrical layers, and causing the conductive patterns to be electrically connected to the first patterned "electrical layer of the lines. 2〇, as claimed in claim 19 , the circuit of the '· is embedded in the dielectric layer 15 16 17 18 19 17 1306370 Case No. 95111566 Year of the Amendment 21, 22 23 24 25 26 No such thin plate substrate manufacturing method, the first round of the case The dielectric layer is formed on the carrier by inkjet printing. The method for manufacturing a coreless thin substrate in which the wiring is embedded in a dielectric layer according to claim 20, wherein the first patterning is performed. The dielectric layer is a negative image inkjet print layer. A method for manufacturing a coreless thin substrate in which a wiring according to the second aspect of the invention is incorporated in a dielectric layer, wherein the carrier is a thermal release film. The method for manufacturing a coreless thin substrate in which a line as described in item 9 is embedded in a dielectric screen, wherein the lines are formed by inkjet printing on the first patterned dielectric layer. A method of manufacturing a coreless thin substrate in which a line of the above-mentioned 23 is embedded in a dielectric layer, wherein the lines are positive image ink jet printing layers, as described in claim 19 a method for manufacturing a coreless thin substrate in which a circuit is embedded in a dielectric layer, wherein the thickness of the first patterned dielectric layer is such that the thickness of the corresponding lines is such that the lines can a method of manufacturing a coreless thin substrate in which a line as described in claim 19 is embedded in a dielectric layer, wherein the second patterning is performed on the upper surface and the lower surface of the first layer. Dielectric layer is printed by inkjet To. "The scope of the patent silk! The method for manufacturing a coreless thin substrate of a dielectric layer, wherein the conductive elements are bare 18 27 1306370, No. 95111566, a correction is exposed to the second patterned dielectric layer An upper surface and a lower surface. The method for manufacturing a coreless thin substrate in which a wiring according to claim 19 is embedded in a dielectric layer, wherein the second patterned dielectric layer is a non-conductive adhesive. 29. The method of manufacturing a coreless thin substrate in which a wiring according to claim 19 is incorporated in a dielectric layer, wherein the conductive components are selected from a conductor plug, a plated through hole, and an inner connection. One of the pads. A method for manufacturing a coreless thin substrate in which a line as described in claim 19 is embedded in a dielectric layer, wherein the first patterned dielectric layer of the outermost layer is further embedded A plurality of pads connecting the wires are provided. The manufacturing method of the wire as described in claim 3, wherein the wire is embedded in the thin plateless substrate, further includes: forming - soldering to the outermost layer First—patterned dielectric layer And to: the external mats. °卩显路1 as claimed in the scope of the patent application, the line is hosted in the manufacturing method of the thin plate-free substrate, and further includes: forming the external pads. ^ ^ ^ 33 The method of manufacturing a circuit according to claim 19, wherein the circuit is interspersed with a thin substrate, further comprising: providing - the first layer; the I electrical layer being located in the second patterned dielectric layer — The surface is fitted with a plurality of external mats. External 1 34. The manufacturing method of the line-fitting non-angered thin-film substrate as described in claim 33 of the patent application is provided. 3, Forming—Hui 19 1306370 Case No. 95111566 Amendment 35 36 37 38 39 40, 41, in the third patterned dielectric layer, and at least partially expose the external pads. The circuit according to claim 34 is embedded in the dielectric layer. The manufacturing method of the coreless thin substrate further comprises: forming an electric forging layer on the external pads. The circuit fitting structure of the coreless thin substrate comprises a patterned dielectric layer, after a plurality of circuit lines Combined with the patterned dielectric layer Wherein the patterned dielectric layer is an inkjet printing layer, and the thickness of the patterned dielectric layer is consistent with the thickness of the mating lines, so that the lines can be exposed to the patterned medium. The upper surface and the lower surface of the electrical layer. The wire fitting structure of the coreless thin substrate according to claim 36, wherein the ink jet printing layer is a negative image inkjet printing layer. The circuit of the coreless thin-film substrate described in claim 36 of the patent scope is the structure of the circuit, wherein the lines are ink-jet printing layers. The line fitting structure of the thin plate substrate is a positive ink jet printing layer. A coreless thin substrate as described in claim 36 or 39 of the patent specification: a line fitting structure wherein the circuits are conductive inks. - A conductive structure of a coreless thin substrate comprising a patterned dielectric layer 'a plurality of conductive elements are proud of the patterned dielectric layer', which makes the patterned dielectric layer an ink Printing the layer, and the thickness of the patterned dielectric layer is consistent with the thickness of the corresponding government-conducting pass element 20 1306370, number 95111566, so that the conductive elements can be exposed to the patterning One of the upper and lower surfaces of the dielectric layer. The conductive fitting structure of the coreless thin substrate according to claim 41, wherein the ink jet printing layer is a negative image ink jet printing layer. The conductive fitting structure of the coreless thin substrate according to claim 41, wherein the patterned dielectric layer is a non-conductive adhesive. The conductive fitting structure of the coreless thin substrate according to claim 41, wherein the conductive elements are conductive ink or conductive metal. twenty one