TWI304236B - Method for manufacturing stacked chip pakcage - Google Patents

Method for manufacturing stacked chip pakcage Download PDF

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Publication number
TWI304236B
TWI304236B TW091135655A TW91135655A TWI304236B TW I304236 B TWI304236 B TW I304236B TW 091135655 A TW091135655 A TW 091135655A TW 91135655 A TW91135655 A TW 91135655A TW I304236 B TWI304236 B TW I304236B
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Taiwan
Prior art keywords
substrate
bonding
semiconductor wafer
manufacturing
package
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TW091135655A
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English (en)
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TW200410346A (en
Inventor
Yon Kim Ji
Iii Moon Ki
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Hynix Semiconductor Inc
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Publication of TW200410346A publication Critical patent/TW200410346A/zh
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Publication of TWI304236B publication Critical patent/TWI304236B/zh

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1304236 _案號91135655_年月日__ 五、發明說明（1) 【本發明所屬之技術領域】 本發明係關於半導體封裝的製造方法，尤其是關於具 有多數疊層半導體構造的疊層晶片封裝的製造方法者。 【先前技術】 配合電子機器輕薄而短小化的趨勢，做為其核心元件 的封裝之高密度化與高結實化也漸成重要的因素。又在電 腦中，由於記憶容量之增加，雖然如大容量RAM及快閃記 憶體的晶片尺寸自然會增大，但以上述情形，封裝之小型 化傾向，乃成研究之對象。 於是，為了減小封裝尺寸而提出的各種方案例中，含 裝有複數的晶片或封裝的疊層晶片封裝（Mu 11 i Ch i p Package MCP)，疊層晶片模組（Mult i Chip Module MCM) 等，主要皆屬於將半導體晶片及封裝平面排列於基板上而 包裝的方法，所以製作上有其限度。 為了克服這種限度，曾有將同一記憶容量的晶片整體 的以複數個疊層封裝方式的提議，通常稱為疊層晶片封裝 (Stacked Chip Package)0 目前前述疊層晶片封裝的技術已成為簡單化的過程， 故可減低疊層晶片封裝的製造成本，又有適於大量生產的 優點。但另一方面，卻有因晶片尺寸的增大而設計封裝内 部的引線時感覺空間不足的缺失。 第1圖為傳統技術疊層晶片封裝製造方法的剖面圖。 如第1圖所示，傳統技術的疊層晶片封裝1 0 0，其具有的構 造為利用基板1 1 0，將多數的半導體晶片1 2 0、1 3 0、1 4 0以 平面包裝成封裝者。
第7頁 1304236 案號 91135655 曰 修正 五、發明說明（2) 在該基板11 0頂面的包裝領域，以黏著劑11 4將各該半 導體晶片1 2 0、1 3 0、1 4 0黏貼，而在基板1 1 0黏著面的反 面，形成多數結合焊節點1 2 2、1 3 2、1 4 2的構造。此時， 以階梯狀疊層各該半導體晶片1 2 0、1 3 0、1 4 0。又該等結 合焊接點1 2 2、1 3 2、1 4 2則以多數個形成於各該半導體晶 片1 2 0、1 3 0、1 4 0頂面邊緣部份。 各該結合焊接點1 2 2、1 3 2、1 4 2各對應於在基板1 1 0頂 面形成的導電性圖案1 1 2，而以結合線1 2 4、1 3 4、1 4 4做電 氣上的連接。 於是為了保護半導體晶片1 2 0、1 3 0、1 4 0及在基板1 1 〇 頂面形成的電氣性連接部份，以環氧樹脂系的封止用樹脂 封止而形成封裝驅體1 5 〇。 基板1 1 0上的導電性圖案1丨2，係為一種互聯用配線 ，，用以電氣上連接半導體晶片1 2 0、1 3 0、1 4 0與焊接球 1 6 0者。 • 半導體晶片1 2 0、1 3 0、1 4 0可利用形成於基板1 1 0頂面 的電路圖案互相做電氣上的連接，亦可將導電性圖案丨i 2 與半導體晶片的焊接點i 2、2 2、3 2同與結合線1 2 4、1 3 4、 1 4 4結合’因而形成電氣上的連接。 但是以傳統技術疊層的半導體晶片尺寸互有不同，如 此則當結合焊節點只係面向上（f ace-up)疊層排列於邊緣 部份的半導體晶片時，遇到半導體晶片尺寸相同，或結合 焊節點排列於半導體晶片之中央部份的場合，傳統方法就 無法適用。 又’在傳統技術上無法增加疊層半導體晶片的引線
1304236 _案號91135655_年月曰 修正_ 五、發明說明（3) 數，只好將頂部的半導體晶片與底部半導體晶片的CS腳針 (chip select pin)予以割裂為二，一根連接於CS腳針， 另一根連接於NC針來使用，因此須要NC針的存在。 【本發明之内容】 本發明乃為了解決上述傳統問題而開發者，本發明之 目的在提供一種疊層晶片封裝的製造方法，其能在中心部 份個別形成結合焊接點，而以面向上（face up)及面向下 (face down)方式疊積同一尺寸的半導體晶片者。 為了達成上述目的，本發明之製造疊層晶片封裝之方 法，其包含的步驟為：1.在中心部位排列有多數第一結合 焊接點的第一半導體晶片上，貼附具有第一中心窗的第一 基板；2.形成第一結合線以連接該第一半導體晶片與該第 一基板；3.在中心部位排列有多數第二結合焊接點的第二 半導體晶片上9貼附具有第二中心窗的苐二基板，4.形成 第二結合線以連接該第二半導體晶片與該第二基板；5 ·互 相貼著所得第一與第二半導體晶片的背面；6.形成第三結 合線以連接該第一與第二基板；7.塑造一成形體以覆蓋於 該第一、第二與第三結合線；及8.黏貼一導電性球於該第 一基板，為其特徵。 【本發明之實施方式】 本發明之目的，其他特徵及優點，可參照文後附圖詳 讀本發明具體實施例的詳細描述，即可瞭解。 第2A圖至第2F圖為說明本發明疊層晶片封裝製造方法 第一實施例的流程剖面圖。 如第2A圖所示，首先在排列有多數個第一結合焊接點
1304236 _案號91135655_年月曰 修正_ 五、發明說明（4) (未圖示）於中央部位的第一半導體晶片1 0上，貼附形成有 第一中央窗口 1 3的第一基板1 2，接著利用第1結合線1 4連 接第一結合焊接點與第一基板1 2。 其次如第2B圖所示，在排列有多數個第二結合焊接點 (未圖示）於中央部位的第二半導體晶片2 0上，貼附形成有 第二中央窗口 2 3的第二基板2 2。之後利用第二結合線2 4連 接第二結合焊接點與第二基板2 2。此時第一與第二半導體 晶片1 0與2 0之尺寸相同。 其次如第2C圖所示，將以前流程中所得第一與第二半 導體晶片相結合。此時該結合流程中係將第一與第二半導 體晶片的背面（即形成有電路之面之背面）互相接合。 其次，如第2D圖所示，利用第三結合線30連接第一與 第二基板1 2與2 2。此時所用第一、第二及第三結合線1 4、 2 4、3 0之材質為鋁或金。 此後，如第2 E圖所示，對所得之物進行成形工程而形 成覆蓋各第一、第二及第三結合線14、24、3 0的成形體 32° 接著如第2F圖所示，貼附導電性焊球34於第一基板1 2 底面的焊球埠（未圖示）上。焊球琿的直徑有1 5 0〜 1 7 0 // m。又導電性焊球3 4直徑有1 0 0 // m〜1 m m。焊球3 4的 主成份為Sn，再加上Pb、In、Bi、Au、Zn、Cu或Sb中之任 何一個而形成者。 第3A至3E圖為說明本發明疊層晶片封裝製造方法第二 實施例的流程剖面圖。 如第3A圖所示，該製造方法係利用如膠帶（未圖示）等
第10頁 f ty 1304236 __案號91135655_年月曰 絛正__ 五、發明說明（5) 在中心部位排列有多數個第一結合焊接點（未圖示）的第一 半導體晶片1 0 0上貼附形成有中心窗口 1 0 3的第一基板 102° 接著貼附第一堰1 0 6於第一基板1 0 2上後，以結合工程 形成連接第一結合焊接點與第一基板1 0 2用之第一結合線 1 0 4。此時第一堰1 0 6扮演防止此後之封裝成形流程中傾斜 或曝露第一半導體晶片100之角色。 其次，如第3B圖所示，利用如膠帶等在中心部位排列 有多數個第二結合焊接點（未圖示）的第二半導體晶片2 0 0 上貼附形成有第二中心窗口 2 0 3的第二基板2 0 2。此後貼附 第二堰2 0 6於第二基板2 0 2上後，以結合工程形成連接第二 結合焊接點與第二基板2 0 2用之第二結合線2 0 4。此時第二 堰2 0 6扮演防止此後之封裝成形流程中第二半導體2 〇 〇產生 模製溢料（mold flash)之角色。又第一與第二堰1〇 6與206 係利用抗焊或絕緣物質形成，此時該第一與第二堰1 〇 6、 2 0 6之厚度維持在2 0 // m〜1匪，以防止在接下去之流程中 成形混合物之流失。 接下去如第3 C圖所示，將已完成成形的第一及第二半 導體晶片1 〇 0、2 0 0的背面互相貼著後，利用結合工程形成 連接第二與第一基板2 0 2與1 0 2用的第三結合線2 3 0。 其次如第3E圖所示，將以前流程中所得物施以成形工 程形成成形體2 5 0以覆蓋各第一及第二半導體晶片1 〇 〇、 200、弟一、第二及第三結合線104、204、230。此時該成 形工程中如弟3D圖所示，須防止起因於上、下模子262、 26 0表面與第一與第二堰106、20 6之接觸而在面向上之方
第11頁 1304236 -案号虎 91挪咖 车月日 修正 五、發明說明（6) ' ' " 向因不受歡迎之成形料流移而引起第一及第二半導體晶片 1 0 0、2 0 0之傾斜或曝露，並抑制面向上方向的模製溢料 產生。 下模2 6 0與第二堰2 0 2間的空隙應保持很小，而以膠帶 貼著於第二半導體晶片方向而使該晶片免受損傷並防止模 製溢料之產生。 、 此後貼著導電性焊球2 5 2於第二基板之焊球埠（未圖 示）上。焊球埠之直徑在丄5 〇〜7 〇 〇// m之間。又導電性焊球 2 5 2之直色 追加Pb、In、Bi、Au、Zn、Cu或Sb中之一而形成者了 ^ 在本發明的第一與第二實施例中，將在中心部位 有多數個結合焊接點而具同一尺寸的第一與第二半導雕曰 片之背面互相貼著’然後進行結合線工程及成形工程。曰曰 •如上揭說明，將在中心部位形成有結合焊接球的 尺寸之各半導體晶片背面互相接著並形成多數個疊厣， 此可得以最小面積擴大記憶體密度。 9 本發明在不脫離其要旨的範圍内可做多種變更而每 大& 〇 果 以上業已舉實施例做了 並未被上揭實施例所限定， 屬具有普通的知識者，均可 做修飾與變更。 本發明的詳細描述。但本發明 在本發明所屬技術領域内)凡 在不脫離本發明構想與精神而
1304236 _案號91135655_年月曰 修正_ 圖式簡單說明 第1圖為說明以傳統技術製造疊層晶片封裝之方法的 剖 面圖 ； 第2A至2F圖為說明本發明疊層晶片封裝製造方法第一 實施例的流程剖面圖； 第3A至3E圖為說明本發明疊層晶片封裝製造方法第二 實施例的流程剖面圖。 【圖中元件編號與名稱對照表】
1 0、2 0 :半導體晶片 1 2、2 2 :基板 1 0 0、2 0 0 :第一半導體晶片 1 0 2 :第一基板
103 、2 0 3 :中心窗口 104 ^ 2 0 4、2 3 0 ： 結合 線 106 :第一堰 110 :基板 112 :導電性圖案 114 :黏貼劑 120 、130、 140： 半導 體晶 片 122 、132、 142： 結合 焊節 點 124 > 134〜144： 結合 線 13： 中心窗口 14 ： 結合線
第13頁 C S. 1 1304236 _案號91135655_年月日_修正 圖式簡單說明
第14頁 150 : 封裝驅體 160 : 焊接球 20 ： 半導體晶片 2 0 2 : 第二堰 2 0 6 : 第二堰 23 ： 中心窗 24 ： 結合線 252 導電性焊球 260 下模子 262 上模子 30 ： 結合線 32 ： 成形體 34 ： 導電性焊球

Claims (1)

1304236 _案號91135655_年月日__ 六、申請專利範圍 1 . 一種製造疊層晶片封裝之方法，其步驟為： 在中心部位排列有多數第一結合焊接點的第一半導體 晶片上5貼附具有弟一中心窗的弟一基板， 形成第一結合線以連接該第一半導體晶片與該第一基 板； 在中心部位排列有多數第二結合焊接點的第二半導體 晶片上’貼附具有苐二中心窗的第二基板； 形成第二結合線以連接該第二半導體晶片與該第二基 板； 互相貼著所得第一與第二半導體晶片的背面； 形成第三結合線以連接該第一與第二基板； 塑造一成形體以覆蓋於該第一、第二與第三結合線； 及 黏貼一導電性球於該第一基板； 其中，該方法更包含在形成有該第一及第二中心窗的 第一及第二基板背面分別形成第一及第二位置固定用堰之 步驟。 2 .如申請專利範圍第1項之製造疊層晶片封裝之方 法，其中所述第一及第二位置固定用堰係利用抗焊物質 者。 3.如申請專利範圍第1項之製造疊層晶片封裝之方 法，其中所述第一及第二位置固定用堰的厚度為20/z m〜 1 mm °
第15頁 3 1304236
-^左圖 代表符號簡單說明： 12： 基 板 14： 結 合 線 22 ： 基 板 24： 結 合 線 32 ： 成 形 體 五、（一）、本案代表圖為··農 (二）、本案代表圖之元件 1 〇:半導體晶片 1 3 :中心窗 2 〇 =半導體晶片 2 3 ·中心窗 3 0 :結合線 3 4 :導電性焊球 五、英文發明摘要（發明名稱：METHOD FOR MANUFACTURING STACKED CHIP PACKAGE) the i nput/output block unit and the bottom serial/parallei shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal
第3頁 1304236 _案號91135655_年月日_ 六、指定代表圖 第5頁
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CN1430251A (zh) 2003-07-16
US6818474B2 (en) 2004-11-16

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