TWI303403B - Display driving device and display apparatus comprising the same - Google Patents

Display driving device and display apparatus comprising the same Download PDF

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TWI303403B
TWI303403B TW094146606A TW94146606A TWI303403B TW I303403 B TWI303403 B TW I303403B TW 094146606 A TW094146606 A TW 094146606A TW 94146606 A TW94146606 A TW 94146606A TW I303403 B TWI303403 B TW I303403B
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Taiwan
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signal
display
voltage
gradation
gradation voltage
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TW094146606A
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Chinese (zh)
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TW200643862A (en
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Takahiro Harada
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Casio Computer Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Description

1303403 九、發明說明： 【發明所屬之技術領域】 本發明有關一種顯示驅動裝置及其驅動控制方法、以及 具有此種驅動裝置之顯示裝置，尤其有關一種將基於複數 個色階電壓之顯示訊號電壓施加於顯示面板之各訊號線， 以使該顯示面板顯示圖像及其驅動控制方法、以及具有此 種驅動裝置之顯示裝置。 【先前技術】 ® 近年來，液晶顯示裝置在非常普遍之數位攝影機、數位 相機等拍攝機器，或行動電話、個人數位秘書（PDA)等可攜 式機器的領域，多作爲用來顯示圖像、文字資訊等的顯示 裝置（顯不器）’也多作爲電腦等資訊終端、電視等影像機 器之監視器、顯示器。這種用途之液晶顯示裝置，係輕薄， 可以低耗電化，顯示畫質也優異。 此種液晶顯不裝置之液晶顯示面板大多使用主動矩陣型 液晶顯示面板，係將複數條掃描線及複數條訊號線分別正 ® 交地配置，並於各交點附近配置液晶像素。此種主動矩陣 型液晶顯示面板，在經由開關元件（例如TFT :薄膜電晶體） 連接於訊號線之像素電極（顯示像素）、與和該像素電極相 對向地配置之共通電極之間塡充液晶，在2個電極間形成 電場，藉以驅動液晶。 具有此種主動矩陣型液晶顯示面板之液晶顯示裝置具 有：R G B解碼器’用以自外部所供給之影像訊號（複合視頻 訊號）萃取R、G、B各色之顯示資料；及訊號驅動器，用以 對各訊號線施加基於R G B解碼器所輸出之顯示資料之顯示 1303403 資料訊號所對應之顯示訊號電壓。 此種訊號驅動器在顯示資料爲數位訊號之情況下具有用 以生成複數個色階電壓的色階電壓生成電路，該複數個色 階電壓用來生成顯示訊號電壓。又，液晶被反轉驅動，故 此色階電壓之電位，極性以既定周期反轉而構成。又，根 據顯示資料之色階値來選擇複數個色階電壓之任一者，將 所選擇之色階電壓所對應之顯示訊號電壓施加給各訊號 線。 Φ 另一方面，在液晶顯示裝置之訊號驅動器之領域，已知 一種技術：將液晶顯示面板高解析化，在訊號線數增加之 情況下，將複數條訊號線分割爲複數個，將相對應之顯示 訊號電壓以分時之方式輸出，並切換施加於分割後之每一 個訊號線，藉以將液晶顯示面板以分時之方式驅動。 在具有上述般色階電壓生成電路之訊號驅動器之情況 下，爲了根據顯示資料之色階値來選擇在色階電壓生成電 路所生成之複數個色階電壓，將所選擇之色階電壓施加於 Φ 各訊號線，故於各色階電壓施加線設置與各訊號線相對應 之複數個開關元件。此開關元件使用電晶體等，許多電晶 體設於各色階電壓施加線，此等許多電晶體相關之負載容 量從全體來看是大容量。因此，色階電壓之電位之極性反 轉後，色階電壓施加線之電位穩定（收斂）在既定電位之 前，耗費一些時間。 【發明内容】 具備此種色階電壓生成電路之訊號驅動器’在適用上述 般分時驅動之情況下，在1水平掃描期間對各訊號線施加 •1303403 顯示訊號電壓的施加時間（寫入_ 變短。此外，色階電壓之電位之 之電位穩定在既定電位之前耗費 電位穩定之狀態下對一開始要被 線的施加時間，亦即寫入時間變 造成顯示畫質之劣化。 又’爲了能以如此短的施加時 的色階電壓，故提高了訊號驅動 φ 下，有訊號驅動器之電力消耗量 本發明係顯示驅動裝置，根據 於複數條訊號線及複數條掃描線 示像素的顯示面板；以及具有此 本發明具有可以抑制顯示畫質之 增加的優點。 用於獲得上述優點的本發明之 色階電壓生成部，生成前述顯示 • 個色階電壓，以基於前述顯示資 時序來反轉前述色階電壓之極性 設於前述複數條訊號線中既定數 數個色階電壓來生成前述顯示資 並對前述既定數目之每一條訊號 電壓；前述色階電壓生成部之反 序，係設定於比下次之前述水平 在對前述複數條訊號線施加前述 F間）隨著分割數之增加而 極性反轉後，若色階電壓 一些時間，則色階電壓在 施加顯示訊號電壓之訊號 短，故寫入動作不充分， 間來對各訊號線施加足夠 器之驅動能力，在此情況 增加的問題。 顯示資料來驅動具有排列 之各交點附近的複數個顯 種驅動裝置之顯示裝置。 劣化並抑制顯示驅動裝置 顯示驅動裝置，其具備： 資料之色階數對應之複數 料對應之水平同步訊號的 ;以及施加電路部，分別 目之訊號線，根據前述複 料對應之顯示訊號電壓， 線依序施加前述顯示訊號 轉前述色階電壓極性之時 同步訊號之時序更早，且 顯示訊號電壓結束後的時 1303403 序。 前述色階電壓生成部之反轉前述色階電壓極性之時序’ 係設定於對前述複數條訊號線施加前述顯示訊號電壓結束 後，且比既定之色階電壓收斂時間早，該色階電壓收斂時 間是在前述色階電壓自下次之前述水平同步訊號之時序做 極性反轉後，該色階電壓之電壓値收斂的時間。 前述顯示驅動裝置，係進一步具備用以將前述顯示資料 載入且並列地保持的資料保持部；前述施加電路部，係具 • 備：第1開關電路部，用來按照前述水平同步訊號而依序 選擇並列地保持於前述資料保持部之前述既定數目之各個 顯示資料；顯示訊號生成部，用來根據前述顯示資料之色 階値’來選擇前述複數個色階電壓之任一個，並生成前述 顯示訊號電壓；以及第2開關電路部，用來按照前述水平 同步訊號而依序選擇前述既定數目之每一條訊號線，分別 對所選擇之前述既定數目之訊號線依序施加前述顯示訊號 電壓’前述顯示訊號電壓是前述顯示訊號生成部所生成， ^ 且與前述第1開關電路部所選擇之前述顯示資料相對應。 又’前述第2開關電路部也可以具有在選擇前述既定數目 之任一條訊號線前，使前述複數條訊號線全部爲選擇狀態 的期間。 用於獲得上述優點之本發明之顯示裝置具備：掃描驅動 笔路’用來對前述複數條掃描線依序輸出掃描驅動訊號， 將前述顯示像素依序設定於選擇狀態；極性反轉訊號生成 部，用來以基於前述影像訊號之水平同步訊號對應之時序 Ί303403 來輸出極性反轉之反轉訊號；以及訊號驅動電路，具備： 生成基於前述影像訊號之顯示資料之色階數對應之複數個 色階電壓，並按照前述反轉訊號之極性反轉時序反轉前述 色階電壓之極性的色階電壓生成部、以及分別設於前述複 數條訊號線中既定數目之訊號線，以根據前述複數個色階 電壓來生成前述顯示資料對應之顯示訊號電壓，並對前述 既定數目之每一條訊號線依序施加前述顯示訊號電壓的施 加電路部；前述反轉訊號之極性反轉時序，係設定於比下 ® 次之前述水平同步訊號之時序更早，且在對前述複數條訊 號線施加前述顯示訊號電壓結束後的時序。 前述反轉訊號之極性反轉時序，係設定於前述施加電路 部對前述複數條訊號線施加前述顯示訊號電壓結束後，且 比既定之色階電壓收斂時間早，該既定之色階電壓收斂時 間是在前述色階電壓自下次之水平同步訊號之時序做極性 反轉後，該色階電壓之電壓値收斂的時間。 前述訊號驅動電路進一步具備用來將前述顯示資料載入 ® 且並列地保持的資料保持部；前述施加電路部，係具備： 第1開關電路部，用來按照前述水平同步訊號依序選擇並 列地保持於前述資料保持部之前述既定數目之各個顯示資 料；顯示訊號生成部，用來根據前述顯示資料之色階値來 選擇前述複數個色階電壓之任一個，並生成前述顯示訊號 電壓；以及第2開關電路部，用來按照前述水平同步訊號 依序選擇前述既定數目之每一筆訊號線，並分別對所選擇 之前述既定數目之訊號線，依序施加前述第1開關電路部 '1303403 4 所選擇之前述顯示資料對應之顯示資料訊號。又，前述第 2開關電路部也可以具有在選擇前述既定數目之訊號線之 任一條前，使前述複數條訊號線全部爲選擇狀態的期間。 用於獲得上述優點之本發明之顯示驅動裝置之驅動控制 方法包含：生成前述顯示資料之色階數對應之複數個色階 電壓的步驟；生成基於前述複數個色階電壓之前述顯示資 料對應之顯示訊號電壓的步驟；對前述複數條訊號線中既 定數目之每一條訊號線依序施加前述顯示訊號電壓的步 ® 驟；以及以在比下次之水平同步訊號之時序更早且在對前 述複數條訊號線施加前述顯示訊號電壓結束後的時序，來 反轉前述色階電壓之極性的步驟。在反轉前述色階電壓極 性之步驟中，反轉前述色階電壓極性之時序，係設定於對 前述複數條訊號線施加前述顯示訊號電壓結束後且比既定 之色階電壓收斂時間早，該既定之色階電壓收斂時間是在 前述色階電壓自下次之水平同步訊號之時序做極性反轉 後，該色階電壓之電壓値收斂的時間。 ® 生成前述顯示訊號電壓之步驟，係包含：將前述顯示資 料載入且並列地保持的步驟、按照前述水平同步訊號而依 序選擇所保持之前述既定數目之各個顯示資料的步驟、以 及根據前述顯示資料之色階値來選擇前述複數個色階電壓 之任一個，並生成前述顯示訊號電壓的步驟； 對前述複數條訊號線中既定數目之每一條訊號線依序施 加前述顯示訊號電壓的步驟，係包含按照前述水平同步訊 號而依序選擇前述既定數目之每一條訊號線，並分別對所 -10- 1303403 選擇之前述既定數目之訊號線依序施加前述顯示訊號電壓 的步驟。又，依序施加前述顯示訊號電壓之步驟也可以包 含在前述既定數目之訊號線之任一條被選擇前，使前述複 數個數目之訊號線全部爲選擇狀態的步驟。 【實施方式】 毕夺伴實施型·態之詳細說明 以下，就相關之顯示驅動裝置及其驅動控制方法以及具 有該顯示驅動裝置之顯示裝置，詳細說明實施型態之型態。 第1圖係顯示本發明液晶顯示裝置構成之方塊圖。 第2圖係本發明顯示像素之等效電路。 液晶顯示裝置1具有液晶顯示面板1〇(顯示面板）、訊號 驅動器20(訊號驅動電路）、掃描驅動器30(掃描驅動電路）、 RGB解碼器40(水平同步訊號生成部）、驅動放大器70、LCD 控制器80(極性反轉訊號生成部）、電壓產生電路90等而構 成。 在此，本發明之訊號驅動器20具備分時驅動方法，以 下，假設爲用以進行3等分驅動的驅動器，但本發明不限 於此種驅動器，也可以爲具有其他分割數之驅動器。 液晶顯示面板1 0具有列方向配設之複數條掃描線G及行 方向配設之複數條訊號線S，於掃描線G及訊號線S之各 交點附近具有第2圖所示之顯示像素PIX。 各顯示像素PIX由經由薄膜電晶體（TFT)91連接於掃描 線G及訊號線S之像素電極92、配置於與像素電極92相 對向之位置的對向電極93、將液晶塡充於像素電極92與對 -11- 1303403 向電極93之間而形成的像素電容94、與像素電容94並列 連接以保持像素電容94之施加電壓的輔助電容95所構 成。又，各顯示像素PIX利用液晶之排列因形成於像素電 極92與對向電極93之間的電場而改變的性質，實現圖像 之顯示。 訊號驅動器20連接有訊號線S，根據自後述之LCD控制 器80輸出之水平控制訊號（時鐘訊號SCK、移位啓動訊號 STH、鎖存式操作控制訊號STB等）來以1列爲單位記憶由 • RGB解碼器40供應之R(紅）、G(綠）、B(藍）各色之顯示資 料，並將基於該顯示資料之顯示訊號電壓依序供應給各訊 號線S。詳細說明將於後述。 掃描驅動器30連接有掃描線G，根據自LCD控制器80 輸出之垂直控制訊號，對各掃描線G依序施加掃描訊號， 而設爲選擇狀態，並對與訊號線S交叉之位置之顯示像素 PIX(像素電極）施加由訊號驅動器20經由訊號線S供應之 顯示訊號電壓。 ® RGB解碼器40，例如從液晶顯示裝置1之外部所供應之 影像訊號（複合視頻訊號）萃取水平同步訊號H、垂直同步訊 號V及複合同步訊號CSY，供應給LCD控制器80，並且將 基於影像訊號所含之R、G、B各色訊號的RGB顯示資料萃 取作爲數位訊號，並輸出到訊號驅動器20。 驅動放大器70，係生成用來施加於各顯示像素PIX連接 於輔助電容95之輔助電容線（共通線）C以及對向電極93的 共同訊號電壓VCOM，並依照自LCD控制器80輸出之極性 -12- 1303403 反轉控制訊號FRP，將共同訊號電壓VCOM之極性反轉輸 出。 LCD控制器80，係根據由RGB解碼器40供應之水平同 步訊號Η、垂直同步訊號V及複合同步訊號CSY，來將極 性控制訊號P〇L等生成並輸出到訊號驅動器20及驅動放大 器70，並且將水平控制訊號、垂直控制訊號生成並輸出到 各個訊號驅動器2 0及掃描驅動器3 0，藉此，以既定之時序 對各顯示像素PIX施加色階電壓，在液晶顯示面板1 0顯示 • 基於顯示資料之既定圖像資訊而控制。 電壓產生電路90，係用來生成供應構成液晶顯示裝置1 之各電路所必要的複數個電壓。例如，在後述之訊號驅動 器20內的色階電壓生成部28,用來將生成色階電壓所必要 的電壓VH及VL等生成供應給訊號驅動器20。 第3圖係本發明訊號驅動器實施型態中主要部分之構成 圖。 訊號驅動器20具有移位暫存部21、資料暫存部22(資料 ® 保持部）、資料鎖存部23、第1開關電路部24(第1開關 電路部）、DAC電路部25(顯示訊號生成電路）、第2開關電 路部26 (第2開關電路部）、開關切換部27、及色階電壓生 成部28 (色階電壓生成電路）而構成。 移位暫存部2 1用來使輸入之移位啓動訊號S TH以時鐘訊 號SCK來依序移位，並作爲時序訊號輸出到資料暫存部22。 a位元之顯示資料（例如，第3圖中，由a = 8位元所構成 之D00〜D07)輸入資料暫存部22，以自移位暫存部21輸入 1303403 之訊號之時序來依序載入顯示資料。 資料鎖存部23，係用來依照輸入之鎖存式操作控制訊號 STB將自資料暫存部22輸出之顯示資料PI、P2.....Pn 一齊載入，並且將載入之顯示資料PI、P2.....Pn透過第 1開關電路部24輸出到DAC電路部25作爲顯示資料Q1、 Q 2、…、Q η 〇 DAC電路部25，係由複數個DAC部251及輸出放大電路 2 5 2所構成，藉由D A C部2 5 1來選擇由色階電壓生成部2 8 • 供應之色階電壓，藉此，每個顯示資料Ql、Q2.....Qn 轉換爲所對應之類比訊號電壓，透過輸出放大電路（緩衝電 路）252輸出作爲顯示訊號電壓，並透過第2開關電路部26 分別施加於訊號線S 1、S 2.....S η。 接著，就第1開關電路部24及第2開關電路部26詳加 說明。第1開關電路部24由分別具有複數個開關的複數個 第1開關群241所構成。又，第2開關電路部26由分別具 有複數個開關的複數個第2開關群26 1所構成。此等第1 ® 開關電路部24及第2開關電路部26係被自開關切換部27 輸出之訊號驅動控制，以分時之方式進行顯示資料訊號之 施加動作。 亦即，第1開關電路部24，係自資料鎖存部23輸出之複 數條顯示資料輸出線中每m條（m爲2以上之整數；第3圖 中，圖示m = 3之情況）顯示資料輸出線就具有1個第1開 關群241，’各第1開關群241則選擇m條顯示資料輸出線 中之1條來連接於1個D A C部2 5 1。 -14·The invention relates to a display driving device, a driving control method thereof, and a display device having the same, and more particularly to a display signal voltage based on a plurality of gradation voltages The signal lines applied to the display panel are such that the display panel displays an image and a driving control method thereof, and a display device having such a driving device. [Prior Art] ® In recent years, liquid crystal display devices have been used in the field of very popular digital cameras, digital cameras, and other portable devices, such as mobile phones and personal digital PDAs. A display device (display device) such as a text message is often used as a monitor for a video device such as a computer or a monitor for a video device such as a television. The liquid crystal display device of this type is light and thin, can be made low in power consumption, and is excellent in display image quality. Most of the liquid crystal display panels of such liquid crystal display devices use an active matrix type liquid crystal display panel, in which a plurality of scanning lines and a plurality of signal lines are arranged in a crosswise manner, and liquid crystal pixels are arranged near each intersection. The active matrix liquid crystal display panel is provided with liquid crystal between a pixel electrode (display pixel) connected to a signal line via a switching element (for example, a TFT: thin film transistor) and a common electrode disposed opposite to the pixel electrode. An electric field is formed between the two electrodes to drive the liquid crystal. A liquid crystal display device having such an active matrix type liquid crystal display panel has: an RGB decoder 'for extracting display data of R, G, and B colors from an externally supplied image signal (composite video signal); and a signal driver for The display signal voltage corresponding to the display 1303403 data signal based on the display data output by the RGB decoder is applied to each signal line. The signal driver has a gradation voltage generating circuit for generating a plurality of gradation voltages for generating a display signal voltage when the display data is a digital signal. Further, since the liquid crystal is driven in reverse, the potential of the gradation voltage and the polarity are reversed with a predetermined period. Further, any one of the plurality of gradation voltages is selected according to the color gradation of the displayed data, and the display signal voltage corresponding to the selected gradation voltage is applied to each of the signal lines. Φ On the other hand, in the field of signal drivers for liquid crystal display devices, a technique is known in which a liquid crystal display panel is highly resolved, and when a number of signal lines is increased, a plurality of signal lines are divided into a plurality of signals, which will correspond to each other. The display signal voltage is output in a time-sharing manner, and is switched to each of the divided signal lines to drive the liquid crystal display panel in a time-sharing manner. In the case of the signal driver having the above-described gradation voltage generating circuit, in order to select a plurality of gradation voltages generated by the gradation voltage generating circuit according to the gradation 显示 of the display data, the selected gradation voltage is applied to Φ Each signal line, so a plurality of switching elements corresponding to the respective signal lines are set in each gradation voltage application line. This switching element uses a transistor or the like, and many of the transistors are provided in the respective gradation voltage application lines, and the load capacity associated with many of the transistors is a large capacity as a whole. Therefore, after the polarity of the potential of the gradation voltage is reversed, the potential of the gradation voltage application line is stabilized (converged) before the predetermined potential, and it takes some time. SUMMARY OF THE INVENTION A signal driver having such a gradation voltage generating circuit is applied to each signal line during a horizontal scanning period in a case where the above-described time-division driving is applied, and the application time of the signal voltage is applied to the respective signal lines (write _ change) In addition, the potential of the potential of the gradation voltage is stabilized at a predetermined potential before the potential is stabilized, and the application time of the line to be initially started, that is, the writing time is changed to deteriorate the display image quality. With such a short application voltage level voltage, the power consumption of the signal driver is improved under the signal driving φ. The present invention is a display driving device, and the display panel is displayed according to a plurality of signal lines and a plurality of scanning lines; And the present invention has the advantage of being able to suppress an increase in display image quality. The gradation voltage generating unit of the present invention for obtaining the above advantages generates the display gradation voltage to invert the aforementioned based on the display timing The polarity of the gradation voltage is set in a predetermined number of gradation voltages in the plurality of signal lines to generate the foregoing display And for each of the predetermined number of signal voltages; the reverse order of the gradation voltage generating unit is set to be more polar than the next level in applying the F to the plurality of signal lines) as the number of divisions increases After the inversion, if the gradation voltage is some time, the signal of the gradation voltage applied to the display signal voltage is short, so the writing operation is insufficient, and the driving ability of the sufficient signal is applied to each signal line, and the problem is increased in this case. . The display device is used to drive a display device having a plurality of display driving devices in the vicinity of each of the arranged intersections. Degrading and suppressing the display driving device display driving device, comprising: a horizontal synchronization signal corresponding to the plurality of materials corresponding to the number of gradations of the data; and an application circuit portion, respectively, the signal line, according to the display signal voltage corresponding to the plurality of materials When the line sequentially applies the aforementioned display signal to the polarity of the gradation voltage, the timing of the synchronization signal is earlier, and the time 1303403 after the end of the signal voltage is displayed. The timing of inverting the polarity of the gradation voltage of the gradation voltage generating unit is set after the end of applying the display signal voltage to the plurality of signal lines, and is earlier than a predetermined gradation voltage convergence time, and the gradation voltage converges The time is the time at which the voltage 値 of the gradation voltage converges after the polarity of the gradation voltage is reversed from the timing of the next horizontal sync signal. Further, the display driving device further includes a data holding unit for loading and holding the display data in parallel, and the application circuit unit is provided with a first switching circuit unit for accommodating the horizontal synchronization signal And selecting, in parallel, each of the display data of the predetermined number of the data holding unit; the display signal generating unit configured to select any one of the plurality of color gradation voltages according to the color gradation ′′ of the display data, and generate the foregoing And displaying the signal voltage; and the second switch circuit unit is configured to sequentially select each of the predetermined number of signal lines according to the horizontal synchronization signal, and sequentially apply the display signal voltage to the selected predetermined number of signal lines. The display signal voltage is generated by the display signal generating unit, and corresponds to the display material selected by the first switch circuit unit. Further, the second switch circuit unit may have a period in which all of the plurality of signal lines are selected before any one of the predetermined number of signal lines is selected. The display device of the present invention for obtaining the above advantages includes: a scan driving pen path for sequentially outputting a scan driving signal to the plurality of scanning lines, sequentially setting the display pixels in a selected state; and a polarity inversion signal generating portion And outputting a polarity inversion reverse signal according to a timing Ί 303403 corresponding to the horizontal synchronization signal of the image signal; and the signal driving circuit has: generating a plurality of colors corresponding to the number of gradations of the display data based on the image signal a gradation voltage generating unit that inverts a polarity of the gradation voltage according to a polarity inversion timing of the inversion signal, and a predetermined number of signal lines respectively disposed in the plurality of signal lines, according to the plurality of The gradation voltage is used to generate the display signal voltage corresponding to the display data, and the application circuit portion for sequentially applying the display signal voltage to each of the predetermined number of signal lines; the polarity inversion timing of the reverse signal is set to be The timing of the above-mentioned horizontal sync signal is earlier, and the above multiple signals are The line applies the timing after the end of the display signal voltage. The polarity inversion timing of the inversion signal is set after the application circuit unit applies the display signal voltage to the plurality of signal lines, and is earlier than a predetermined color gradation voltage convergence time, and the predetermined color gradation voltage convergence time After the polarity of the gradation voltage is reversed from the timing of the next horizontal sync signal, the voltage 値 of the gradation voltage converges. Further, the signal driving circuit further includes a data holding unit for loading and displaying the display data in parallel, and the application circuit unit includes: a first switching circuit unit for sequentially juxtaposed in accordance with the horizontal synchronization signal a display signal generating unit configured to select any one of the plurality of gradation voltages based on the gradation 値 of the display data and generate the display signal voltage; and The second switch circuit unit is configured to sequentially select each of the predetermined number of signal lines according to the horizontal synchronization signal, and sequentially apply the first switch circuit unit '1303403 to the selected predetermined number of signal lines. The display data signal corresponding to the selected display data selected. Further, the second switch circuit unit may have a period in which all of the plurality of signal lines are selected before any one of the predetermined number of signal lines is selected. The driving control method of the display driving device of the present invention for obtaining the above advantages includes: generating a plurality of gradation voltages corresponding to the number of gradations of the display data; and generating the display data corresponding to the plurality of gradation voltages a step of displaying a signal voltage; sequentially applying the foregoing display signal voltage to each of the predetermined number of signal lines in the plurality of signal lines; and at a timing earlier than the next horizontal synchronization signal and in the foregoing The step of inverting the polarity of the gradation voltage by applying a timing after the end of the display signal voltage is applied to the plurality of signal lines. In the step of inverting the polarity of the gradation voltage, the timing of inverting the polarity of the gradation voltage is set after the end of the application of the display signal voltage to the plurality of signal lines and is earlier than a predetermined gradation voltage convergence time. The predetermined gradation voltage convergence time is the time at which the voltage 値 of the gradation voltage converges after the gradation voltage is reversed from the timing of the next horizontal synchronization signal. The step of generating the foregoing display signal voltage includes: a step of loading and holding the display data in parallel, a step of sequentially selecting each of the predetermined number of display materials held in accordance with the horizontal synchronization signal, and according to the foregoing Displaying a color gradation of the data to select any one of the plurality of gradation voltages, and generating the step of displaying the signal voltage; and sequentially applying the display signal voltage to each of the predetermined number of signal lines of the plurality of signal lines And the step of sequentially selecting each of the predetermined number of signal lines according to the horizontal synchronization signal, and sequentially applying the display signal voltage to the predetermined number of signal lines selected by the -10-1303403. Moreover, the step of sequentially applying the display signal voltage may also include the step of causing the plurality of signal lines to be in a selected state before any one of the predetermined number of signal lines is selected. [Embodiment] Detailed description of the mode of the completion mode will be described in detail below with reference to the related display driving device, its driving control method, and the display device having the display driving device. Fig. 1 is a block diagram showing the constitution of a liquid crystal display device of the present invention. Figure 2 is an equivalent circuit of the display pixel of the present invention. The liquid crystal display device 1 includes a liquid crystal display panel 1 (display panel), a signal driver 20 (signal drive circuit), a scan driver 30 (scan drive circuit), an RGB decoder 40 (horizontal sync signal generation unit), a drive amplifier 70, and an LCD. The controller 80 (polarity inversion signal generating unit), the voltage generating circuit 90, and the like are configured. Here, the signal driver 20 of the present invention is provided with a time division driving method, and is assumed to be a driver for performing halving drive, but the present invention is not limited to such a driver, and may be a driver having other division numbers. The liquid crystal display panel 10 has a plurality of scanning lines G arranged in the column direction and a plurality of signal lines S arranged in the row direction, and has display pixels PIX shown in FIG. 2 near the intersections of the scanning lines G and the signal lines S. . Each of the display pixels PIX is connected to the pixel electrode 92 of the scanning line G and the signal line S via the thin film transistor (TFT) 91, the counter electrode 93 disposed at a position facing the pixel electrode 92, and the liquid crystal is filled on the pixel electrode. 92 is formed by a pixel capacitor 94 formed between the pair of -11-1303403 electrodes 93 and an auxiliary capacitor 95 connected in parallel with the pixel capacitor 94 to hold the applied voltage of the pixel capacitor 94. Further, each display pixel PIX realizes display of an image by the property that the arrangement of the liquid crystals changes due to the electric field formed between the pixel electrode 92 and the counter electrode 93. The signal driver 20 is connected to the signal line S, and is stored in units of one column according to the horizontal control signal (clock signal SCK, shift start signal STH, latch operation control signal STB, etc.) output from the LCD controller 80, which will be described later. • Display data of R (red), G (green), and B (blue) colors supplied from the RGB decoder 40, and sequentially supply the display signal voltages based on the display data to the respective signal lines S. The detailed description will be described later. The scan driver 30 is connected to the scan line G, and sequentially applies a scan signal to each scan line G according to the vertical control signal output from the LCD controller 80, and sets the display pixel to the position where the signal line S intersects. The PIX (pixel electrode) applies a display signal voltage supplied from the signal driver 20 via the signal line S. The RGB decoder 40, for example, extracts the horizontal synchronizing signal H, the vertical synchronizing signal V, and the composite synchronizing signal CSY from the image signal (composite video signal) supplied from the outside of the liquid crystal display device 1, and supplies it to the LCD controller 80, and will be based on The RGB display data of the R, G, and B color signals included in the image signal is extracted as a digital signal and output to the signal driver 20. The driving amplifier 70 generates a common signal voltage VCOM applied to the auxiliary capacitance line (common line) C and the opposite electrode 93 of each of the display pixels PIX connected to the auxiliary capacitor 95, and according to the polarity output from the LCD controller 80 - 12- 1303403 Reverses the control signal FRP and inverts the polarity of the common signal voltage VCOM. The LCD controller 80 generates and outputs the polarity control signal P〇L and the like to the signal driver 20 and the driver amplifier 70 according to the horizontal synchronization signal Η, the vertical synchronization signal V, and the composite synchronization signal CSY supplied from the RGB decoder 40. And the horizontal control signal and the vertical control signal are generated and output to the respective signal driver 20 and the scan driver 30, whereby the color gradation voltage is applied to each display pixel PIX at a predetermined timing, and displayed on the liquid crystal display panel 10. Controls the display of the established image information of the data. The voltage generating circuit 90 is for generating a plurality of voltages necessary for supplying the circuits constituting the liquid crystal display device 1. For example, the gradation voltage generating unit 28 in the signal driver 20, which will be described later, generates and supplies the voltages VH and VL necessary for generating the gradation voltage to the signal driver 20. Fig. 3 is a view showing the configuration of the main part of the signal driver implementation of the present invention. The signal driver 20 includes a shift temporary storage unit 21, a data temporary storage unit 22 (data management unit), a data latch unit 23, a first switch circuit unit 24 (first switch circuit unit), and a DAC circuit unit 25 (display signal) The generating circuit), the second switching circuit unit 26 (second switching circuit unit), the switching unit 27, and the gradation voltage generating unit 28 (gradation voltage generating circuit) are configured. The shift register unit 2 1 is configured to sequentially shift the input shift enable signal S TH by the clock signal SCK, and output it to the data temporary storage unit 22 as a timing signal. The display data of the a bit (for example, D00 to D07 composed of a = 8 bits in the third figure) is input to the data temporary storage unit 22, and the timing of the signal input to the 1303403 from the shift temporary storage unit 21 is used. Load the display data. The data latch unit 23 is configured to load the display data PI, P2, . . . , Pn output from the data temporary storage unit 22 in accordance with the input latch operation control signal STB, and display the loaded display data. PI, P2, . . . , Pn are output to the DAC circuit unit 25 through the first switch circuit unit 24 as display data Q1, Q2, ..., Q 〇 DAC circuit unit 25, and are amplified by a plurality of DAC units 251 and outputs. The circuit 2 52 is configured to select the gradation voltage supplied by the gradation voltage generating unit 28 by the DAC unit 251, whereby each of the display materials Q1, Q2, . . . , Qn is converted into a The analog signal voltage is output as a display signal voltage through an output amplifier circuit (snubber circuit) 252, and is applied to the signal lines S1, S2, ..., Sn through the second switch circuit unit 26, respectively. Next, the first switch circuit unit 24 and the second switch circuit unit 26 will be described in detail. The first switch circuit unit 24 is composed of a plurality of first switch groups 241 each having a plurality of switches. Further, the second switch circuit unit 26 is composed of a plurality of second switch groups 26 1 each having a plurality of switches. The first-to-one switch circuit unit 24 and the second switch circuit unit 26 are controlled by the signal drive output from the switch switching unit 27 to display the data signal in a time-sharing manner. In other words, the first switch circuit unit 24 is for every m pieces of a plurality of display data output lines output from the data latch unit 23 (m is an integer of 2 or more; in the third figure, m = 3 is shown) The display data output line has one first switch group 241, and each of the first switch groups 241 selects one of the m display data output lines to be connected to one DAC unit 251. -14·

1303403 又，第2開關電路部26，同樣地，液晶顯示面板1 〇 數條訊號線S中每m條訊號線S就具備1個第2開 26 1 ’各第2開關群26 1則用以選擇m條訊號線S中之 將自輸出放大電路25 2輸出之作爲顯示資料訊號之色 壓施加於訊號線S。 開關切換部27，係將第1開關控制訊號SW_ R 1、 G1及SW— B1輸出到第1開關群241，並將第2開關 訊號SW一 R〇、SW— GO及SW— B0輸出到第2開關群 將第1開關群24 1及第2開關群261之連接狀態設定 同狀態，並使其等同步作動。又，輸出第1開關控制 SW— Rl、SW一 G1及SW— B1及第2開關控制訊號SW_ SW一 GO及SW一 B0，使得在1掃描期間（例如，1水zp 期間）內，第1開關群241及第2開關群261之連接狀 一圈’以進行第1開關電路部24及第2開關電路部 控制動作。 第1開關控制訊號S W — R 1、S W_ G 1及S W_ B 1、 連接於第1開關群24 1之m條顯示資料輸出線中之β 相關而構成。又，在1掃描期間內，任一個第1開| 成爲ON狀態，切換開關使得與成爲ON狀態之第1圍 號形成相關之顯示資料輸出線與DAC電路部25連接 第2開關控制訊號SW_ R〇、S W_ G0及S W_ BO、 連接於第2開關群26 1之m條訊號線S中之任一條： 構成。又，在1掃描期間內，第2開關控制訊號S W SW— GO及SW一 B0依序成爲〇N狀態，切換開關使 之複 關群 1條， 階電 sw_ 控制 261， ，爲相 丨訊號 —R0、 :掃描 :態轉 26之 係與 ΐ 一條 3訊號 I關訊 〇 係與 目關而 一 R0、 I與成 -15- •1303403 爲ON狀態之第2開關控制訊號形成相關之訊號線S與輸 出放大電路25 2之輸出端子連接。 因此，訊號驅動器20進行分時驅動，係將對液晶顯示面 板1 〇之訊號線S施加顯示資料訊號的動作在1掃描期間內 分割成m等分而進行分時。在此情況下，構成D A C電路部 25之DAC部251及輸出放大電路252之個數與構成第1開 關電路部24、第2開關電路部26的第1開關群241、第2 開關群26 1之個數相同，故爲訊號線S條數之1 / m。 其次，就DAC電路部25及色階電壓生成部28加以說明。 第4圖係顯示本實施形態之DAC電路部及色階電壓生成 部電路構成例的圖。 色階電壓生成部28係對電壓VH與電壓VL之間，以顯 示資料之色階數（色階數=2a。例如，第4圖中，28= 256 色階）對應之複數個電阻Rl、R2.....R254來進行分壓， 並將分壓後之電壓作爲色階電壓施加於色階電壓施加線 VO、V 1.....V2 5 5。 具體來說，自電壓產生電路90對放大器281及284供應 電壓VH，將放大後之電壓施加於端子281a及284a。又， 自電壓產生電路90對放大器282及2 8 3供應電壓VL，將 放大後之電壓施加於端子282a及28 3 a。又，開關28a依照 自LCD控制器80輸出之極性控制訊號P〇L來切換端子281a 或端子2 82a以做選擇。開關28b也同樣地依照極性控制訊 號P〇L來切換端子2 8 3 a或端子2 8 4 a以做選擇。在此，利 用開關28a及28b來同時選擇端子281a及端子2 8 3 a，並同 -16- 1303403 時選擇端子282a及端子2 84a。因此，電壓VH施加於色階 電壓施加線V0時，電壓VL施加於色階電壓施加線V 25 5 ; 電壓V L施加於色階電壓施加線V 0時，電壓V Η施加於色 階電壓施加線V25 5。如此，依照極性控制訊號POL之極性 反轉，極性反轉後之電壓施加於色階電壓施加線V 0及 V 25 5，同時，色階電壓施加線VI〜V254之電壓也做極性 反轉。 DAC部251係具備解碼器2511、及連接於各色階電壓施 ® 力□線 VO、VI.....V 25 5 之選擇開關 SW0、SW1.....SW255 而構成。解碼器25 1 1用來將自第1開關群24 1輸出之顯示 資料輸入解碼，並輸出RGB各像素之色階數所對應之色階 位準訊號。各選擇開關SW0、SW1.....SW25 5根據自解 碼器25 1 1輸出之色階位準訊號來控制〇N/ OFF。又，所選 擇之色階電壓施加線V 0、V 1.....V 2 5 5與色階電壓輸出 線S L導通，將施加於色階電壓施加線V 0、V 1.....V 2 5 5 之色階電壓施加於色階電壓輸出線S L。亦即，色階電壓輸 ® 出線中所選擇之色階電壓施加線V 0、V 1.....V 2 5 5之色 階電壓輸出到色階電壓輸出線SL，再透過輸出放大電路 2 5 2輸出到第2開關群2 6 1。 其次，就本實施型態之液晶顯示裝置1之驅動控制方法 加以說明，且與適用習知驅動控制方法之情況比對，藉以 詳細說明本發明之作用功效。 第5 A圖係顯示習知液晶顯示裝置之主要訊號之訊號波 形的圖。 -17- •1303403 第5B圖係將第5A圖之時間Τ(水平同步訊號Η輸出後， 下次水平同步訊號輸出爲止的1水平掃描期間）放大顯示的 圖。 該等圖中，使橫軸爲時間軸，自上方起顯示水平同步訊 號Η、極性控制訊號POL、施加於色階電壓施加線V0之電 壓波形、施加於色階電壓施加線V255之電壓波形、第2開 關控制訊號 SW_ R0、SW_ GO、SW_ B0、共同訊號電壓 VCOM之電壓波形。 > 第5B圖中，極性控制訊號POL之極性與水平同步訊號Η 之上升部分相對應地同時反轉。再者，第2開關控制訊號 SW_ R0成爲高位準，作爲顯示資料訊號之色階電壓施加於 與第2開關控制訊號SW_ R0相對應之訊號線S。其次，第 2開關控制訊號SW_ G0被選擇成爲高位準，接著，第2 開關控制訊號SW_ B 0被選擇成爲高位準，被選擇之色階 電壓作爲顯示資料訊號依序施加於對應之訊號線S。 然而，如第5B圖所示，色階電壓施加線V0及V255之 > 電位之極性依照極性控制訊號POL之極性反轉而反轉穩定 之前，耗費時間11 1。這是因爲於1個色階電壓施加線有許 多由電晶體所構成之選擇開關SW1、SW2.....SW25 5連 接著，而成爲色階電壓施加線之大負載容量。因此，色階 電壓之電位因極性反轉而改變後，色階電壓施加線在既定 之電位穩定（收斂）前耗費時間。如此，各色階電壓施加線 之電位之變動期間（時間11 1)中，無法正確生成顯示資料所 對應之色階電壓，可獲得正確的色階電壓的時間變成僅有 -18- 1303403 扣除變動期間11 1後所得之時間11 2，在變動期間11 1，未 進行正確的寫入動作。因此，在此情況下，正確的色階電 壓施加之施加時間（寫入時間）實質上變短。如此，若色階 電壓對第2開關控制訊號SW_ R0所對應之訊號線S的施 加時間實質上變短，則與其他之第2開關控制訊號SW_ GO 及SW_ B〇所對應之訊號線S相比，有對第2開關控制訊 號SW_ R0所對應之訊號線S的色階電壓施加不足（顯示資 料訊號之寫入不足）的問題發生。亦即，對第2開關控制訊 • 號SW_ R0所對應之訊號線S之顯示像素PIX施加不夠的 色階電壓，故顯示於液晶顯示面板1 0之圖像產生縱形圖 紋，導致顯示畫質劣化。 另一方面，若爲了即便在上述般短的施加時間也能對訊 號線S施加足夠的色階電壓，而提高輸出放大電路252之 驅動能力，則產生電力消耗量增加之問題。 其次，說明本實施型態之液晶顯示裝置1之驅動控制方 法。 ® 第6A圖係顯示本實施型態之液晶顯示裝置1之主要訊號 之訊號波形的圖。 第6B圖係將第6A圖之時間T(1水平掃描期間）附近放大 顯示的圖。 該等圖中，使橫軸爲時間軸，自上方起顯示水平同步訊 號Η、極性控制訊號POL、施加於色階電壓施加線V0之電 壓波形、施加於色階電壓施加線V25 5之電壓波形、第2開 關控制訊號SW— R〇、SW— GO、SW— B0、共同訊號電壓 -19- 1303403 VCOM之電壓波形。 習知之極性控制訊號POL雖然依照水平同步訊號Η之上 升部分而同時做極性反轉，但在本實施型態，如第6 Α圖所 示’以在水平同步訊號Η上升經過時間Tk( < T)後，且在 該掃描期間對各訊號線S之色階電壓施加結束後的時序， 使極性控制訊號P〇L之極性反轉。換言之，L C D控制器8 0 係將極性控制訊號POL，以比下次之水平同步訊號Η之上 升部分還早時間（Τ - Tk)(色階電壓收斂時間），且在該掃描 ® 期間對各訊號線S之色階電壓之施加結束後的時序，做極 性反轉並輸出。又，在色階電壓生成部28，開關28a及28b 依照極性控制訊號POL之極性反轉而切換，故施加於色階 電壓施加線V 0〜V 2 5 5之色階電壓之極性反轉。 又’此色階電壓收斂時間，係設定各色階電壓施加線之 極性依照極性控制訊號POL之極性反轉而反轉且電位在穩 定（收斂）之前耗費的時間，設定爲基於色階電壓施加線負 載容量之時間常數所對應的時間。又，例如，在如本實施 — 型態般進行3等分之分時驅動之情況下，也可以將T - Tk 之時間設定爲約1 / 4T的時間。 亦即，因爲極性控制訊號POL之極性反轉以比下次之水 平同步訊號Η之上升部分早時間（T - Tk)的時序來進行，故 在水平同步訊號Η之上升部分之時點，各色階電壓施加線 之電位已經在穩定狀態。 再者，因爲在1掃描期間對各訊號線S之色階電壓之施 加結束後，極性控制訊號POL之極性反轉，而色階電壓之 -20- 1303403 極性反轉，故即便依照水平同步訊號Η之上升部分，第2 開關控制訊號SW一 R0、SW— GO、SW_ Β0之任一訊號成爲 高位準’也能將顯示資料所對應之正確的色階電壓施加於 所對應之訊號線S。 因此，可以避免習知發生之顯示畫質劣化。又，因可以 使對各訊號線S施加色階電壓之施加時間（寫入時間）相等 (時間t22)，故可以提高顯示畫質。再者，不必爲了解決對 顯示像素PIX之色階電壓之施加不足的問題，而提高輸出 • 放大器電路25 2之驅動能力，故能抑制電力消耗量之增加。 再者，設定成，在前面之掃描期間對訊號線S之色階電 壓之施加結束後，一直到在下次之掃描期間第2開關控制 訊號SW一 R0、SW一 GO、SW— B0中任一訊號成爲高位準爲 止的空閒時間爲△ t。也可以將該空閒時間△ t充當爲用於 使顯示像素PIX之電位爲既定之收斂電位的時間。又，也 可以將空閒時間△ t充當爲遮沒期。 又，如第6A、6B圖所示，也可以設定成，在極性控制訊 ® 號POL之極性反轉而第2開關控制訊號SW_ R〇、SW_ G〇、SW_ B0中任一訊號成爲高位準前，第2開關控制訊 號SW— R0、SW— GO、SW— B0所有的開關成爲線路電壓穩 定時間（時間t21)高位準。因此，色階電壓之任一電壓施加 於訊號線S。以往，極性控制訊號POL之極性反轉，而第 2開關控制訊號SW— R0、SW— GO、SW— B0中任一訊號成 爲高位準之前，訊號線S處於高阻抗狀態，但透過液晶顯 示面板1 0內之寄生電容，訊號驅動器20之輸出端子之電 -21- Ί303403 位例如成爲與共同訊號電壓VC 0M同電位，然後，處於與 施加於訊號線S之色階電壓間之電位差大的狀態。亦即， 有以下的問題：對訊號線S施加色階電壓，該訊號線S之 電位穩定之前耗費時間，對顯示像素PIX之寫入時間變 長。因此’設定成，極性控制訊號POL之極性反轉，而第 2開關控制訊號SW— R〇、SW— GO、SW— B0中任一訊號成 爲高位準之前，第2開關控制訊號SW—RO、SW—GO、SW —B0在線路電壓穩定時間（時間t2l)之間成爲高位準，藉此 φ 對訊號線S施加色階電壓之任一電壓。此電壓與之後施加 之色階電壓沒有太大的差別。因此，即便對訊號線S施加 正常之色階電壓，該訊號線s之電位也立刻到達色階電壓 之電位，故可以縮短對顯示像素PIX之寫入時間。 如此，本實施型態中，因爲以在1掃描期間對各訊號線 S之色階電壓之施加結束後，且比下次之水平同步訊號η 之上升部分還早色階電壓收斂時間（Τ - Tk)的時序來進行 極性控制訊號P 0 L之極性反轉，故消除極性反轉後一直到 Φ 色階電壓之電位穩定爲止耗費的時間之影響，即便依照水 平同步訊號Η之上升部分，第2開關控制訊號S W — R 0、 SW_ GO、SW一 Β0之任一訊號成爲高位準，仍可以將顯示 資料所對應之正確色階電壓施加於訊號線S。藉此，可以 防止顯示畫質劣化。又，因爲可以使對各訊號線S施加顯 示資料對應之色階電壓的施加時間（寫入時間）相等，故可 以提筒顯示畫質。再者，不必爲了解決對顯示像素ΡΙχ之 色階電壓之施加不足的問題而提高輸出放大器電路25 2之 -22- 1303403 驅動能力，故可以減少電力消耗量。 以上’已就本發明之實施型態加以說明，但可適用本發 明的型態不應該限定於上述之實施型態，當然可以做適當 變更。例如，第1開關群241是每自資料鎖存部23輸出之 每3條顯示資料輸出線就具備1個開關，且第2開關群26 1 是每3條訊號線S就具備1個開關，但也可以每3條以外 之2條或4條以上之複數條顯示資料輸出線及訊號線S就 具備1個開關。 • 【圖式簡單說明】 第1圖係顯示本發明液晶顯示裝置構成之方塊圖。 第2圖係本發明顯示像素之等效電路。 第3圖係本發明訊號驅動器實施型態中主要部分之構成 圖。 第4圖係本實施型態之色階電壓生成部及d A C電路部之 電路構成圖。 第5A、5B圖係顯示有習知液晶顯示裝置主要訊號訊號 ® 波形的時序圖。 第6A、6B圖係顯示有本實施型態液晶顯示裝置主要訊 號訊5虎波形的時序圖。 【主要元件符號說明】 1 液晶顯示裝置 10 液晶顯示面板 20 訊號驅動器 21 移位暫存部 -23- Ί303403 22 資料暫存部 23 資料鎖存部 24 第1開關電路部 25 DAC電路部 26 第2開關電路部 27 開關切換部 28 色階電壓生成部 28a 開關 28b 開關 30 掃描驅動器 40 RGB解碼器 70 驅動放大器 80 LCD控制器 90 電壓產生電路 91 薄膜電晶體 92 像素電極 93 對向電極 94 像素電容 95 輔助電容 241 第1開關群 251 DAC 3 252 輸出放大電路 261 第2開關群 281 放大器 281a 端子 -24- Ί303403 282 放大器 282a 端子 283 放大器 283a 端子 284 放大器 284a 端子 2511 解碼器 G 掃描線 PIX 顯示像素 Rl··· R254 電阻 S，SL··· Sn 訊號線 SL 色階電壓輸出線 SWO.·· SW255 選擇開關1303403 Further, in the second switching circuit unit 26, the liquid crystal display panel 1 has one second opening 26 for every m signal lines S in the plurality of signal lines S. The second switching group 26 1 is used for The color voltage which is output from the output amplifier circuit 25 2 as the display data signal is selected from the m signal lines S to be applied to the signal line S. The switch switching unit 27 outputs the first switch control signals SW_R1, G1, and SW_B1 to the first switch group 241, and outputs the second switch signals SW_R_, SW-GO, and SW-B0 to the first switch The switch group sets the connection state of the first switch group 24 1 and the second switch group 261 to the same state, and causes them to operate in synchronization. Further, the first switch control SW_R1, SW-1G1 and SW_B1, and the second switch control signal SW_SW_GO and SW_B0 are output so that during the 1 scan period (for example, 1 water zp period), the first The switch group 241 and the second switch group 261 are connected in a loop to perform the control operation of the first switch circuit unit 24 and the second switch circuit unit. The first switch control signals S W — R 1 , S W — G 1 , and S W — B 1 are connected to β of the m display data output lines connected to the first switch group 24 1 . Further, in any one scanning period, any one of the first opening | is in an ON state, and the switching switch is connected to the display data output line associated with the first surrounding number in the ON state, and the second switching control signal SW_R is connected to the DAC circuit unit 25. 〇, S W_ G0 and S W_ BO, and any one of the m signal lines S connected to the second switch group 26 1 : constitutes. Moreover, during the one-scan period, the second switch control signals SW SW_GO and SW-B0 sequentially become the 〇N state, and the switch is switched to make one group, and the step power sw_ control 261 is a phase signal. R0, : Scan: State to 26 and ΐ A 3 signal I is related to the signal and a R0, I and -15- • 1303403 are the ON state of the second switch control signal to form the relevant signal line S It is connected to the output terminal of the output amplifying circuit 25 2 . Therefore, the signal driver 20 performs time-division driving, and the operation of displaying the data signal on the signal line S of the liquid crystal display panel 1 is divided into m equal divisions in one scanning period to perform time division. In this case, the number of the DAC unit 251 and the output amplifier circuit 252 constituting the DAC circuit unit 25 and the first switch group 241 and the second switch group 26 1 that constitute the first switch circuit unit 24 and the second switch circuit unit 26 The number is the same, so it is 1 / m of the number of signal lines S. Next, the DAC circuit unit 25 and the gradation voltage generating unit 28 will be described. Fig. 4 is a view showing an example of a circuit configuration of a DAC circuit unit and a gradation voltage generating unit according to the present embodiment. The gradation voltage generating unit 28 is configured to display a plurality of resistors R1 corresponding to the number of gradations of the data (the number of gradations = 2a, for example, 28 = 256 gradations in Fig. 4) between the voltage VH and the voltage VL, R2 ..... R254 is used for voltage division, and the divided voltage is applied as a gradation voltage to the gradation voltage application lines VO, V 1.....V2 5 5 . Specifically, the self-voltage generating circuit 90 supplies the voltages VH to the amplifiers 281 and 284, and applies the amplified voltages to the terminals 281a and 284a. Further, the voltage generating circuit 90 supplies the voltage VL to the amplifiers 282 and 298, and applies the amplified voltage to the terminals 282a and 283a. Further, the switch 28a switches the terminal 281a or the terminal 2 82a for selection in accordance with the polarity control signal P〇L output from the LCD controller 80. Switch 28b also switches terminal 2 8 3 a or terminal 2 8 4 a in accordance with polarity control signal P 〇 L for selection. Here, the terminals 281a and the terminals 2 8 3 a are simultaneously selected by the switches 28a and 28b, and the terminals 282a and the terminals 2 84a are selected in the same manner as -16-1303403. Therefore, when the voltage VH is applied to the gradation voltage application line V0, the voltage VL is applied to the gradation voltage application line V 25 5 ; when the voltage VL is applied to the gradation voltage application line V 0 , the voltage V Η is applied to the gradation voltage application line V25 5. Thus, in accordance with the polarity inversion of the polarity control signal POL, the voltage after the polarity inversion is applied to the tone voltage applying lines V 0 and V 25 5 , and the voltages of the level voltage applying lines VI to V254 are also reversed in polarity. The DAC unit 251 includes a decoder 2511 and selection switches SW0 and SW1.....SW255 connected to the respective gradation voltages □ lines VO, VI.....V 25 5 . The decoder 25 1 1 is for inputting the display data output from the first switch group 24 1 and outputting the gradation level signal corresponding to the number of gradations of each pixel of RGB. Each of the selection switches SW0, SW1, ..., SW25 5 controls 〇N/OFF based on the gradation level signal output from the decoder 25 1 1 . Further, the selected gradation voltage application lines V 0, V 1.....V 2 5 5 are turned on with the gradation voltage output line SL, and are applied to the gradation voltage application lines V 0 , V 1.... The gradation voltage of .V 2 5 5 is applied to the gradation voltage output line SL. That is, the gradation voltage of the gradation voltage application line V 0, V 1.....V 2 5 5 selected in the gradation voltage output is output to the gradation voltage output line SL, and then amplified through the output. The circuit 2 5 2 outputs to the second switch group 2 6 1 . Next, the driving control method of the liquid crystal display device 1 of the present embodiment will be described, and compared with the case of applying the conventional driving control method, the function of the present invention will be described in detail. Fig. 5A is a diagram showing signal waveforms of main signals of conventional liquid crystal display devices. -17- • 1303403 Figure 5B is a magnified view of the time Τ of Figure 5A (the horizontal sync signal Η output, the next horizontal sync signal output period). In the figures, the horizontal axis is the time axis, and the horizontal synchronization signal Η, the polarity control signal POL, the voltage waveform applied to the gradation voltage application line V0, the voltage waveform applied to the gradation voltage application line V255, and the voltage waveform of the gradation voltage application line V255 are displayed from above. The second switch controls the voltage waveforms of the signals SW_R0, SW_GO, SW_B0, and the common signal voltage VCOM. > In Fig. 5B, the polarity of the polarity control signal POL is simultaneously inverted in correspondence with the rising portion of the horizontal sync signal Η. Further, the second switch control signal SW_R0 is at a high level, and the gradation voltage as the display data signal is applied to the signal line S corresponding to the second switch control signal SW_R0. Next, the second switch control signal SW_G0 is selected to be a high level. Then, the second switch control signal SW_B 0 is selected to be a high level, and the selected gradation voltage is sequentially applied as a display data signal to the corresponding signal line S. . However, as shown in Fig. 5B, the polarity of the potential of the gradation voltage application lines V0 and V255 is 11 1 before the polarity of the polarity control signal POL is inverted and stabilized. This is because a plurality of gradation voltage application lines have a large load capacity of a gradation voltage application line by a plurality of selection switches SW1, SW2, ..., SW25 5 composed of transistors. Therefore, after the potential of the gradation voltage is changed by the polarity inversion, the gradation voltage application line takes time before the predetermined potential is stabilized (convergence). As described above, in the fluctuation period (time 11 1) of the potential of each gradation voltage application line, the gradation voltage corresponding to the display data cannot be correctly generated, and the time for obtaining the correct gradation voltage becomes only -18 - 1303403. The time 11 11 obtained after 11 1 is not correctly written in the change period 11 1,. Therefore, in this case, the application time (writing time) of the correct gradation voltage application is substantially shortened. Thus, if the application time of the gradation voltage to the signal line S corresponding to the second switch control signal SW_R0 is substantially shortened, the signal line S corresponding to the other second switch control signals SW_GO and SW_B 相For example, there is a problem that the gradation voltage of the signal line S corresponding to the second switch control signal SW_R0 is insufficiently applied (displaying insufficient writing of the data signal). That is, an insufficient color gradation voltage is applied to the display pixel PIX of the signal line S corresponding to the second switch control signal SW_R0, so that the image displayed on the liquid crystal display panel 10 has a vertical pattern, resulting in display Deterioration. On the other hand, if a sufficient gradation voltage can be applied to the signal line S even in the short application time as described above, and the driving ability of the output amplifying circuit 252 is increased, the power consumption amount increases. Next, a driving control method of the liquid crystal display device 1 of the present embodiment will be described. ® Fig. 6A is a view showing signal waveforms of main signals of the liquid crystal display device 1 of the present embodiment. Fig. 6B is an enlarged view of the vicinity of time T (1 horizontal scanning period) of Fig. 6A. In the figures, the horizontal axis is the time axis, and the horizontal synchronization signal Η, the polarity control signal POL, the voltage waveform applied to the gradation voltage application line V0, and the voltage waveform applied to the gradation voltage application line V25 5 are displayed from above. The voltage waveform of the second switch control signal SW_R〇, SW_GO, SW_B0, common signal voltage -19-1303403 VCOM. The conventional polarity control signal POL performs polarity reversal at the same time according to the rising portion of the horizontal synchronizing signal ,, but in the present embodiment, as shown in FIG. 6 'to increase the elapsed time Tk in the horizontal synchronizing signal ( ( < After T), and after the end of the application of the gradation voltage of each signal line S during the scanning period, the polarity of the polarity control signal P 〇 L is inverted. In other words, the LCD controller 80 sets the polarity control signal POL earlier than the rising portion of the next horizontal sync signal Τ (Τ - Tk) (gradation voltage convergence time), and during the scan ® The timing after the application of the gradation voltage of the signal line S is completed, and the polarity is inverted and output. Further, in the gradation voltage generating unit 28, the switches 28a and 28b are switched in accordance with the polarity inversion of the polarity control signal POL, so that the polarity of the gradation voltage applied to the gradation voltage applying lines V 0 to V 25 5 is reversed. Further, the gradation voltage convergence time is set based on the gradation voltage application line by setting the polarity of each gradation voltage application line in accordance with the polarity inversion of the polarity control signal POL and reversing the potential before the potential is stabilized (convergence). The time corresponding to the time constant of the load capacity. Further, for example, when driving in a divided manner of three equal parts as in the present embodiment, the time of T - Tk may be set to a time of about 1 / 4T. That is, since the polarity inversion of the polarity control signal POL is performed at a timing earlier than the rising portion of the horizontal synchronization signal T (T - Tk), at the time of the rising portion of the horizontal synchronization signal ,, each color gradation The potential of the voltage application line is already in a steady state. Furthermore, since the polarity of the polarity control signal POL is reversed after the application of the gradation voltage of each signal line S is completed during one scanning period, the polarity of the -20-1303403 of the gradation voltage is reversed, so even according to the horizontal synchronization signal In the rising portion of the Η, any of the second switch control signals SW-R0, SW-GO, SW_ Β0 becomes a high level, and the correct gradation voltage corresponding to the display data can be applied to the corresponding signal line S. Therefore, it is possible to avoid the deterioration of the display image quality which is conventionally occurring. Further, since the application time (writing time) for applying the gradation voltage to each signal line S can be made equal (time t22), the display image quality can be improved. Further, it is not necessary to improve the driving ability of the output/amplifier circuit 25 2 in order to solve the problem of insufficient application of the gradation voltage to the display pixel PIX, so that an increase in the amount of power consumption can be suppressed. Furthermore, it is set that after the application of the gradation voltage of the signal line S is completed in the previous scanning period, until the second switching control signal SW-R0, SW-GO, SW-B0 during the next scanning period The idle time until the signal becomes high is Δt. The idle time Δt may also be used as the time for setting the potential of the display pixel PIX to a predetermined convergence potential. Also, the idle time Δt can be used as the blanking period. Further, as shown in FIGS. 6A and 6B, the polarity of the polarity control signal POL may be reversed and any of the second switch control signals SW_R〇, SW_G〇, SW_B0 may become a high level. Before, all the switches of the second switch control signals SW_R0, SW_GO, SW_B0 become the high level of the line voltage stabilization time (time t21). Therefore, any voltage of the gradation voltage is applied to the signal line S. In the past, the polarity of the polarity control signal POL was reversed, and before any of the second switch control signals SW_R0, SW_GO, and SW_B0 became a high level, the signal line S was in a high impedance state but passed through the liquid crystal display panel. The parasitic capacitance in 10, the electric potential of the output terminal of the signal driver 20 is -21403, for example, becomes the same potential as the common signal voltage VC 0M, and then is in a state of a potential difference from the color gradation voltage applied to the signal line S. . That is, there is a problem that the gradation voltage is applied to the signal line S, the time before the potential of the signal line S is stabilized, and the writing time to the display pixel PIX becomes long. Therefore, it is set such that the polarity of the polarity control signal POL is reversed, and before the second switch control signal SW_R〇, SW_GO, SW_B0 becomes a high level, the second switch control signal SW_RO, SW_GO, SW_B0 become a high level between the line voltage stabilization time (time t2l), whereby φ applies any voltage of the gradation voltage to the signal line S. This voltage is not much different from the gradation voltage applied thereafter. Therefore, even if a normal gradation voltage is applied to the signal line S, the potential of the signal line s immediately reaches the potential of the gradation voltage, so that the writing time to the display pixel PIX can be shortened. Thus, in this embodiment, since the application of the gradation voltage of each signal line S is completed during one scanning period, and the rising portion of the next horizontal synchronization signal η is earlier, the gradation voltage convergence time is earlier (Τ - The timing of Tk) is used to reverse the polarity of the polarity control signal P 0 L, so that the effect of the time elapsed until the potential of the Φ gradation voltage is stabilized after the polarity reversal is eliminated, even in accordance with the rising portion of the horizontal synchronization signal, 2 The switch control signal SW — R 0, SW_GO, SW Β 0 any signal becomes a high level, and the correct gradation voltage corresponding to the display data can still be applied to the signal line S. Thereby, deterioration of display image quality can be prevented. Further, since the application time (writing time) of the gradation voltage corresponding to the display data applied to each of the signal lines S can be made equal, the image quality can be displayed in a cylinder. Further, it is not necessary to increase the driving ability of the output amplifier circuit 25 2 -22 - 1303403 in order to solve the problem of insufficient application of the gradation voltage of the display pixel ,, so that the power consumption can be reduced. The above description has been made with respect to the embodiment of the present invention, but the form to which the present invention can be applied is not limited to the above-described embodiment, and may be appropriately modified. For example, the first switch group 241 has one switch for every three display data output lines output from the data latch unit 23, and the second switch group 26 1 has one switch for every three signal lines S. However, it is also possible to display one of the data output lines and the signal line S in two or more than three or three. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the construction of a liquid crystal display device of the present invention. Figure 2 is an equivalent circuit of the display pixel of the present invention. Fig. 3 is a view showing the configuration of the main part of the signal driver implementation of the present invention. Fig. 4 is a circuit configuration diagram of the gradation voltage generating unit and the d A C circuit unit of the present embodiment. Figures 5A and 5B show timing diagrams of the main signal signals ® waveforms of conventional liquid crystal display devices. Figs. 6A and 6B are timing charts showing the main signal of the liquid crystal display device of the present embodiment. [Description of main component symbols] 1 Liquid crystal display device 10 Liquid crystal display panel 20 Signal driver 21 Shift temporary storage unit -23- Ί 303403 22 Data temporary storage unit 23 Data latch unit 24 First switch circuit unit 25 DAC circuit unit 26 2nd Switch circuit unit 27 switch switching unit 28 gradation voltage generating unit 28a switch 28b switch 30 scan driver 40 RGB decoder 70 drive amplifier 80 LCD controller 90 voltage generating circuit 91 thin film transistor 92 pixel electrode 93 counter electrode 94 pixel capacitance 95 Auxiliary capacitor 241 1st switch group 251 DAC 3 252 Output amplifier circuit 261 2nd switch group 281 Amplifier 281a Terminal-24- Ί303403 282 Amplifier 282a Terminal 283 Amplifier 283a Terminal 284 Amplifier 284a Terminal 2511 Decoder G Scan line PIX Display pixel Rl· ·· R254 Resistor S, SL··· Sn Signal line SL Level voltage output line SWO.·· SW255 Selector switch

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Claims (1)

1303403 十、申請專利範圍： 1 · 一種顯示驅動裝置，係根據顯示資料來驅動具有以矩陣 狀排列於複數條掃描線及複數條訊號線之各交點附近的 複數個顯示像素的顯示面板， 其具備：色階電壓生成部，生成前述顯示資料之色階 數對應之複數個色階電壓，以基於前述顯示資料對應之 水平同步訊號的時序來反轉前述色階電壓之極性；以及 施加電路部，分別設於前述複數條訊號線中既定數目 之訊號線，根據前述複數，個色階電壓來生成前述顯示資 料對應之顯示訊號電壓，並對前述既定數目之每一條訊 號線依序施加前述顯示訊號電壓； 前述色階電壓生成部之反轉前述色階電壓極性之時 序，係設定於比下次之前述水平同步訊號之時序更早， 且在對前述複數條訊號線施加前述顯示訊號電壓結束後 的時序。 2.如申請專利範圍第1項之顯示驅動裝置，其中，前述色 階電壓生成部之反轉前述色階電壓極性之時序，係設定 於對前述複數條訊號線施加前述顯示訊號電壓結束後， 且比既定之色階電壓收斂時間早，該色階電壓收斂時間 是在前述色階電壓自下次之前述水平同步訊號之時序做 極性反轉後，該色階電壓之電壓値收斂的時間。 3 .如申請專利範圍第1項之顯示驅動裝置，其中，前述顯 示驅動裝置，係進一步具備用以將前述顯示資料載入且 並列地保持的資料保持部； -26- 1303403 前述施加電路部，係具備： 第1開關電路部，用來按照前述水平同步訊號而 選擇並列地保持於前述資料保持部之前述既定數目 個顯示資料； 顯示訊號生成部，用來根據前述顯示資料之色階 來選擇前述複數個色階電壓之任一個，並生成前述 訊號電壓；以及 第2開關電路部，用來按照前述水平同步訊號而 > 選擇前述既定數目之每一條訊號線，分別對所選擇 述既定數目之訊號線依序施加前述顯示訊號電壓， 顯示訊號電壓是前述顯示訊號生成部所生成，且與 第1開關電路部所選擇之前述顯示資料相對應。 4.如申請專利範圍第3項之顯示驅動裝置，其中，前 示資料係數位訊號，前述顯示訊號生成部係具有數 類比變換電路。 5 .如申請專利範圍第3項之顯示驅動裝置，其中，前纽 I 開關電路部，係具有在選擇前述既定數目之任一條 線前，使前述複數條訊號線全部爲選擇狀態的期間 6. —種顯示裝置，係用來在具有以矩陣狀排列於複數 描線及複數條訊號線之各交點附近的複數個顯示像 顯示面板，顯示基於影像訊號之圖像資訊， 該顯示裝置具備： 掃描驅動電路，用來對前述複數條掃描線依序輸 描驅動訊號，將前述顯示像素依序設定於選擇狀態 依序 之各 値， 顯示 依序 之前 前述 前述 述顯 位一 5第2 訊號 〇 條掃 素的 出掃 -27- 1303403 極性反轉訊號生成部，用來以基於前述影像訊號之水 平同步訊號對應之時序來輸出極性反轉之反轉訊號；以 及 訊號驅動電路，具備：生成基於前述影像訊號之顯示 資料之色階數對應之複數個色階電壓，並按照前述反轉 訊號之極性反轉時序反轉前述色階電壓之極性的色階電 壓生成部、以及分別設於前述複數條訊號線中既定數目 之訊號線，以根據前述複數個色階電壓來生成前述顯示 I 資料對應之顯示訊號電壓，並對前述既定數目之每一條 訊號線依序施加前述顯示訊號電壓的施加電路部； 前述反轉訊號之極性反轉時序，係設定於比下次之前 述水平同步訊號之時序更早，且在對前述複數條訊號線 施加前述顯示訊號電壓結束後的時序。 7 .如申請專利範圍第6項之顯示裝置，其中，前述反轉訊 號之極性反轉時序，係設定於前述施加電路部對前述複 數條訊號線施加前述顯示訊號電壓結束後，且比既定之 I 色階電壓收斂時間早，該既定之色階電壓收斂時間是在 前述色階電壓自下次之水平同步訊號之時序做極性反轉 後，該色階電壓之電壓値收斂的時間。 8 ·如申請專利範圍第6項之顯示裝置，其中，前述訊號驅 動電路進一步具備用來將前述顯示資料載入且並列地保 持的資料保持部； 前述施加電路部，係具備： 第1開關電路部，用來按照前述水平同步訊號依序選 -28- 1303403 擇並列地保持於前述資料保持部之前述既定數目之各個 顯示資料； 顯示訊號生成部，用來根據前述顯示資料之色階値來 選擇則述複數個色階電壓之任一個，並生成前述顯不訊 號電壓；以及 第2開關電路部，用來按照前述水平同步訊號依序選 擇前述既定數目之每一條訊號線，並分別對所選擇之前 述既定數目之訊號線，依序施加前述第1開關電路部所 選擇之前述顯示資料對應之顯示資料訊號。 9 ·如申請專利範圍第8項之顯示裝置，其中，前述顯示資 料爲數位訊號，前述顯示訊號生成部具有數位-類比變 換電路。 1 〇·如申請專利範圍第8項之顯示裝置，其中，前述第2開 P痛電路部係具有在選擇前述既定數目之訊號線之任一條 前’使前述複數條訊號線全部爲選擇狀態的期間。 1 1. 一種顯示驅動裝置之驅動控制方法，係用來根據顯示資 料來驅動具有以矩陣狀排列於複數條掃描線及複數條訊 號線之各交點附近的複數個顯示像素的顯示面板； 包含·· 生成則述藏不資料之色階數對應之複數個色階電壓的 步驟； 生成基於前述複數個色階電壓之前述顯示資料對應之 顯示訊號電壓的步驟； 對前述複數條訊號線中既定數目之每一條訊號線依序 -29- 1303403 施加前述顯示訊號電壓的步驟；以及 以在比下次之水平同步訊號之時序更早且在對 數條訊號線施加前述顯示訊號電壓結束後的時序 轉前述色階電壓之極性的步驟。 1 2 ·如申請專利範圍第1 1項之顯示驅動裝置之驅動 法，其中，在反轉前述色階電壓極性之步驟中， 述色階電壓極性之時序，係設定於對前述複數條 施加前述顯示訊號電壓結束後且比既定之色階電 > 時間早，該既定之色階電壓收斂時間是在前述色 自下次之水平同步訊號之時序做極性反轉後，該 壓之電壓値收斂的時間。 1 3 ·如申請專利範圍第1 1項之顯示驅動裝置之驅動 法，其中，生成前述顯示訊號電壓之步驟，係包 前述顯示資料載入且並列地保持的步驟、按照前 同步訊號而依序選擇所保持之前述既定數目之各 資料的步驟、以及根據前述顯示資料之色階値來 > 述複數個色階電壓之任一個，並生成前述顯示訊 的步驟； 對前述複數條訊號線中既定數目之每一條訊號 施加前述顯示訊號電壓的步驟，係包含按照前述 步訊號而依序選擇前述既定數目之每一條訊號線 別對所選擇之前述既定數目之訊號線依序施加前 訊號電壓的步驟。 1 4 ·如申請專利範圍第1 3項之顯示驅動裝置之驅動 前述複 ，來反 控制方 反轉前 訊號線 壓收斂 階電壓 色階電 控制方 含：將 述水平 個顯示 選擇前 號電壓 線依序 水平同 ，並分 述顯示 控制方 -30- 1303403 法，其中，依序施加前述顯示訊號電壓之步驟，係包含 在前述既定數目之訊號線之任一條被選擇前，使前述複 數個訊號線全部爲選擇狀態的步驟。1303403 X. Patent application scope: 1 . A display driving device, which is configured to drive a display panel having a plurality of display pixels arranged in a matrix in the vicinity of respective intersections of a plurality of scanning lines and a plurality of signal lines according to display data. a gradation voltage generating unit that generates a plurality of gradation voltages corresponding to the number of gradations of the display data, and reverses a polarity of the gradation voltage based on a timing of a horizontal synchronization signal corresponding to the display data; and an application circuit unit, Each of the plurality of signal lines is disposed in a predetermined number of signal lines, and the display signal voltage corresponding to the display data is generated according to the plurality of gradation voltages, and the display signal is sequentially applied to each of the predetermined number of signal lines. The timing of inverting the polarity of the gradation voltage by the gradation voltage generating unit is set earlier than the timing of the next horizontal synchronization signal, and after applying the display signal voltage to the plurality of signal lines Timing. 2. The display driving device according to claim 1, wherein the timing of inverting the polarity of the gradation voltage by the gradation voltage generating unit is set after the application of the display signal voltage to the plurality of signal lines is completed. And the convergence time of the gradation voltage is earlier than the predetermined gradation voltage convergence time, and the voltage 値 of the gradation voltage converges after the gradation voltage is reversed from the timing of the next horizontal synchronization signal. 3. The display driving device according to claim 1, wherein the display driving device further includes a data holding unit for loading and holding the display material in parallel; -26-1303403, the application circuit portion, The first switch circuit unit is configured to select and hold the predetermined number of display materials in parallel with the data holding unit in accordance with the horizontal synchronization signal; and display a signal generating unit for selecting according to the color gradation of the display data. And the second switching circuit unit is configured to select each of the predetermined number of signal lines according to the horizontal synchronization signal, and respectively select the predetermined number of each of the plurality of gradation voltages; The signal line sequentially applies the display signal voltage, and the display signal voltage is generated by the display signal generating unit and corresponds to the display data selected by the first switch circuit unit. 4. The display driving device of claim 3, wherein the display signal coefficient bit signal, the display signal generating portion has a analog-to-digital conversion circuit. 5. The display driving device according to claim 3, wherein the front button I circuit portion has a period in which all of the plurality of signal lines are selected before the selection of any one of the predetermined numbers. a display device for displaying image information based on image signals in a plurality of display image display panels arranged in a matrix arrangement between respective intersections of a plurality of lines and a plurality of signal lines, the display device having: a scan driver The circuit is configured to sequentially scan the driving signals for the plurality of scanning lines, and sequentially set the display pixels in the selected state in sequence, and display the foregoing display bits 5 and 2 second signals before the sequence a sweeping -27-1303403 polarity inversion signal generating unit for outputting a polarity inversion reversal signal based on a timing corresponding to the horizontal sync signal of the image signal; and a signal driving circuit having: generating the image based on the image The number of gradations corresponding to the number of gradations of the display data of the signal, and the polarity of the reverse signal is reversed a gradation voltage generating unit that reverses the polarity of the gradation voltage and a predetermined number of signal lines respectively disposed in the plurality of signal lines to generate a display signal corresponding to the display I data according to the plurality of gradation voltages a voltage, and an application circuit portion for sequentially applying the display signal voltage to each of the predetermined number of signal lines; and the polarity inversion timing of the inversion signal is set earlier than a timing of the next horizontal synchronization signal. And applying a timing after the end of the display signal voltage to the plurality of signal lines. 7. The display device of claim 6, wherein the polarity inversion timing of the inversion signal is set after the application circuit unit applies the display signal voltage to the plurality of signal lines, and is longer than the predetermined one. The I gradation voltage convergence time is earlier, and the predetermined gradation voltage convergence time is a time when the gradation voltage of the gradation voltage is inverted from the timing of the next horizontal synchronization signal, and the voltage 値 of the gradation voltage converges. The display device of claim 6, wherein the signal driving circuit further includes a data holding unit for loading and holding the display data in parallel; and the applying circuit unit includes: a first switching circuit And the display unit is configured to hold the display data in the foregoing data holding unit in parallel according to the horizontal synchronization signal, and to display the signal generation unit according to the color tone of the display data. Selecting one of a plurality of gradation voltages to generate the aforementioned display signal voltage; and the second switch circuit portion for sequentially selecting each of the predetermined number of signal lines according to the horizontal synchronization signal, and separately The predetermined number of signal lines are selected, and the display data signals corresponding to the display data selected by the first switch circuit unit are sequentially applied. The display device of claim 8, wherein the display information is a digital signal, and the display signal generating unit has a digital-analog conversion circuit. The display device of claim 8, wherein the second open P pain circuit portion has a function of selecting all of the predetermined number of signal lines to make the plurality of signal lines all selected. period. 1 1. A driving control method for a display driving device for driving a display panel having a plurality of display pixels arranged in a matrix in a vicinity of respective intersections of a plurality of scanning lines and a plurality of signal lines in accordance with display data; a step of generating a plurality of gradation voltages corresponding to the number of gradations of the data; generating a display signal voltage corresponding to the display data based on the plurality of gradation voltages; and a predetermined number of the plurality of signal lines Each of the signal lines sequentially applies the step of displaying the signal voltage in sequence -29-1303403; and repeats the timing after the timing of synchronizing the signal with the next horizontal level and after applying the display signal voltage to the plurality of signal lines The step of the polarity of the gradation voltage. The driving method of the display driving device according to the first aspect of the invention, wherein in the step of inverting the polarity of the gradation voltage, the timing of the polarity of the gradation voltage is set to apply the foregoing to the plurality of stripes After the end of the display signal voltage and earlier than the predetermined gradation power > time, the predetermined gradation voltage convergence time is after the color is reversed from the timing of the next horizontal synchronization signal, and the voltage 値 converges. time. The driving method of the display driving device according to the first aspect of the invention, wherein the step of generating the display signal voltage is performed by the step of loading and juxtaposing the display data, and sequentially following the preamble signal a step of selecting each of the predetermined numbers of data held, and a step of generating a plurality of gradation voltages according to the color gradation of the display data, and generating the foregoing display signal; for the plurality of signal lines The step of applying the foregoing display signal voltage to each of the predetermined number of signals includes sequentially selecting each of the predetermined number of signal lines according to the step signal to sequentially apply the pre-signal voltage to the selected predetermined number of signal lines. step. 1 4 · If the display drive device of the patent application range 13 is driven by the above-mentioned complex, the anti-control side reverses the front signal line voltage convergence level voltage gradation electric control party includes: the horizontal display selects the front voltage line In the same order, the display controller -30-1303403 method is described, wherein the step of sequentially applying the display signal voltage is performed by including the plurality of signals before any one of the predetermined number of signal lines is selected. The lines are all steps to select the state. -31--31-
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