JP3691034B2 - Signal output device and liquid crystal display device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal output device suitable for a capacitive load driving device such as a liquid crystal display, and a liquid crystal display device using the signal output device.
[0002]
[Prior art]
In recent years, liquid crystal display devices used for mobile phones, mobile terminals, and the like have been strongly demanded for high-definition display and low power consumption. That is, regarding the signal output device of the liquid crystal driving device, there is a demand that it can be adapted to increase in the number of pixels (load) and can realize low power consumption.
[0003]
In a conventional signal output device of a liquid crystal driving device, a method in which an operational amplifier that is substantially responsible for driving a load is associated with each pixel of a liquid crystal display (for example, see Patent Document 1).
FIG. 14 is a diagram illustrating an example of a signal output device that is mainstream as a signal output device of a conventional liquid crystal driving device.
[0004]
In the figure, LV0 to LV2 are high impedance signals generated using ladder resistors and the like, and have voltage levels corresponding to three levels of gradation.
SF0 to SF7 are shift register circuits SFR that sequentially transfer the output signal selection information SI for each shift clock CLK, and LF0 to LF7 are register circuits REG that are updated by the load signal HS.
[0005]
The data held in the register circuit REG represents output signal selection information until the next load signal HS arrives, and the selection circuits SW0 to SW7 are controlled by this output signal selection information, and any one of the signals LV0 to LV2 One voltage level is input to the operational amplifiers OP0 to OP7.
The signals impedance-converted by the operational amplifiers OP0 to OP7 are applied to load circuits LD0 to LD7 connected to the output terminals of the operational amplifiers OP0 to OP7.
[0006]
In this conventional signal output device, a signal having a voltage level of one of the signals LV0 to LV2 is output to the load circuit in accordance with the output signal selection information held in each stage of the register circuit REG. become.
In FIG. 14, an IC using eight operational amplifiers is taken as an example, but a liquid crystal driving IC actually used in a mobile phone has a width of about 2 cm due to dimensional restrictions. In the case of a high-definition liquid crystal, 720 electrodes are provided in the width of 2 cm. Then, one operational amplifier (OP0 to OP7) shown in FIG. 14 must be accommodated in a width of 30 microns, which makes designing difficult in terms of space. Note that the selection circuits SW0 to SW7, the storage circuits LF0 to LF7, and the storage circuits SF0 to SF7 do not require a complicated circuit, so there is no space problem.
[0007]
Therefore, a signal output device shown in FIG. 13 is known as a device free from such a space problem.
In this signal output device, operational amplifiers OP10, OP11, and OP12 that input three signals LV0 to LV2 corresponding to gradation levels to input terminals are arranged, and signals LV0 to LV2 are input to selection circuits SW0 to SW7. In the preceding stage, the impedance is converted by an operational amplifier.
[0008]
Note that the driving of the load circuits LD0 to LD7 is performed in accordance with the output signal selection information held in each stage of the register circuit REG, as in the voltage output device shown in FIG. Any one of the output signals of OP12 is selected and applied to the load circuits LD0 to LD7 via the selection circuits SW0 to SW7, thereby driving the load circuit.
[0009]
[Patent Document 1]
JP 2000-305534 A (3rd page, FIG. 1)
[0010]
[Problems to be solved by the invention]
In the signal output device having the configuration shown in FIG. 13, the number of operational amplifiers may be the same as the number of gradations, and the number of operational amplifiers can be significantly reduced as compared with the voltage output device having the configuration shown in FIG. 14.
Incidentally, in the illustrated example, the number of operational amplifiers is three. In a general display device, the relationship of the number of gradations <the number of pixels in one horizontal line is established between the number of gradations and the number of pixels in one horizontal line. Therefore, the signal output device of FIG. 13 can significantly reduce the number of operational amplifiers compared to the signal output device of FIG.
[0011]
However, when both are compared in terms of performance required for individual operational amplifiers, there is a large performance difference between the operational amplifiers constituting the signal output devices of FIG. 14 and FIG.
That is, since the operational amplifier of FIG. 14 only needs to drive one load circuit at all times, the operational amplifier of FIG. 13 has only to have a predetermined performance suitable for driving a single load circuit. Depending on the signal selection state, a wide range of loads from the maximum load (eight load circuits in FIG. 13) to no load are connected.
[0012]
Therefore, it is required that the load circuit be driven so as to satisfy a predetermined specification over the entire range from no load to the maximum load.
Since the three operational amplifiers OP12, OP13, and OP14 shown in FIG. 13 may drive 0 to 8 loads, it is necessary to give each operational amplifier enough capacity to drive the maximum load. There is. Therefore, even when the load is small, an arithmetic drive circuit having a large capacity operates, so that there is a problem that the power consumption becomes large.
[0013]
The present invention has been made to solve the above-described problems, and is a signal output device suitable for low power consumption and semiconductor integrated circuit while having good output characteristics regardless of the size of a connected load. Therefore, the purpose is to realize stable high-quality display and low power consumption of a liquid crystal display device.
[0014]
[Means for Solving the Problems]
  In order to solve the above-described problems, the present invention provides a plurality of operational amplifiers having load driving capability capable of driving all of a plurality of loads by inputting signals of different levels.And 1A selection circuit capable of selecting a plurality of loads for each operational amplifier; delay means for delaying an input signal applied to the plurality of operational amplifiers for a predetermined time; and an input signal before being delayed by the delay means. Based on the level, a signal for determining which output terminal of the plurality of operational amplifiers is connected to each of a plurality of loads, and a selection circuit control means for controlling the selection circuit by this signal; A load counting circuit that counts how many loads are connected to the output terminals of the operational amplifiers and generates a control signal for each operational amplifier according to the count, and the plurality of operational amplifiers include the In accordance with the timing at which the input signal is applied, the control signal of the load counter circuit controls the respective operational amplifiers.The bias current is controlled, and the value of the phase compensation element provided in the feedback loop of the plurality of operational amplifiers is controlled based on the control signal.It is characterized by that.
[0015]
  In addition, the present inventionLiquid crystal displayA liquid crystal display having a plurality of operational amplifiers having load driving capability capable of driving all of a plurality of loads, each having a signal of a different level as input, and liquid crystal elements being a plurality of loads driven by these operational amplifiers A selection circuit that allows one operational amplifier to be selected for a load that is one liquid crystal element and a plurality of loads that are liquid crystal elements to be selected for one operational amplifier; A delay means for delaying input signals applied to the plurality of operational amplifiers for a predetermined time, and an output of the plurality of operational amplifiers for each of the plurality of loads based on the level of the input signal before being delayed by the delay means. A signal for determining whether to connect the terminal is generated, and by this signal, the selection circuit control means for controlling the selection circuit, and how many loads are connected to the output terminals of the respective operational amplifiers. A load counting circuit that counts whether the input signal is applied to the plurality of operational amplifiers, and counts whether the load is applied to the plurality of operational amplifiers. According to the control signal of the counting circuit, each of the operational amplifiersThe bias current is controlled, and the value of the phase compensation element provided in the feedback loop of the plurality of operational amplifiers is controlled based on the control signal.It is characterized by that.
[0016]
  Also,Close the average number of loads connected to the operational amplifierBy dividing a plurality of loads into a plurality of groups, setting one different value of control signal for each group, and selecting the control signal according to the count in the load counting circuit, control for each operational amplifier It is a signal.
[0017]
[Action]
According to the present invention, even when the number of loads connected to each of the plurality of operational amplifiers during operation, that is, the size of the load changes, a control operation is performed to suppress the capability of the operational amplifier in accordance with the change. In particular, by controlling the bias current of multiple operational amplifiers using the output signal of the load counting circuit, it is possible to avoid wasting power consumption, and it is provided in the feedback loop of multiple operational amplifiers. By controlling the value of the phase compensation element, it is possible to prevent the operational amplifier with a lighter load from oscillating. For example, the power consumption is small while maintaining stable output characteristics. A voltage output device suitable for the above can be realized.
[0018]
Further, by using this signal output device, a liquid crystal display device with low power consumption can be realized. In addition, the load is divided into a plurality of groups so that it can be controlled with a small number of control signals, and the vicinity of the average value of the load connected to the operational amplifier is divided densely, so that the efficiency is high. A liquid crystal display device can be provided.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the signal output apparatus of the present invention.
The main configuration of the signal output device of the present embodiment is configured by storage circuits SF0 to SF7, and is configured by a shift register circuit SFR that transfers the output signal selection information SI at the rising edge of the shift clock CLK, and storage circuits LF0 to LF7. The register circuit REG whose data is updated at the rising edge of the load signal HS, the selection circuits SW0 to SW7 controlled by the output voltage selection information of the register circuit REG, and the operational amplifiers OP10, OP11, OP12 that output voltages for each gradation As long as this is the case, the signal output device shown in FIG. 13 is the same. A feature of this embodiment is that it includes a load counting circuit CT0 that generates control signals CS0, CS1, and CS2 for controlling the load driving capabilities of the operational amplifiers OP10, OP11, and OP12. The operational amplifiers OP10, OP11, and OP12 each have a load driving capability capable of driving even when all eight load circuits LD0 to LD7 are connected. In practice, the load may be a little less than the entire load. In the case of a liquid crystal display device, at least one load is connected to each operational amplifier. However, in a special application, the load may not be connected to any of the plurality of operational amplifiers.
[0020]
The signal output device of the present embodiment is provided with three signals of a shift clock CLK, output signal selection information SI, and a load signal HS, and the output signal selection information SI input to the shift register SFR is used for shift. The data is sequentially transferred in the shift register circuit SFR by the clock CLK. N # SF0 to N # SF7 indicate the timing of the output signal of each stage of the shift register circuit.
[0021]
The output signal selection information SI is based on the gradation of the video information, and is a signal for instructing which of the gradation signals LV0, LV1, and LV2 that are the inputs of the operational amplifiers OP10, OP11, and OP12 to be selected. There is. The load signal HS is a signal for updating the output voltage data, and is input every 8 periods of the shift clock CLK (in the case of a liquid crystal display device, once per horizontal period).
[0022]
As soon as the data transfer is completed up to the transfer stage SF7 of the shift register circuit SFR, the load signal HS is generated, and the circuit operation for loading the transfer data into the data holding register circuit SFR is executed. The selection control signals N # LF0 to N # LF7 are output to each stage of the register circuit SFR by the above circuit operation at the timing shown in the figure.
The load clock circuit CT0 is applied with the shift clock CLK, the output signal selection information SI, and the load signal HS, and receives control signals CS0, CS1, and CS2 corresponding to the contents of the output signal selection information SI input between the load signals. Output to operational amplifiers OP10, OP11, OP12, and output signal N via the selection circuits SW0-SW7 controlled by the selection control signals N # LF0-N # LF7 from the register circuit REG. Control is performed to make the capacity suitable for the number of load circuits LD0 to LD7 to which # OP0 to N # OP2 are applied, that is, the size of the load.
[0023]
If four loads are connected to the operational amplifier OP10, the bias current of the operational amplifier OP10 is reduced to an appropriate value, and if three loads are connected to the operational amplifier OP11, the bias current is further reduced. Thus, assuming that one load is connected to the operational amplifier OP12, the bias current is controlled so as to be sufficiently reduced, thereby eliminating waste of power consumption of the operational amplifiers OP10, OP11, OP12.
[0024]
In the case of a liquid crystal display device, in the case of operational amplifiers, for example, assuming that there are 64 operational amplifiers (64 gradations) and the number of loads is 720, each operational amplifier is shown in FIG. Although a dedicated control signal may be generated, such detailed control is not necessary for 720 loads. Therefore, coarse control, for example, four-stage control, that is, four control signals are set in advance. It may be selected and used. Details will be described later.
[0025]
The input terminals of the operational amplifiers OP10, OP11, OP12 are added with the input signal delayed by a predetermined time delay means. This is because the timing at which a signal is applied to the input terminals of the operational amplifiers OP10, OP11, OP12 and the timing at which the operational amplifiers OP10, OP11, OP12 are controlled by the control signals CS0, CS1, CS2 are matched. In the case of a liquid crystal display device, the delay time of the delay means may be one horizontal period, and the delay means may be an ordinary delay line or a memory.
[0026]
FIG. 2 is a timing chart illustrating the timing of each signal during the operation of the signal output device shown in FIG.
In FIG. 2, the output signal selection information SI is added to the shift register circuit SFR and the load counting circuit CTO, and any one of the input signals LV0, LV1, LV2 of the operational amplifiers OP10, OP11, OP12 is used as the load circuit LD0-LD7. 2, SI numbers 0, 1 and 2 in FIG. 2 correspond to LV0, LV1 and LV2, and indicate what signals are applied to the load circuits LD0 to LD7.
[0027]
In response to the instruction of the output signal selection information SI, the signals LV2, LV1, LV1, LV2, LV0, LV2, LV2, LV1 are once sent from the selection circuit SW0 to SW7 in order from SW0 in synchronization with the rising edge of the load signal HS2. In addition, in synchronization with the rise of the load signal HS3, the selection circuits SW0 to SW7 output signals LV2, LV0, LV2, LV1, LV1, LV0, LV0, and LV1 in order from SW0.
[0028]
When the load signal HS2 rises, the output information of the shift register SFR is written into the register REG and is held for t2. FIG. 2 shows a state in which signals N # SF0 to N # SF7 (2120221) at the time of rising of the load signal HS2 are written as signals N # LF0 to N # LF7 (2120221) and held for the period t2.
Looking at the waveform for each pulse section of the load signal HS, eight output signal selection information SI input to the shift register SFR during the period t1 from the rise of the load signal HS1 to the rise of the load signal HS2 is one LV0. LV1 means three and LV2 means four. In response to this, the load measuring circuit CTO counts the content of the output signal selection information SI, that is, the number of LV0, LV1, and LV2, and outputs this as a control signal. According to this, the control signals CS0, CS1, and CS2 output from the load counting circuit CTO in synchronization with the load signal HS2 are 1, 3, and 4 (indicated by CS0, CS1, and CS2 in FIG. 2), respectively.
[0029]
The control signals CS0, CS1, and CS2 have one load circuit that outputs the signal LV0 and three load circuits that output the signal LV1 during the period t2 from the load signal HS2 to the arrival of the next load signal HS3. This means that there are four load circuits that output the signal LV2.
The operational amplifiers OP10, OP11, OP12 have their load driving capabilities controlled by these control signals CS0, CS1CS2. In the above example, one operational amplifier OP10 is connected to one load circuit, three are connected to OP11, and four are connected to OP12. The load driving capability is controlled by the number of connected loads. It should be noted that at the input terminals of the operational amplifiers OP10, OP11, OP12, a video signal delayed by one horizontal period is added to the grayscale signal generation circuit, and a plurality of grayscale voltages corresponding to the video signal are created. Added.
[0030]
  As can be seen from FIG. 2, the output signal CS0 of the load counting circuit CTO,CS 1, CS 2Is held for t2, and this signal ist1It is made based on the output signal selection signal SI for the period. Therefore, the timing of the input signals of the operational amplifiers OP10, OP11, OP12 and the operational amplifiers OP10, OP11, OP12 are signaled.CS 0, CS 1, CS 2The timing to control with is the same. That is, information on the input signal is obtained one horizontal period ahead of the input signals of the operational amplifiers OP10, OP11, OP12, and the control signalCS 0, CS 1, CS 2Is making.
[0031]
Next, specific means for controlling the load driving capability of the operational amplifier will be described. FIG. 3 is a conceptual diagram showing an operational amplifier including a variable bias current source VRI, a variable resistor VRR, a variable capacitor VRC, and a variable effective size (W / L) transistor VRT. Four parameters are controlled by a control signal CNT. 1 shows an operational amplifier that can optimally control the. The control signal CNT corresponds to the control signals CS0, CS1, and CS2. VP and VN are a pair of signal input terminals, VB is a bias voltage application terminal, and OUT is an output terminal.
[0032]
FIG. 4 is a block diagram specifically illustrating a configuration example of an operational amplifier, which includes a variable bias current source VRI, a variable resistor VRR for phase compensation, a variable capacitor VRC for phase compensation, and a variable effective size (W / L). The circuit arrangement with the transistor VRT is shown, the bias current source of the differential amplifier circuit unit DAC and the output circuit unit OPC is configured as a variable bias current source VRI, and the differential of the differential amplifier circuit unit DAC An element for phase compensation, that is, a variable capacitor VRC and a variable resistor VRR are connected in series between the output generation point and the output terminal OUT of the output circuit unit OPC, that is, in the feedback loop, and further, an output constituting the output circuit unit OPC The circuit configuration is such that the MOS transistor is a variable effective size (W / L) transistor VRT. These variable parts require at least a variable bias current source VRI to reduce power consumption. The phase compensation variable resistor VRR and variable capacitor VRC are for preventing circuit oscillation, and the transistor VRT is for preventing ringing and is provided as necessary.
[0033]
FIG. 5 is a diagram showing a specific circuit configuration example that enables selection of four types of capacitance values as the variable capacitance VRC shown in FIG. 3 and FIG. 4, and the capacitance C is connected between the terminals XX ′. In addition to this connection, a circuit configuration in which a capacitor C of the same size and a capacitor 2C of twice the size are connected in parallel via switches S1 and S2 whose opening and closing is controlled by the control signal CNT in parallel with this capacitor. ing.
[0034]
According to this configuration, the capacitance value between the terminals XX 'is C by opening both switches S1 and S2, 2C by closing only switch S1, and by closing only switch S2. By closing both switches 3C and S1 and S2, 4C is obtained, and four capacitance values can be selected.
FIG. 6 is a diagram showing a specific circuit configuration example that enables selection of four resistance values as the variable resistance VRR shown in FIG. 3 and FIG. A resistor R of the same size and a resistor 2R of twice the size are connected in series, and switches S1 and S2 whose switching is controlled by a control signal CNT are connected in parallel with the resistor 2R and one resistor R. It has a circuit configuration.
[0035]
According to this configuration, the resistance value between terminals Z and Z 'is 4R by opening both switches S1 and S2, and 3R by closing only switch S1, and by closing only switch S2. 2R, and by closing both switches S1 and S2, it becomes R, and four resistance values can be selected.
FIG. 7 is a diagram showing a specific circuit configuration example that enables selection of four kinds of current values as the variable bias current source VRI shown in FIGS. 3 and 4, and a transistor between terminals Y and Y ′. The MOS transistor MOST1 having the same size as the W / L is connected to the MOS transistor MOST1 having the same transistor size through the switches S1 and S2 whose opening / closing is controlled by the control signal CNT. The circuit configuration is such that a MOS transistor MOST3 having a transistor size of 2 W / L is connected in parallel with the MOS transistor MOST1.
[0036]
According to this configuration, when the bias current value determined by the gate bias VG of the MOS transistor and the transistor size W / L is I, the bias current flowing between the terminals YY 'opens both the switches S1 and S2. By closing only switch S1, 2I, by closing only switch S2, 3I, and by closing both switches S1 and S2, it becomes 4I. Selectable.
[0037]
FIG. 8 is a diagram showing a specific circuit configuration example that enables selection of four effective sizes as the variable effective size (W / L) transistor VRT shown in FIG. 3 and FIG. A MOS transistor MOST1 having a transistor size of W / L is connected between U ', and a MOS transistor MOST2 having the same transistor size is selected via switches S1 and S2 whose opening / closing is controlled by a control signal CNT. The circuit configuration is such that a MOS transistor MOST3 having a double transistor size 2 W / L is connected in parallel with the MOS transistor MOST1.
[0038]
According to this configuration, when the three MOS transistors connected in parallel are viewed as one MOS transistor, the effective size (W / L) is W / L by opening both the switches S1 and S2. Closing only switch S1 is 2W / L, closing only switch S2 is 3W / L, and closing both switches S1 and S2 is 4W / L, giving four effective sizes. Selectable.
[0039]
Next, the load counting circuit CTO will be described with reference to FIGS.
FIG. 9 is a block diagram showing the configuration of the load counting circuit corresponding to the case of the number of gradation levels of 3 shown in FIG. 1, and the three that detect coincidence with “0”, “1”, and “2”, respectively. The coincidence count circuits COC0, COC1, and COC2 are connected in parallel.
The load counting circuit configured as shown is applied with the shift clock CLK, the output signal selection information SI, and the load signal HS for determining the data update timing. From the three coincidence counting circuits COC0, COC1, and COC2, Control signals CS0, CS1, and CS2 are output.
[0040]
FIG. 10 is a block diagram showing the internal configuration of the coincidence count circuit COC2 that outputs the control signal CS2 among the three coincidence count circuits shown in FIG. 9. The coincidence detection circuit COD2 includes output signal selection information. SI and a fixed value for comparison “2” (corresponding to 2 of the output signal selection information SI) are input. The output C # C2 of the coincidence detection circuit COD2 becomes high level “H” only when the output signal selection information SI is “2” as shown in FIG. This signal is ANDed with the shift clock CLK by the AND gate AG, and becomes the output L # C2 shown in FIG. This output L # C2 is input to the counter circuit CC as a clock input. The counter circuit CC operates so as to increase the count value by “1” every time the clock input rises. The output P # C2 (shown in FIG. 11) of the counter circuit CC is input to the register circuit RC, and the load signal HS is connected to the reset inversion input of the counter circuit CC and serves as the clock input of the register circuit RC. Therefore, the output CS2 of the register circuit RC is the numerical information (as shown in FIG. 11) taken in at the next rising edge of the load signal HS, the number counted by the counter circuit CC during the period when the level of the load signal HS is “0”. As shown in the example, 4) is shown. That is, the counter output P # C2 is incremented by 1 every time the AND gate output L # C2 rises during the period when the level of the load signal HS is “0”, and reset to “0” at the rise of the load signal HS. Is done. The register circuit output CS2 updates the value of the counter output P # C2 at the rising edge of the load signal HS, and in this case becomes “4”.
[0041]
FIG. 10 shows a specific configuration of the coincidence count circuit COC2 which is one of the circuit elements constituting the load counting circuit of FIG. 9, but the coincidence count circuit COC0 shows a comparison applied to the coincidence detection circuit. The fixed value for use is “0”, and the match count circuit COC1 has the same configuration except that the fixed value for comparison applied to the match detection circuit is set to “1”. Therefore, in this case, the control outputs CS0 and CS1 output from the respective register circuits RC are the shift clocks CLK that have passed through the AND gate AG when the output signal selection information SI matches “0”. The value “1” indicating the number and the value “2” indicating the number of shift clocks CLK that have passed through the AND gate AG when the output signal selection information SI matches “1”.
[0042]
As described above, in the coincidence counting circuit constituting the load counting circuit CTO, the coincident output signal selection information is counted in the counter circuit during the period when the level of the load signal HS is “0”, and the next incoming load signal HS The count value is transferred to the register circuit RC at the rising edge, and the operation is repeated when the counter circuit CC is initialized and the count value is reset to “0”.
[0043]
FIG. 12 shows a block diagram when a liquid crystal display panel is used as a load. In FIG. 12, LCDP is a liquid crystal display panel, a plurality of gate lines G1, G2, G3... Coming from the gate driver GD and a plurality of data lines S1, S2, S3 coming from the selection circuit SW of the source driver SD. ..., a plurality of TFTs, and a liquid crystal element connected to them. The contents of the source driver SD are the same as those shown in FIG. A gradation signal generation circuit GSG is provided on the input terminal side of the operational amplifier circuit OP, and a voltage signal of, for example, 64 gradations corresponding to the video signal is generated here. A signal obtained by delaying the video signal from the video signal terminal T by one horizontal period is added to the input terminal of the gradation signal generation circuit GSG via the 1H delay circuit DL. The signal at the video signal input terminal T is applied to the control signal generation circuit CSG, and the load signal HS, the output signal selection information SI, and the clock signal CLK are generated.
[0044]
Now, when a voltage is applied to the gate line G2, if a voltage corresponding to the video signal from the operational amplifier OP is present on the data line S1, this voltage is applied to the liquid crystal element L1 via the TFT1. This liquid crystal element is an example of the load of FIG. 1, and there are actually 720 pieces.
The information of the input signal applied to the operational amplifier OP in the presence of the 1H delay circuit DL is previously extracted by the control signal generation circuit CSG. Based on the information of the input signal obtained by the information acquisition means, a signal for determining which output terminal of the plurality of operational amplifiers is connected to each of the plurality of loads is generated, and the selection circuit SW is selected by this signal. Control is performed by control means (shift register circuit REG and register circuit).
[0045]
The load counting circuit CTO counts how many loads are connected to the output terminal of each operational amplifier OP, and generates a control signal for each operational amplifier in accordance with this count. The load driving capability of each operational amplifier OP is controlled by the control signal of the load counting circuit CTO in accordance with the timing at which the input signal is applied to the plurality of operational amplifiers OP.
[0046]
For each of the 64 operational amplifiers OP, a dedicated control signal is generated by the load counting circuit CTO, and it is possible to finely control each of the operational amplifiers OP. However, as described above, rough control is performed. It is more efficient.
Specifically, description will be made assuming a case of 64 operational amplifiers OP and 720 loads. The load is divided into a plurality of groups, specifically four groups. A control signal of value V1 for 1 to 19 loads, V2 for 20 to 99 loads, V3 for 100 to 299 loads, and V4 control signals for 300 to 720 loads. Set in advance. These control signals are set so as to provide a load driving capability suitable for the number of loads connected to the operational amplifier OP. For example, in the case of an operational amplifier OP to which 1 to 19 loads are connected, even if the load driving capacity is optimal for 10 loads, it may not be optimal for 1 or 19 loads. However, it can be set so as to provide a sufficiently satisfactory load driving capability.
[0047]
The load counter circuit CTO has 64 coincidence count circuits, and different coincidence count circuits are set with different gradation voltages (input signal levels of the operational amplifier OP). The gradation voltage and the signal applied to the resist circuit SFR are matched. Every time they match, 1 is added and the number of loads connected to each operational amplifier OP is counted for a predetermined time (one horizontal period). Based on this count, the control signal V1 is selected when the load is 1 to 19, V2 when the load is 20 to 99, V3 when the load is 100 to 299, and V4 when the load is 300 to 720. Since the control is in four stages, the switching circuits shown in FIGS. 5, 6, 7 and 8 can be used.
[0048]
One operational amplifier OP is connected to 720 ÷ 64 = 11.25, that is, an average of 11 and 12 loads. There are few opportunities for many loads to be connected. Therefore, control is performed mainly in places where the load is small. That is, when the load is divided into groups, the vicinity of the number of average loads connected to each operational amplifier OP is divided densely.
[0049]
In the case of this embodiment, it is considered that control signals for respective operational amplifiers are generated by selecting four preset control signals in accordance with the count in the load counting circuit CTO.
[0050]
【The invention's effect】
As described above, according to the present invention, in the signal output device constituted by a plurality of operational amplifiers, the load counting circuit counts the number of load circuits connected to each operational amplifier, and the load driving capability of each operational amplifier. Can be maintained with low waste driving capacity controlled according to the size of the connected load, so that an appropriate bias current is selected while ensuring good output characteristics according to the required specifications. It becomes possible. In addition, by controlling the value of the phase compensation element provided in the feedback loop of multiple operational amplifiers, it is possible to prevent the operational amplifiers with lighter loads from oscillating and maintain stable output characteristics. However, a signal output device with low power consumption can be obtained.
[0051]
In addition, according to the present invention, even when the number of display pixels is increased in accordance with the demand for higher definition or larger size of the liquid crystal panel, the liquid crystal has stable high quality display and low power consumption. A display device can be realized. In addition, the load is divided into a plurality of groups so that it can be controlled with a small number of control signals, and the vicinity of the average value of the number of loads connected to the operational amplifier is divided densely. A liquid crystal display device with good quality can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a signal output device of the present invention.
FIG. 2 is a timing diagram illustrating the timing of each signal during operation of the signal output device shown in FIG.
FIG. 3 is a conceptual diagram of an operational amplifier incorporating a variable bias current source, a variable resistor and a variable capacitor used in the signal output apparatus of the present invention.
FIG. 4 is a block diagram specifically showing the configuration of the operational amplifier.
5 is a diagram showing a specific circuit configuration example of the variable capacitor shown in FIGS. 3 and 4. FIG.
6 is a diagram showing a specific circuit configuration example of the variable resistor shown in FIGS. 3 and 4. FIG.
7 is a diagram showing a specific circuit configuration example of the variable bias current source shown in FIGS. 3 and 4. FIG.
8 is a diagram illustrating a specific circuit configuration example for realizing the variable effective size (W / L) transistor shown in FIGS. 3 and 4. FIG.
9 is a block diagram showing a configuration of a load counting circuit corresponding to the case of the number of gradation levels of 3 shown in FIG.
10 is a block diagram showing an internal configuration of a part of the block of FIG. 9;
11 is a timing chart showing a timing relationship of signals at various parts of the block shown in FIG. 10;
FIG. 12 is a block diagram showing an embodiment of a liquid crystal display device of the present invention.
FIG. 13 is a block diagram of a conventional signal output device.
FIG. 14 is a block diagram of another conventional signal output device.
[Explanation of symbols]
OP10 to OP12, OP operational amplifier
SFR shift register circuit
SF0 to SF7 memory circuit
REG register circuit
LF0 to LF7 Memory circuit
SW0 to SW7, SW selection circuit
LD0 to LD7 load circuit
CT0 load counting circuit
VRI variable bias current source
VRR variable resistance
VRC variable capacity
VRT variable effective size (W / L) transistor
DAC differential amplifier circuit
OPC output circuit
C, 2C capacity
R, 2R resistance
  S1, S2 switch
MOST1 to MOST3 MOS transistor
COC0 to COC2 coincidence count circuit
COD2 coincidence detection circuit
AG AND gate
CC counter circuit
RC register circuit
DL 1H delay circuit
GSG gradation signal generation circuit
CSG control signal generator
SD source driver
LCDP LCD panel

Claims (4)

As input respective different levels of signals, and a plurality of operational amplifiers having a load drive capacity capable of driving all of the plurality of loads, a selection circuit which can select a plurality of load for one operational amplifier And delay means for delaying the input signals applied to the plurality of operational amplifiers for a predetermined time, and based on the level of the input signal before being delayed by the delay means, which one of the plurality of operational amplifiers is in each of the plurality of loads. A signal for determining whether to connect the output terminal is generated, and the selection circuit control means for controlling the selection circuit by this signal, and how many loads are connected to the output terminals of the respective operational amplifiers are counted. And a load counting circuit for generating a control signal for each operational amplifier according to the count, and in accordance with the timing at which the input signal is applied to the plurality of operational amplifiers, Controls the bias current of the respective operational amplifier by the control signal of the duty count circuit, the value of the phase compensation element provided in the feedback loop of the plurality of operational amplifiers that to control on the basis of the control signal A signal output device.   The load counting circuit has one coincidence count circuit for one operational amplifier. The coincidence count circuit includes an input signal level of the operational amplifier and a signal level of information of the input signal applied to the selection circuit control means. 2. The signal according to claim 1, wherein the count number is increased each time the counts are matched, the count number for a predetermined time is held, and the control signal is used to control the operational amplifier for a next predetermined time. Output device. A liquid crystal display having a plurality of operational amplifiers having load driving capability capable of driving all of a plurality of loads, each having a signal of a different level as input, and liquid crystal elements being a plurality of loads driven by these operational amplifiers A selection circuit that allows one operational amplifier to be selected for a load that is one liquid crystal element and a plurality of loads that are liquid crystal elements to be selected for one operational amplifier; A delay means for delaying input signals applied to the plurality of operational amplifiers for a predetermined time, and an output of the plurality of operational amplifiers for each of the plurality of loads based on the level of the input signal before being delayed by the delay means. A signal for determining whether to connect the terminal is generated, and by this signal, the selection circuit control means for controlling the selection circuit, and how many loads are connected to the output terminals of the respective operational amplifiers. A load counting circuit that counts whether the input signal is applied to the plurality of operational amplifiers, and counts whether the load is applied to the plurality of operational amplifiers. A bias current of each of the operational amplifiers is controlled by the control signal of the counting circuit, and a value of a phase compensation element provided in a feedback loop of the plurality of operational amplifiers is controlled based on the control signal. A liquid crystal display device. A plurality of loads are divided into a plurality of groups by making the vicinity of the average number of loads connected to the operational amplifier dense, and a control signal having one different value is set for each group, and the load counting circuit according to the count in the load counting circuit 4. The liquid crystal display device according to claim 3 , wherein the control signal is selected as a control signal for each operational amplifier.

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