JP2003228080A - Display pixel circuit and planar display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defective pixels from occurring which flicker in the still picture display mode. <P>SOLUTION: The planar display device is provided with display pixels PX of a structure holding a light modulation layer between a pair of electrodes, pixel switches 11 for retrieving video signals, static memory parts 13 for holding the video signals applied to the display pixels PX from the pixel switches, and connection control parts 14 for controlling the electrical connections between the display pixels PX and the static memory parts 13. Especially, the static memory parts 13 have a larger current driving capacity than the connection control parts 14 so as to absorb transient currents flowing during a transitional state of the connection control parts 14. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device in which each display pixel has a structure in which a light modulation layer is sandwiched between a first electrode and a second electrode, and in particular, a static display held in a memory section provided for each display pixel. The present invention relates to a flat display device which periodically inverts the polarity of an image display signal and applies it to the display pixel.

[0002]

2. Description of the Related Art For example, a liquid crystal display device is characterized by being thin, small, and lightweight, and is used in a mobile phone or a PDA (Portable Digital As
It is widely used as an image monitor for portable terminal equipment such as a computer. Since such portable terminal devices generally operate using a battery as a power source, the consumption rate of the battery greatly affects the usable time. For these reasons, low power consumption of liquid crystal display devices has been actively studied.

Conventionally, in an active matrix type liquid crystal display device, it has been common to use an amorphous silicon thin film transistor as a pixel switch for taking in a video signal supplied from an external drive circuit and applying it to a display pixel. Advances in thin film formation technology have made it possible to obtain high-quality images by forming polysilicon thin film transistors made of polysilicon having a mobility higher than that of amorphous silicon on the same substrate as constituent elements of pixel switches and drive circuits. . In such a situation where the polysilicon thin film transistor can be used, the S
A memory technology represented by a RAM (Static Random Access Memory) is also used to reduce the power consumption of a liquid crystal display device. In this SRAM technology, a plurality of memory units are configured by combining polysilicon thin film transistors, and are provided for each of a plurality of display pixels forming a display screen. Each memory unit is electrically connected to the corresponding display pixel via the connection control unit, holds the video signal captured by the pixel switch and applied to the display pixel, and drives the display pixel corresponding to this video signal. Therefore, the output operation of the drive circuit can be intermittently performed to display a still image when the video signal does not need to be updated frequently.

In the field of liquid crystal display devices, generally, in order to prevent uneven distribution of liquid crystal material in a liquid crystal layer sandwiched as a light modulation layer between a plurality of pixel electrodes and a single common electrode facing these pixel electrodes. In addition, frame inversion driving is known in which the polarities of video signal voltages applied to a plurality of display pixels are inverted, for example, in units of vertical scanning (frame) periods. In addition, in order to suppress the occurrence of flicker, in addition to frame inversion drive, H line inversion drive that inverts the polarity of the voltage applied to the display pixel every one or multiple rows, and application to the display pixel every one or multiple columns V line inversion drive is known in which the polarity of the applied voltage is inverted. Further, in the liquid crystal display device with a built-in memory, for example, the H line inversion drive is used in the normal display mode, and the frame inversion drive is adopted in the still image display mode in order to further reduce the power consumption. The connection control unit is used not only for controlling electrical connection between the display pixel and the memory unit but also for controlling such polarity inversion.

In addition, the common inversion method may be adopted in order to reduce the drive voltage required for the above polarity inversion. In this common inversion method, when the maximum value of the potential difference between the pixel electrode and the common electrode is set to 5 V for polarity inversion, the potential of the common electrode is periodically set to 0 V.
And + 5V from one to the other, and in synchronization with this, the pixel signal is driven by inverting the level of the video signal voltage in the range of 0V to + 5V. On the other hand, in the method of fixing the potential of the common electrode to 0V, it is necessary to invert the level of the video signal voltage in the range of -5 to + 5V to drive the pixel electrode.

[0006]

However, if the common inversion method is adopted in the above-described memory built-in type liquid crystal display device, a defective pixel which becomes a black defect point when the entire display screen is displayed in white is displayed as a still image. It has been reported to occur in mode.

An object of the present invention is to provide a display pixel circuit and a flat panel display device capable of preventing generation of defective pixels which become a dark spot in the still image display mode and ensuring high quality and reliability.

[0008]

According to the present invention, a display pixel having a structure in which a light modulation layer is sandwiched between a pair of electrodes, a pixel switch for capturing a video signal, and an image applied from the pixel switch to the display pixel. A static memory unit that holds signals and a connection control unit that controls the electrical connection between the display pixel and the static memory unit are provided. The static memory unit absorbs the current that temporarily flows during the state transition of the connection control unit. Thus, a display pixel circuit having a larger current drive capability than the connection controller is provided.

Further, according to the present invention, there is provided a flat display device in which a plurality of the above-mentioned display pixel circuits are arranged in a substantially matrix form.

In these display pixel circuits and flat panel display devices, the static memory section has a larger current drive capacity than the connection control section so as to absorb the current that temporarily flows during the state transition of the connection control section. For example, even if a current temporarily flows from the display pixel to the static memory unit due to a potential change caused by the polarity reversal during the state transition of the connection control unit synchronized with the polarity reversal of the display pixel, the static memory unit absorbs the current. The change of the video signal in the holding state is suppressed. As a result, it is possible to prevent the generation of defective pixels, which become dark spots in the still image display mode, and to ensure high quality and reliability.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flat panel display device according to an embodiment of the present invention will be described below with reference to the drawings. This flat panel display is a liquid crystal display used as an image monitor of a mobile terminal device having a still image display mode for displaying a still image in order to reduce power consumption in addition to a normal display mode capable of displaying a moving image and a still image. It is a device.

FIG. 1 shows a schematic circuit configuration of the flat display device, FIG. 2 shows a schematic sectional structure of the flat display device, and FIG. 3 shows an equivalent circuit around the display pixel shown in FIG. .

This flat display device comprises a liquid crystal display panel 1 and a liquid crystal controller 2 for controlling the liquid crystal display panel 1. The liquid crystal display panel 1 has a structure in which, for example, the liquid crystal layer LQ is held as a light modulation layer between the array substrate AR and the counter substrate CT, and the liquid crystal controller 2 is arranged on a drive circuit substrate independent of the liquid crystal display panel 1. It

The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix in the display area DS on the glass substrate, and a plurality of scanning lines Y (Y1 to Ym) formed along rows of the plurality of pixel electrodes PE. ), A plurality of signal lines X (X1 to Xn) formed along the columns of the plurality of pixel electrodes PE, the signal lines X1 to Xn, and the scanning lines Y1 to Ym, which are arranged adjacent to each other at respective intersecting positions, and each corresponding scan. In response to the scanning signal from the line Y, the pixel switch 11 that takes in the video signal Vpix from the corresponding signal line X and applies it to the corresponding pixel electrode PE, the scanning line Y1
~ Scanning line drive circuit 3 for driving Ym and signal line X1 ~
A signal line drive circuit 4 for driving Xn is provided. Each pixel switch 11 is composed of an N-channel polysilicon thin film transistor having an LDD structure and a double gate structure, for example. Here, the LDD length is 2 μm on each side.
The scanning line drive circuit 3 and the signal line drive circuit 4 are configured by combining a plurality of polysilicon thin film transistors formed on the array substrate AR together with the thin film transistors of the pixel switch 11. The counter substrate CT includes a single common electrode CE arranged to face the plurality of pixel electrodes PE, a color filter (not shown), and the like.

The liquid crystal controller 2 receives, for example, a video signal and a synchronizing signal supplied from the outside, and generates a pixel video signal Vpix, a vertical scanning control signal YCT and a horizontal scanning control signal XCT in the normal display mode. The vertical scanning control signal YCT includes, for example, a vertical start pulse, a vertical clock signal, an output enable signal ENAB, etc., and is supplied to the scanning line driving circuit 3. The horizontal scanning control signal XCT includes a horizontal start pulse, a horizontal clock signal, a polarity inversion signal, etc., and is supplied to the signal line drive circuit 4 together with the video signal Vpix.

The scanning line driving circuit 3 includes a shift register and is controlled by the vertical scanning control signal YCT so as to sequentially supply the scanning signal for conducting the pixel switch 11 to the scanning lines Y1 to Ym every one vertical scanning (frame) period. It The shift register selects one of the plurality of scanning lines Y1 to Ym by shifting a vertical start pulse supplied every one vertical scanning period in synchronization with a vertical clock signal,
A scan signal is output to the selected scan line with reference to the output enable signal ENAB. The output enable signal ENAB is maintained at a high level in order to permit the output of the scanning signal in the effective scanning period of the vertical scanning (frame) period, and the scanning is performed in the vertical blanking period excluding the effective scanning period from the vertical scanning period. It is kept low to inhibit signal output.

The signal line driving circuit 4 has a shift register and a sampling output circuit, and serial-parallel converts and samples a video signal input in one horizontal scanning period (1H) in which each scanning line Y is driven by the scanning signal. It is controlled by the horizontal scanning control signal XCT so that the analog video signal Vpix is supplied to the signal lines X1 to Xn.

The common electrode CE is set to the common potential Vcom as shown in FIG. The common potential Vcom is level-reversed from one of 0V and 5V every horizontal scanning period (H) in the normal display mode, and from one of 0V and 5V every one frame period (F) in the still image display mode. The level is inverted. In the normal display mode, one horizontal scanning period (H) as in the present embodiment
Instead of inverting the level of the common potential Vcom every time, the level of the common potential Vcom may be inverted for example every 2H or every one frame period (F).

The polarity inversion signal is supplied to the signal line drive circuit 4 in synchronization with the level inversion of the common potential Vcom. Then, in the normal display mode, the signal line driving circuit 4 inverts the level of the video signal Vpix having an amplitude of 0V to 5V in response to the polarity inversion signal so as to have a polarity opposite to the common potential Vcom, and outputs the signal. In the still image display mode, the operation is stopped after outputting the video signal whose gradation is limited for the still image.

The liquid crystal layer LQ of the liquid crystal display panel 1 has a common potential Vcom of 0 V set on the common electrode CE, for example.
Is a normally white in which black is displayed by applying the video signal Vpix of 5 V to the pixel electrode PE, and as described above, in the normal display mode, the potential relationship between the video signal Vpix and the common potential Vcom is one horizontal scanning period. The H common inversion drive, which is alternately inverted every (H), is adopted, and the frame inversion drive, which is alternately inverted every frame in the still image display mode, is adopted. The display screen is composed of a plurality of display pixels PX. Each display pixel PX includes the pixel electrode PE, the common electrode CE, and the liquid crystal material of the liquid crystal layer LQ sandwiched therebetween.
Furthermore, a plurality of static memory units 13 and a plurality of connection control units 14 are provided for the plurality of display pixels PX, respectively. As shown in FIG. 3, the pixel electrode PE is connected to the pixel switch 11 that selectively takes in the video signal Vpix on the signal line X, and further, for example, a capacitance is connected to an auxiliary capacitance line set to the common potential Vcom of the common electrode CE. Join.
The pixel electrode PE and the common electrode CE form a liquid crystal capacitance via a liquid crystal material, and the pixel electrode PE and the auxiliary capacitance line are in parallel with the liquid crystal capacitance without the liquid crystal material.
Make up.

When the pixel switch 11 is driven by the scanning signal from the scanning line Y, the video signal Vpi on the signal line X
x is applied to the display pixel PX. The auxiliary capacitance 12 has a capacitance value sufficiently larger than the liquid crystal capacitance, and is charged / discharged by the video signal Vpix applied to the display pixel PX. Auxiliary capacity 1
When 2 holds the video signal Vpix by this charging / discharging, this video signal Vpix compensates the fluctuation of the potential held in the liquid crystal capacitance when the pixel switch 11 becomes non-conducting, whereby the pixel electrode PE and the common electrode. The potential difference between CEs is maintained.

Further, each static memory unit 13 has P
Channel polysilicon thin film transistors Q1, Q3, Q
5 and N-channel polysilicon thin film transistors Q2 and Q4 having an LDD structure, and holds the video signal Vpix applied from the pixel switch 11 to the display pixel PX. Each connection control unit 14 has LDD-structure N-channel polysilicon thin film transistors Q6 and Q7, and not only controls the electrical connection between the display pixel PX and the static memory unit 13, but also stores an image stored in the static memory unit 13. It also serves as a polarity control circuit that controls the output polarity of the signal.
Here, the LDD length is 2 μm on each side. The thin film transistors Q1 and Q2 operate at a power supply voltage between the power supply terminal Vdd (= 5V) and the power supply terminal Vss (= 0V).
The complementary inverter INV1 is formed, and the thin film transistors Q3 and Q4 form a second complementary inverter INV2 that operates at the power supply voltage between the power supply terminals Vdd and Vss. The output terminal of the complementary inverter INV2 is a complementary inverter IN
These complementary inverters I connected to the input terminal of V1
A column inverter circuit is composed of NV1 and INV2. The output terminal of the complementary inverter INV1 is connected to the input terminal of the complementary inverter INV2 via the thin film transistor Q5. Here, the thin film transistor Q5 constitutes a loop switch that feeds back the output of the cascade inverter circuit as the input of the cascade inverter circuit. The thin film transistor Q5 is controlled, for example, via the scanning line Y, and does not conduct in the frame period in which the pixel switch 11 conducts due to the rising of the scanning signal from the scanning line Y, but conducts in the frame period subsequent to this frame. As a result, the thin film transistor Q5 is maintained in a non-conductive state at least until the pixel switch 11 captures the video signal Vpix.

As shown in FIG. 4, the thin film transistor Q6 has a double gate structure in which two gate electrodes G1 and G2 are formed on the polysilicon semiconductor thin film SF in an insulating manner, and the thin film transistor Q7 also has the same double gate structure as the thin film transistor Q6. Have a structure. These thin film transistors Q6 and Q7 are, for example, 1 in the still image display mode.
It is controlled by polarity control signals POL1 and POL2 which are alternately set to a high level for each frame. The thin film transistor Q6 is connected between the pixel electrode PE and the input end of the complementary inverter INV2 and the output end of the complementary inverter INV1 via the thin film transistor Q5.
The thin film transistor Q7 is connected between the pixel electrode PE and the input end of the complementary inverter INV1 and the output end of the complementary inverter INV2.

The static memory unit 13 is the connection control unit 1.
It is configured to have a current driving capacity greater than 4. In the connection control unit 14, an N-channel polysilicon thin film transistor Q6 is formed with a channel width W = 3 μm and a channel length L = 3 μm + 3 μm = 6 μm as shown in FIG. 4A, and 3 μm / 6 μm = 0.5.
Has a W / L ratio of The same applies to the N-channel polysilicon thin film transistor Q7. In the column inverter circuit of the static memory unit 14, the P channel polysilicon thin film transistor Q3 has a channel width W.
= 7 μm and channel length L = 3.5 μm, and formed as shown in FIG.
It has a W / L ratio of m = 2. The same applies to the P-channel polysilicon thin film transistor Q1 and the N-channel thin film transistors Q2 and Q4. Further, in the loop switch of the static memory unit 14, the P-channel thin film transistor Q5 has a channel width W = 7.5 μm.
And the channel length L = 3 μm in FIG.
And having a W / L ratio of 7.5 μm / 3 μm = 2.5. Here, the thin film transistor Q
If the W / L ratio of 6 and Q7 is k, the thin film transistor Q
The W / L ratio of 1 to Q4 is 4k, and the thin film transistor Q
The W / L ratio of 5 is 5k. In reality, the W / L ratio of the thin film transistor Q3 is four times or more the W / L ratio of the thin film transistor Q6, and the W / L ratio of the thin film transistor Q5 is five times or more the W / L ratio of the thin film transistor Q6. It is preferable to make it larger than the / L ratio.

Next, the operation of the above flat panel display device will be described. As shown in FIG. 5, in the normal display mode, while the liquid crystal controller 2 maintains the polarity control signals POL1 and POL2 at a low level, the scanning line driving circuit 3 sequentially outputs the scanning signals to the plurality of scanning lines Y every one frame period. (Y1 to Y
m). Each scanning line Y is maintained at a high level for one horizontal scanning period (1H) by the scanning signal. The signal line drive circuit 4 outputs the video signal Vpix for one row whose level is inverted every horizontal scanning period to a plurality of signal lines X (X1 to X).
n). The pixel switch 11 of each display pixel PX is rendered conductive by the scanning signal from the corresponding scanning line Y, and captures the video signal Vpix supplied to the corresponding signal line X to take in the pixel electrode PE.
Apply to. When the pixel switch 11 becomes non-conductive after one horizontal scanning period and the pixel electrode PE is brought into an electrically floating state, the video signal Vpix is held by the liquid crystal capacitor and the auxiliary capacitor 12 until the pixel switch 11 becomes conductive again. . During this period, the display pixel PX is set to the light transmittance corresponding to the potential difference between the common electrode CE and the pixel electrode PE.

When shifting to the still picture display mode, the polarity control signal POL1 is maintained at a high level and the POL2 is maintained at a low level in the still picture writing period which is the first one frame period, and the video signal for a still picture is maintained. Vpix is supplied to the signal line X every horizontal scanning period in this frame period. In the subsequent still image holding period, the polarity control signals POL2 and POL1 are alternately set to a high level every frame period in order to invert the output polarity of the static memory unit 13.

When the polarity control signal POL1 is maintained at the high level in the first frame period corresponding to the still image writing period in the still image display mode as described above, the video signal Vpix corresponding to binary still image information. Is applied to the pixel electrode PE via the pixel switch 11 and is also supplied to the static memory unit 13 via the thin film transistor Q6.
For example, when the polarity control signal POL1 is low level and POL2 is high level during the still image holding period, this video signal Vpix
Is inverted in level by the complementary inverter INV2 and applied as an output video signal to the pixel electrode PE via the thin film transistor Q7. Here, the operation during the still image writing period in the still image display mode will be supplemented. In the last frame period of the normal display mode, the pixel potentials VP1, VP2, VP3 of the display pixels PX from the first row to the fourth row.
VP4 is set to 5V, 0V, 5V, and 0V so as to have the same brightness in the line inversion drive, and the video signal Vpix for still images is, for example, 5V only during the horizontal scanning period when the fourth scanning line Y4 is driven. Set to 0 otherwise
Suppose it is set to V. In this case, the pixel potential VP1
Changes from 5V to 0V in the still image writing period, and the pixel potential VP2 does not change from 0V in the still image writing period. On the other hand, the pixel potential VP3 transits from 5V to 0V,
The pixel potential VP4 transitions from 0V to 5V.

In the flat panel display device of the above-described embodiment, the connection control unit 14 is arranged so that the static memory unit 13 absorbs the current that temporarily flows during the state transition of the connection control unit 14.
It has a larger current drive capability. Therefore, for example, during the state transition of the connection control unit 14 synchronized with the polarity reversal of the display pixel, even if a current temporarily flows from the display pixel PX to the static memory unit 13 due to a potential change due to the polarity reversal, the static memory unit 13 Absorbs this current and suppresses the change of the video signal Vpix in the holding state. As a result, it is possible to prevent the generation of defective pixels, which become dark spots in the still image display mode, and to ensure high quality and reliability.

The present invention is not limited to the above-mentioned embodiments, and can be variously modified without departing from the gist thereof.

FIG. 6 shows a modification of the circuit configuration shown in FIG. In the above-described embodiment, the P-channel polysilicon thin film transistor Q5 is used as the loop switch.
However, the loop switch is changed to a P-channel polysilicon thin film transistor, and for example, the liquid crystal controller 2
The thin film transistor Q5 may be independently controlled by the control signal REV generated from the signal generation unit.

Furthermore, in the above-described embodiment, the case where the flat display device is a liquid crystal display device has been described, but the present invention is also applicable to an organic EL display device and the like.

[0032]

As described above, according to the present invention, there is provided a display pixel circuit and a flat display device capable of preventing generation of a defective pixel which becomes a dark spot in the still image display mode and ensuring high quality and reliability. be able to.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic circuit configuration of a flat panel display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic cross-sectional structure of the flat panel display device shown in FIG.

FIG. 3 is a diagram showing an equivalent circuit around the display pixel shown in FIG.

FIG. 4 is a plan view showing dimensions of the thin film transistors of the connection control unit and the static memory unit shown in FIG.

5 is a diagram showing operation waveforms of the flat panel display device shown in FIG.

FIG. 6 is a diagram showing a modified example of the circuit configuration shown in FIG.

[Explanation of symbols]

X: Signal line Y: scanning line PX ... Liquid crystal display pixel 11 ... Pixel switch 12 ... auxiliary capacity 13 ... Static memory section 14 ... Connection control unit PE ... Pixel electrode AR ... array substrate CT ... Counter substrate CE ... Common electrode LQ ... Liquid crystal layer Q1 to Q7 ... Polysilicon thin film transistor

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G09G 3/20 680 G09G 3/20 680G 3/36 3/36 H01L 29/786 H01L 29/78 618C 614 617N F-term (reference) 2H092 JA09 JA10 JB42 KA04 NA13 2H093 NA31 NC18 NC22 NC29 NC34 NC40 NC41 NC62 ND16 5C006 AA01 AA02 AC27 AC28 AF42 AF44 AF45 AF51 AF53 AF61 AF69 AF71 AF73 BB16 BC03 BC06 BC12 BC20 EB05 A05A17 FA10 FA10 FA10A10 EE28 FF11 JJ02 JJ03 JJ04 5F110 AA07 AA30 BB02 BB04 BB07 EE24 EE28 GG02 GG13 GG23 GG28 GG29 HM15 NN72

Claims (6)

[Claims] 1. A display pixel having a structure in which a light modulation layer is sandwiched between a pair of electrodes, a pixel switch for taking in a video signal, and a static memory section for holding a video signal applied from the pixel switch to the display pixel. A connection control unit that controls electrical connection between the display pixel and the static memory unit, wherein the static memory unit absorbs a current flowing during a state transition of the connection control unit. A display pixel circuit having a larger current driving capability than that of the display pixel circuit. 2. The static memory unit includes a cascade inverter circuit in which first and second complementary inverters are connected in cascade, and a loop switch for feeding back an output of the cascade inverter circuit as an input of the cascade inverter circuit. The display pixel circuit according to claim 1. 3. The connection control unit includes a pair of N-channel polysilicon thin film transistors that alternately apply the output of the first complementary inverter and the output of the second complementary inverter to the display pixel in a predetermined cycle. The cascaded inverter circuit has a channel width W and a channel length L of the N-channel polysilicon thin film transistor of the connection controller.
The L / P ratio is 4 times or more, and the loop switch is 5 times or more the W / L ratio of the N channel polysilicon thin film transistor of the connection controller. Inverter circuit P-channel polysilicon thin film transistor W / L
The display pixel circuit according to claim 2, comprising a P-channel polysilicon thin film transistor having a W / L ratio larger than the ratio. 4. The display pixel circuit according to claim 3, wherein the N-channel polysilicon thin film transistor of the connection controller has a double gate structure. 5. The flat display device according to claim 1, wherein the plurality of display pixel circuits are arranged in a substantially matrix form. 6. A driving circuit configured by combining a plurality of polysilicon thin film transistors so as to output a video signal to the pixel switch section of each display pixel circuit and control the pixel switch section. The flat panel display device according to claim 5.