JP2003084718A - Liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption, to stabilize the display quality and to simplify the circuit structure. SOLUTION: A liquid crystal display element is provided with a liquid crystal display pixel PX in which a liquid crystal material is held between electrodes PE and CE, a dynamic memory circuit DM which includes a switching element Qsig and a capacitive element CM, an electrode drive circuit DV which applies pixel potentials corresponding to display signals held in the circuit DM to the electrode PE and a polarity control circuit PCV which periodically polarity reverses the pixel potentials with respect to the common potential of the electrode CE. The circuit DV includes complementary thin film transistors Q2 and Q4 whose one ends are respectively connected to the electrode PE and are respectively controlled by the potential between the terminals of the element CM. The circuit PC is constituted so that a condition, in which one end of the element CM and the other end of the transistor Q4 are electrically connected to a power supply terminal Gnd, and a condition, in which the other end of the element CM and the other end of the transistor Q2 are electrically connected, are alternatively set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display element in which the drive polarity of display pixels is periodically inverted, and more particularly to a liquid crystal display element including a memory circuit that holds a display signal supplied to the display pixels.

[0002]

2. Description of the Related Art Liquid crystal display devices are thin, small and lightweight, and are used in mobile phones and PDAs (Portable Digital Assistants).
It is widely used as an image monitor for portable terminal devices such as e). Since such portable terminal devices generally operate using a rechargeable battery as a power source, the consumption rate of the battery greatly affects the usable time. For these reasons, low power consumption of liquid crystal display devices has been actively studied.

Recently, static memory technology has been used to reduce the power consumption of liquid crystal devices. In this application, for example, when displaying a still image that does not require updating of the display signal, the low power consumption mode is set, and the static memory circuit holds the display signal supplied from the external drive circuit and applies it to the display pixel. To do. As a result, image display can be continued even if the output operation of the external drive circuit is stopped.

In a conventional liquid crystal display device using this static memory technology, a plurality of display pixels PX whose display screen is constituted by a static memory circuit MR as shown in FIG.
Is provided for each of the. The display pixel PX includes a pair of pixel electrodes PE and a counter electrode CE and a liquid crystal material sandwiched therebetween, and the display signal has a polarity opposite to the common potential Vcom set in the counter electrode CE, for example, 1
The polarity is inverted for each frame and supplied to the signal line X. The pixel electrode PE is connected to the pixel switch Qsig which selectively outputs the display signal on the signal line X. Counter electrode CE
Is an auxiliary capacitance line Cs that is capacitively coupled to the pixel electrode PE, for example.
And the potential Vcs of the auxiliary capacitance line Cs is set to a value equal to the common potential Vcom. The pixel electrode PE and the counter electrode CE form a liquid crystal capacitor LC via a liquid crystal material,
The pixel electrode PE and the auxiliary capacitance line Cs form an auxiliary capacitance Csig parallel to the liquid crystal capacitance without interposing the liquid crystal material. The pixel switch Qsig is composed of, for example, a thin film transistor, and applies a display signal on the signal line X to the display pixel PX when driven by a scanning signal from the scanning line Y. At this time, the display pixel PX is set to the light transmittance corresponding to the potential difference between the counter electrode CE and the pixel electrode PE. Auxiliary capacity Csi
g has a capacitance value sufficiently larger than the liquid crystal capacitance LC and is charged and discharged by the display signal applied to the display pixel PX.
When the auxiliary capacitance Csig holds the display signal by this charging / discharging, this display signal is applied from the auxiliary capacitance Csig to the pixel electrode PE when the pixel switch Qsig becomes non-conductive. As a result, the potential difference between the pixel electrode and the counter electrode is maintained.

Further, the display pixel PX has a polarity control circuit PC.
To the static memory circuit MR. The static memory circuit MR holds the display signal applied to the display pixel PX from the signal line X via the pixel switch Qsig in association with the rising of the scanning signal from the scanning line Y, and itself in accordance with the falling of this scanning signal. The display signal held in step 3 is applied to the display pixel PX. Here, the polarity control circuit P
C controls so that the display signal applied from the static memory circuit MR to the display pixel PX is level-inverted every frame and has a polarity opposite to the common potential Vcom. Therefore, even if the output operation of the external drive circuit is stopped, the potential difference between the pixel electrode and the counter electrode is reversed in polarity every frame, so that the burn-in phenomenon due to uneven distribution of the liquid crystal material can be prevented.

[0006]

In the above-mentioned liquid crystal display device, when the polarity of the display signal applied from the static memory circuit MR to the display pixel PX is inverted in the low power consumption mode, the liquid crystal capacitance LC and the auxiliary device are used. Capacity Csig
Charge and discharge current of the pair of power supply terminals Vdd, Gnd
Flow from one side to the other, which causes the power supply terminal Vd
The voltage between d and Gnd is changed. This power supply fluctuation makes the operation of the static memory circuit MR unstable. Further, when the power supply fluctuation is large, the contents held in the static memory circuit MR are changed and the display image is disturbed. In addition, this liquid crystal display device has at least seven active elements, that is, thin film transistors Q1 ′ to
I need Q7 '. Furthermore, the polarity control signal POL-
Since the A and POL-B wiring areas are also required, efficient reduction of power consumption and high definition of the display screen are restricted.

It is an object of the present invention to provide a liquid crystal display device which solves the above problems and stabilizes the display quality with low power consumption while simplifying the circuit structure.

[0008]

According to the present invention, a liquid crystal display pixel for controlling a liquid crystal material by a potential difference between a pixel electrode and a counter electrode, a switch element for sampling a display signal supplied from the outside, and this switch element. A memory circuit including a capacitive element that holds a display signal sampled in step S1, an electrode drive circuit that applies a pixel potential corresponding to the display signal held in the memory circuit to the pixel electrode, and a counter electrode that is applied to the counter electrode. A polarity control circuit for periodically reversing the polarity of the pixel potential with respect to a common potential, and the electrode drive circuit is connected to the pixel electrode at one end and is controlled by the potentials at one end and the other end of the capacitive element, respectively. The polarity control circuit includes complementary first and second active elements, wherein one end of the capacitive element and the other end of the second active element have a first electric current. A state in which it is electrically connected to a terminal and a state in which the other end of the capacitive element and the other end of the first active element are electrically connected to a second power supply terminal set to a potential higher than that of the first power supply terminal. A liquid crystal display device is provided that is configured to be set alternately.

In this liquid crystal display element, the potential of the first power supply terminal and the potential of the second power supply terminal are alternately and cyclically applied to the display pixel PE in accordance with the polarity reversal of the pixel potential, and the liquid crystal capacitance LC is supplied with the potential. The applied polarity is reversed. Since this operation can be set independently of the sampling cycle of the display signal,
When the display signal does not change, the operation of peripheral circuits can be stopped to achieve low power consumption, and the cycle of this operation should be set longer than the typical 1/60 second sampling cycle of the display signal. As a result, it is possible to further reduce power consumption. Further, this liquid crystal display element does not cause the power supply fluctuation that occurs in the static memory circuit, and does not require many circuit components and control signals as in the case where the static memory circuit is provided. That is, the display quality can be stabilized while the circuit structure can be simplified.

[0010]

DETAILED DESCRIPTION OF THE INVENTION A liquid crystal display device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. The liquid crystal display device is used as an image monitor of a mobile terminal device having a low power consumption mode capable of displaying a still image in addition to a normal mode capable of displaying a moving image.

FIG. 1 shows a schematic structure of this liquid crystal display device, and FIG. 2 shows a pixel peripheral circuit of this liquid crystal display device.
The liquid crystal display device includes a liquid crystal display panel 1 and a liquid crystal controller 2 that controls the liquid crystal display panel 1. The liquid crystal display panel 1 has a structure in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and the liquid crystal controller 2 is arranged on an external drive circuit substrate independent of the liquid crystal display panel 1. The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix, a plurality of scanning lines Y (Y1 to Ym) formed along rows of the plurality of pixel electrodes PE, and a column of the plurality of pixel electrodes PE. Signal lines X formed by
(X1 to Xn), the signal lines X1 to Xn, and the scanning lines Y1 to Ym, respectively. The pixel display signals Vpix from the corresponding signal lines X are sampled in response to the scanning signals from the corresponding scanning lines Y, respectively. N-channel low temperature polysilicon thin film transistor (TF)
T) Qsig, scanning line driving circuit 3 for driving scanning lines Y1 to Ym, and signal line driving circuit 4 for driving signal lines X1 to Xn
including. The counter substrate CT includes a single counter electrode CE which is arranged to face the plurality of pixel electrodes PE and is set to the common potential Vcom. Scan line drive circuit 3 and signal line drive circuit 4
Is composed of a plurality of low-temperature polysilicon thin film transistors formed on the array substrate AR similarly to the thin film transistor Qsig. The counter electrode CE is set to the common potential Vcom supplied from the outside.

The liquid crystal controller 2 receives a digital video signal and a synchronizing signal supplied from the outside, and generates a pixel display signal Vpix, a vertical scanning control signal YCT, a horizontal scanning control signal XCT, and a polarity inversion signal POL as in the conventional case. . The vertical scanning control signal YCT includes, for example, a vertical start pulse and a vertical clock signal, and is supplied to the scanning line driving circuit 3. The horizontal scanning control signal XCT includes a horizontal start pulse, a horizontal clock signal, etc., and a display signal Vpix.
It is also supplied to the signal line drive circuit 4. Polarity inversion signal P
OL is a plurality of pixel electrodes P arranged on the array substrate AR.
Generated for E, for example, the polarity is inverted in one frame period in the normal mode, and the level is inverted in a predetermined period longer than that in the normal mode, for example, every four frame periods to achieve lower power consumption in the low power consumption mode. To be done. The common potential Vcom is 0V in synchronization with this polarity inversion signal POL.
And 5V level-inverted from one to the other. As a result, the common potential Vcom has an amplitude of 0V to 5V, while the pixel display signal Vpix has an amplitude of 0V to 3V.

The scanning line driving circuit 3 includes a shift register circuit, and is controlled by the vertical scanning control signal YCT so as to sequentially supply a scanning signal for conducting the thin film transistor Qsig to the scanning lines Y1 to Ym every one vertical scanning (frame) period. It The shift register circuit shifts a vertical start pulse supplied every one vertical scanning period in synchronization with a vertical clock signal to thereby shift one of the plurality of scanning lines Y1 to Ym.
A book is selected and a scanning signal is output to the selected scanning line.

The signal line driving circuit 4 has a shift register circuit, and the display signal Vpix is supplied to the signal lines X1 to X in one horizontal scanning period (1H) in which each scanning line Y is driven by the scanning signal.
It is controlled by the horizontal scanning control signal XCT so as to be supplied to each n. The shift register circuit shifts the horizontal start pulse supplied for each horizontal scanning period in synchronization with the horizontal clock signal to thereby output a plurality of signal lines X1.
To Xn and select the display signal V for the selection signal line.
supply pix.

In this liquid crystal display device, the liquid crystal layer LQ has a pixel potential of 5V depending on the display signal Vpix with respect to the common potential Vcom of 0V set on the counter electrode CE.
It is a normally white color that displays black by being applied to E, and is driven in an inversion drive system in which the voltage polarity between the pixel electrode PE and the counter electrode CE is periodically inverted. The display screen DS has a pair of pixel electrodes PE and counter electrodes C, respectively.
E, and a plurality of display pixels PX including the liquid crystal material of the liquid crystal layer LQ sandwiched between these electrodes PE and CE, and the dynamic memory circuit DM includes these display pixels PX.
Is provided for each of the.

As shown in FIG. 2, the dynamic memory circuit DM includes a thin film transistor Qsig for sampling the display signal Vpix on the signal line X as a pixel switch and a capacitive element CM for holding the display signal Vsig sampled by the thin film transistor Qsig. Composed. The capacitance element CM is 1/10 of the liquid crystal capacitance LC between the pixel electrode PE and the counter electrode CE which sandwich the liquid crystal material.
It is set below. Each display pixel PX has P-channel low temperature polysilicon thin film transistors Q1 to Q3 and N channel low temperature polysilicon thin film transistors Q4 to Q6 in addition to the dynamic memory circuit DM.

The thin film transistors Q1 and Q2 are connected in series between the power supply terminal Vdd set to the potential of 5V and the pixel electrode PE, and the thin film transistors Q4 and Q5 are connected between the power supply terminal Gnd and the pixel electrode PE set to the potential of 0V. Connected in series. The thin film transistors Q2 and Q4 are controlled by the negative terminal potential of the capacitive element CM and the positive terminal potential of the capacitive element CM, respectively. The thin film transistor Q3 has a power supply terminal Vdd.
And the thin film transistor Q6 is connected between the power supply terminal Gnd and the negative end of the capacitive element CM. Thin film transistors Q1 and Q
The gates of 3, Q5, and Q6 are connected to receive the polarity inversion signal POL. The thin film transistor Qsig is connected between the signal line X and the positive end of the capacitive element CM,
It is controlled by the potential of the scanning line Y. Thin film transistor Q
2 and Q4 form an electrode drive circuit DV for applying a pixel potential corresponding to the display signal Vpix held in the dynamic memory circuit DM to the pixel electrode, and the thin film transistor Q
1, Q3, Q5, and Q6 form a polarity control circuit PC that periodically inverts the polarity of the pixel potential with respect to the common potential Vcom applied to the counter electrode CE.

When the thin film transistor Qsig becomes conductive when driven by the scanning signal from the scanning line Y, the display signal Vpix on the signal line X is applied to the plus end of the capacitive element CM to charge and discharge the capacitive element CM. 1 scan signal supply
When stopped after the horizontal scanning period, the thin film transistor Qsig
Becomes non-conducting, and the capacitive element CM holds the amount of charge obtained as a result of charging and discharging as the display signal Vpix. The electrode drive circuit DV applies a pixel potential corresponding to the display signal Vpix held in the capacitive element CM to the pixel electrode PE. At this time, the display pixel PX is set to the light transmittance corresponding to the potential difference between the counter electrode CE and the pixel electrode PE. Polarity control circuit P
C inverts the polarity of the pixel potential so as to have the opposite polarity to the common potential Vcom of the counter electrode CE in synchronization with the polarity inversion signal POL.

That is, the pixel electrode PE and the counter electrode C
By reversing the polarity while maintaining the voltage difference between E, the burn-in phenomenon due to uneven distribution of the liquid crystal material is prevented.

When displaying a still image which does not require updating of the display signal Vpix, the liquid crystal controller 2 shifts from the normal mode to the low power consumption mode and controls the scanning line driving circuit 3 to stop the output of the scanning signal. At the same time, the signal line drive circuit 4 is controlled to stop the output of the display signal Vpix. The polarity inversion signal POL is continuously output from the liquid crystal controller 2 even in the low power consumption mode in order to prevent the burn-in phenomenon due to uneven distribution of the liquid crystal material.

Now, the operations of the dynamic memory circuit DM, the electrode drive circuit DV, and the polarity control circuit PC will be described in more detail. Here, the display signal Vp in which the capacitive element CM is sampled by the thin film transistor Qsig is used.
It is assumed that an amount of electric charge corresponding to ix is already held.

FIG. 3 shows a state in which the pixel peripheral circuit shown in FIG. 2 is set at the rising edge of the polarity inversion signal POL. When the polarity inversion signal POL becomes high level, the thin film transistors Q5 and Q6 of the polarity control circuit PC become conductive and the thin film transistors Q1 and Q3 of the polarity control circuit PC become non-conductive. Thin film transistor Q2 of electrode drive circuit DV
Is conductive by the potential of the power supply terminal Gnd set at the negative end of the capacitive element CM via the electrode thin film transistor Q6, but since the thin film transistor Q1 is non-conductive,
The pixel electrode PE is maintained in a state of being electrically separated from the power supply terminal Vdd. During this period, the thin film transistor Q4 of the electrode drive circuit DV is controlled by the positive end potential of the capacitive element CM charged and discharged by the display signal Vsig.

The pixel peripheral circuit becomes the equivalent circuit shown in FIG. 4 in such a state. The thin film transistor Q4 becomes conductive when the display signal Vsig is equal to or higher than the threshold voltage (= about 1.5 V) of the thin film transistor Q4. Accordingly, the voltage between the power supply terminal Gnd and the counter electrode CE is changed to the display pixel P.
Applied to X. Further, the thin film transistor Q4 becomes non-conductive when the display signal Vsig is less than the threshold voltage of the thin film transistor Q4. In this case, the voltage between the power supply terminal Gnd and the counter electrode CE is almost equal to the thin film transistor Q4.
Is not applied to the display pixel PX.

FIG. 5 shows a state in which the pixel peripheral circuit shown in FIG. 2 is set according to the fall of the polarity inversion signal POL. When the polarity inversion signal POL becomes low level, the polarity control circuit P
The thin film transistors Q1 and Q3 of C become conductive, and the thin film transistors Q5 and Q6 of the polarity control circuit PC become non-conductive. The thin film transistor Q4 of the electrode drive circuit DV is conductive by the potential of the power supply terminal Vdd set at the positive end of the capacitive element CM via the electrode thin film transistor Q3, but the thin film transistor Q5 is non-conductive, so that the pixel electrode PE is connected to the power supply terminal Gnd. It remains electrically isolated from the. During this period, the thin film transistor Q2 of the electrode drive circuit DV is controlled by the negative end potential of the capacitive element CM charged and discharged by the display signal Vsig.

The pixel peripheral circuit becomes the equivalent circuit shown in FIG. 6 in such a state. In the thin film transistor Q2, the display signal Vsig indicates that the threshold voltage (= −−) of the thin film transistor Q2.
1.5V), the voltage applied to the gate of the thin film transistor Q2 is Vdd−.
It conducts when the voltage is 1.5 V or less. As a result, the voltage between the power supply terminal Vdd and the counter electrode CE is changed to the display pixel PX.
Applied to. Further, the thin film transistor Q2 becomes non-conductive when the absolute value of the display signal Vsig is less than the absolute value of the threshold voltage of the thin film transistor Q2. In this case, the voltage between the power supply terminal Vdd and the counter electrode CE is almost applied to the thin film transistor Q2 and is not applied to the display pixel PX.

If the capacitive element CM holds the amount of electric charge capable of conducting each of the thin film transistors Q2 and Q4, the voltage + (Vdd-Vcom) with reference to the common potential Vcom.
And- (Vcom-gnd) are alternately applied to the display pixel PX with the inversion of the polarity inversion signal POL.

In the liquid crystal display device according to the above-described embodiment, the potential of the power supply terminal Gnd and the potential of the power supply terminal Vdd are alternately applied to one end and the other end of the capacitive element CM according to the inversion of the polarity inversion signal POL, and the display signal is displayed. Since it can be set to a cycle independent of the sampling cycle of Vpix, the display signal Vpix
In such a case, the period of polarity inversion operation by the polarity inversion signal POL can be lengthened to reduce power consumption. Further, this liquid crystal display device not only causes the power supply fluctuation that occurs in the static memory circuit MR shown in FIG.
7 thin film transistors Q required when providing
1'-Q7 'and two control signals POL-A, POL
-B can be replaced with six thin film transistors Q1 to Q6 and one control signal POL. That is,
While stabilizing the display quality, the circuit structure can be simplified.
Further, the signal to be written to the capacitive element CM need only be a voltage at which the thin film transistors of Q1 to Q6 are conductive, and a large amplitude is not required. Therefore, the power supply voltage of the signal line drive circuit 4 which is the supply source of this display signal Vpix It can also be reduced.

Incidentally, the pixel electrode PE shown in FIG. 7 is directly driven by the auxiliary capacitance Csig, but the pixel electrode PE of this embodiment is driven by the drive circuit DV. The capacitive element CM is the thin film transistor Q2, Q of this drive circuit DV.
However, the pixel electrode PE is not directly driven. Since the gate resistance values of these thin film transistors Q2 and Q4 are 10 to 100 times the specific resistance of the display pixel PX,
The retention period of the charge accumulated in the capacitive element CM also increases in proportion to this. That is, in the rewriting cycle of the dynamic memory circuit DM, the value of the capacitive element CM is set to the conventional auxiliary capacitance Csig.
By setting it to be approximately, the sampling period of the display signal Vpix can be set to 1/6 seconds or more, which is longer than the general 1/60 seconds.

[0029]

As described above, according to the present invention, it is possible to provide a liquid crystal display element which can reduce the power consumption and stabilize the display quality while simplifying the circuit structure.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic structure of a liquid crystal display device according to an embodiment of the present invention.

2 is a circuit diagram showing a pixel peripheral circuit of the liquid crystal display device shown in FIG.

FIG. 3 is a diagram showing a state in which the pixel peripheral circuit shown in FIG. 2 is set with rising of a polarity inversion signal.

FIG. 4 is a diagram showing an equivalent circuit of a pixel peripheral circuit set in the state shown in FIG.

5 is a diagram showing a state in which the pixel peripheral circuit shown in FIG. 2 is set in association with a fall of a polarity inversion signal.

FIG. 6 is a diagram showing an equivalent circuit of a pixel peripheral circuit set in the state shown in FIG.

FIG. 7 is a circuit diagram showing a pixel peripheral circuit of a conventional liquid crystal display device using a static memory technique.

[Explanation of symbols]

PX ... Liquid crystal display pixel Qsig ... Thin film transistor for pixel switch CM: Capacitive element DM: Dynamic memory circuit PC ... Polarity control circuit DV ... Electrode drive circuit PE ... Pixel electrode CE ... Counter electrode Vdd, Gnd ... Power supply terminal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 611 G09G 3/20 611A 621 621B 624 624B 631 631H F term (reference) 2H092 JB42 JB44 KA04 NA26 2H093 NA31 NB07 NC40 ND39 5C006 AC28 AF44 AF45 AF51 AF69 BB16 BC03 BC06 BC12 BC20 BF11 EB05 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ03 5C094 AA22 AA45 BA03 BA43 CA19 DB04

Claims (5)

[Claims] 1. A liquid crystal display pixel for controlling a liquid crystal material by a potential difference between a pixel electrode and a counter electrode, a switch element for sampling a display signal supplied from the outside, and a capacitor for holding a display signal sampled by the switch element. A memory circuit including an element, an electrode drive circuit for applying a pixel potential corresponding to a display signal held in the memory circuit to the pixel electrode, and a cycle of the pixel potential with respect to a common potential applied to the counter electrode. A polarity control circuit for selectively reversing the polarity, wherein the electrode driving circuit is connected to the pixel electrode at one end and is controlled by potentials at one end and the other end of the capacitive element, respectively, complementary first and second active elements The polarity control circuit includes a state in which one end of the capacitive element and the other end of the second active element are electrically connected to the first power supply terminal. And a state in which the other end of the capacitive element and the other end of the first active element are electrically connected to a second power supply terminal that is set to a potential higher than that of the first power supply terminal. A liquid crystal display element characterized by the following. 2. The liquid crystal display element according to claim 1, wherein the first and second active elements are respectively composed of P-channel and N-channel thin film transistors connected to the pixel electrode at one end. 3. The display signal has an amplitude larger than a threshold voltage of thin film transistors of the first and second active elements and smaller than a power supply voltage between the first and second power supply terminals. 2. The liquid crystal display element according to item 2. 4. The polarity control circuit includes an N-channel thin film transistor connected between the first power supply terminal and one end of the capacitive element, and between the first power supply terminal and the other end of the N-channel thin film transistor of the second active element. An N-channel thin film transistor connected, a P-channel thin film transistor connected between the second power supply terminal and the other end of the capacitive element, and a second power supply terminal connected between the other end of the P-channel thin film transistor of the first active element The liquid crystal display element according to claim 3, comprising a P-channel thin film transistor that is formed. 5. The switch element is composed of a polysilicon thin film transistor, and the thin film transistors of the drive circuit and the polarity control circuit are polysilicon thin film transistors formed together with the switch element. Liquid crystal display element.