CN111681549A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN111681549A CN111681549A CN202010548934.4A CN202010548934A CN111681549A CN 111681549 A CN111681549 A CN 111681549A CN 202010548934 A CN202010548934 A CN 202010548934A CN 111681549 A CN111681549 A CN 111681549A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/179—Interconnections, e.g. wiring lines or terminals
Abstract
The invention discloses an array substrate and a display panel. The array substrate comprises a substrate and a driving circuit layer positioned on the substrate, wherein pixel driving circuits are arranged in the driving circuit layer, and each pixel driving circuit comprises a threshold compensation transistor; the threshold compensation transistor comprises a first channel region, a second channel region and a middle active region, wherein the middle active region is arranged between the first channel region and the second channel region; a first voltage line and a data signal line are arranged in the driving circuit layer; the first voltage lines at least partially overlap with a vertical projection of the intermediate active region on the substrate, and the data signal lines do not overlap with the vertical projection of the first voltage lines on the substrate. The grid potential change of the driving transistor can be reduced, and the display uniformity of a display panel formed by the array substrate is improved. Meanwhile, delay generated during data signal writing on the data signal line can be reduced, and further the time requirement for data writing is favorably reduced, so that the display panel is favorably realized with high refreshing frequency.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
The display panel can drive the light-emitting device to emit light through the pixel driving circuit to realize display. In the working process of the pixel driving circuit, the parasitic capacitance formed by the power supply signal line and the intermediate node of the threshold compensation transistor can be increased to ensure that the grid potential of the driving transistor is kept unchanged after the charging is finished, so that the display uniformity of the display panel is improved. However, the parasitic capacitance on the data signal line is easily increased in the above process, and further, the time required for writing the data voltage in the data writing stage is increased, which is not favorable for realizing the high refresh frequency of the display panel.
Disclosure of Invention
The invention provides an array substrate and a display panel, which are used for reducing parasitic capacitance on a data signal line and are beneficial to realizing high refreshing frequency of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, which is characterized by including a substrate and a driving line layer located on the substrate, where a pixel driving circuit is disposed in the driving line layer, and each pixel driving circuit includes a threshold compensation transistor; the threshold compensation transistor includes a first channel region, a second channel region, and an intermediate active region disposed between the first channel region and the second channel region;
a first voltage line and a data signal line are arranged in the driving circuit layer; the first voltage line at least partially overlaps a vertical projection of the intermediate active region on the substrate, and the data signal line does not overlap the vertical projection of the first voltage line on the substrate.
Optionally, each of the pixel driving circuits further comprises a storage capacitor; the first electrode plate of the storage capacitor and the first voltage line are arranged on the same layer.
Optionally, the first voltage line and the source and drain of the threshold compensation transistor are disposed in the same layer.
Optionally, each of the pixel driving circuits further includes a reference voltage signal line; the first voltage line is electrically connected to the reference voltage line.
Optionally, each of the pixel driving circuits further comprises a driving transistor; a first pole of the threshold compensation transistor is electrically connected with the grid electrode of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected with the second pole of the driving transistor;
the reference voltage signal line is arranged on one side of the threshold compensation transistor, which is far away from the driving transistor, and the data signal line is arranged on one side of the driving transistor, which is far away from the threshold compensation transistor.
Optionally, the reference voltage line is disposed on a side of the source drain layer of the threshold compensation transistor away from the substrate; the reference voltage line extends along a direction in which the data signal line extends.
Optionally, each of the pixel driving circuits further includes a first scan signal line and a first initialization transistor;
the gate of the first initialization transistor is electrically connected to the first scan signal line, the first pole of the first initialization transistor is electrically connected to the reference voltage line, and the second pole of the first initialization transistor is electrically connected to the gate of the driving transistor.
Optionally, each of the pixel driving circuits further includes a second scanning signal line and a data writing transistor;
the gate of the data writing transistor is electrically connected to the second scanning signal line, the first pole of the data writing transistor is electrically connected to the data signal line, and the second pole of the data writing transistor is electrically connected to the first pole of the driving transistor.
Optionally, each of the pixel driving circuits further includes a third scanning signal line, a light emitting device, and a second initialization transistor;
the gate of the second initialization transistor is electrically connected to the third scanning signal line, the first electrode of the second initialization transistor is electrically connected to the reference voltage line, and the second electrode of the second initialization transistor is electrically connected to the anode of the light emitting device.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in any embodiment of the present invention.
According to the technical scheme of the embodiment of the invention, the first voltage wire is arranged on the array substrate, the first voltage wire and the vertical projection of the middle node of the threshold compensation transistor on the substrate are at least partially overlapped to form a parasitic capacitor, and the potential of the first voltage provided by the first voltage wire is fixed, so that the potential of the middle node of the threshold compensation transistor can be maintained to be stable when a scanning signal jumps, the risk of electric leakage of the threshold compensation transistor is reduced, the grid potential change of the driving transistor caused by the grid potential jump of the threshold compensation transistor can be avoided when the data writing stage of the pixel driving circuit is finished, the driving current of the pixel driving circuit is ensured to correspond to the data voltage, and the display uniformity of the array substrate after a display panel is formed is ensured. Meanwhile, the first voltage line does not overlap with a vertical projection of the data signal line on the substrate, so that parasitic capacitance on the data signal line can be reduced. When the pixel driving circuit works in a data writing stage, the delay generated when the data signal on the data signal line is written can be reduced, and the time requirement of data writing is further favorably reduced, so that the high refreshing frequency of the display panel is favorably realized.
Drawings
Fig. 1 is a schematic structural diagram of a conventional pixel driving circuit;
FIG. 2 is a timing diagram of the corresponding pixel driving circuit of FIG. 1;
fig. 3 is a schematic structural diagram of a conventional array substrate;
fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a conventional pixel driving circuit. As shown in fig. 1, the pixel driving circuit includes a driving transistor Mdr, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a storage capacitor C1, and a light emitting device D1. The driving transistor Mdr, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are exemplarily shown to be P-type transistors. The specific connection relationship is shown in fig. 1. Fig. 2 is a timing diagram of the pixel driving circuit shown in fig. 1. Wherein, Scan1 is the timing of the first Scan signal provided by the first Scan signal input terminal Scan1, Scan2 is the timing of the second Scan signal provided by the second Scan signal input terminal Scan2, Scan3 is the timing of the third Scan signal provided by the third Scan signal input terminal Scan3, and EN is the timing of the emission control signal provided by the emission control signal input terminal EN. The specific working process of the pixel driving circuit is as follows:
in the first phase t11, the first Scan signal provided by the first Scan signal input terminal Scan1 is at a low level, the second Scan signal provided by the second Scan signal input terminal Scan2 is at a high level, the third Scan signal provided by the third Scan signal input terminal Scan3 is at a high level, and the emission control signal provided by the emission control signal input terminal EN is at a high level. At this time, the fifth transistor M5 outputs the reference voltage signal provided from the reference voltage signal input terminal Vref1 to the gate of the drive transistor Mdr, and initializes the gate of the drive transistor Mdr, so that the drive transistor Mdr is in a conductive state.
In the second phase t12, the first Scan signal provided by the first Scan signal input terminal Scan1 is at a high level, the second Scan signal provided by the second Scan signal input terminal Scan2 is at a low level, the third Scan signal provided by the third Scan signal input terminal Scan3 is at a high level, and the emission control signal provided by the emission control signal input terminal EN is at a high level. At this time, the first transistor M1 and the second transistor M2 are turned on, the data voltage provided by the data signal input terminal Vdata is written to the gate of the driving transistor Mdr through the first transistor M1, the driving transistor Mdr and the second transistor M2 until the potential of the gate of the driving transistor Mdr is the sum of the data voltage and the threshold voltage of the driving transistor Mdr, and the driving transistor Mdr is turned off, so that the writing of the data voltage and the threshold compensation of the driving transistor Mdr are realized.
In the third stage t13, the first Scan signal provided by the first Scan signal input terminal Scan1 is at a high level, the second Scan signal provided by the second Scan signal input terminal Scan2 is at a high level, the third Scan signal provided by the third Scan signal input terminal Scan3 is at a low level, and the emission control signal provided by the emission control signal input terminal EN is at a high level. At this time, the sixth transistor M6 outputs the reference voltage signal provided from the reference voltage signal input terminal Vref1 to the anode of the light emitting device D1, and initializes the anode of the light emitting device D1.
In the fourth phase t14, the first Scan signal provided at the first Scan signal input terminal Scan1 is at a high level, the second Scan signal provided at the second Scan signal input terminal Scan2 is at a high level, the third Scan signal provided at the third Scan signal input terminal Scan3 is at a high level, and the emission control signal provided at the emission control signal input terminal EN is at a low level. At this time, the third transistor M3 and the fourth transistor M4 are turned on, and the third transistor M3 outputs the first power supplied from the first power input terminal Vdd to the source of the driving transistor Mdr, so that the gate-source voltage difference of the driving transistor Mdr is increased, and the voltage difference between the source and the gate of the driving transistor Mdr is greater than the threshold voltage of the driving transistor Mdr, and thus the driving transistor Mdr is turned on. The cathode of the light emitting device D1 is electrically connected to the second power input terminal Vss, and at this time, the driving transistor Mdr supplies a driving current to the light emitting device D1 to drive the light emitting device D1 to emit light.
In the process of the above operation, in the second stage t12, the data voltage is written into the gate of the driving transistor Mdr through the second transistor M2. Because parasitic capacitance exists between the gate and the drain of the second transistor M2, when the second stage t12 is finished, the second Scan signal provided by the second Scan signal input terminal Scan2 changes from low level to high level, that is, the gate potential of the second transistor M2 changes from low level to high level, the drain potential of the second transistor M2 also changes due to the coupling effect of the parasitic capacitance, so that the second transistor M2 has a leakage phenomenon, and further the gate potential of the driving transistor Mdr changes, and therefore, in the fourth stage t14, a certain error exists between the driving current formed by the driving transistor Mdr according to the gate potential and the gray scale corresponding to the data voltage, and the display of the display panel is not uniform. Fig. 3 is a schematic structural diagram of a conventional array substrate. As shown in fig. 1 and 3, the array substrate includes a driving transistor Mdr, a first transistor M1, a second transistor M2, a power signal line vdd, a data signal line vdata, a first scan signal line scan1, a second scan signal line scan2, and a third scan signal line scan 3. The second transistor M2 is a double-gate transistor, including an intermediate node a. The power supply signal line vdd supplies a power supply signal to the pixel driving circuit. Since the power supply signal line vdd supplies a power supply signal of a fixed potential, the power supply signal line vdd may be electrically connected to the metal trace 101, and the metal trace 101 overlaps with the intermediate node a of the second transistor M2, thereby forming a parasitic capacitance. When the second scan signal provided by the second scan signal line scan2 jumps and the gate potential of the second transistor M2 changes from low to high, the parasitic capacitance formed by the metal trace 101 and the intermediate node a can maintain the drain potential of the second transistor M2 unchanged, so that the potential of the gate of the driving transistor Mdr can be maintained unchanged, and the display uniformity of the display panel is improved. With continued reference to fig. 3, when the metal trace 101 extends from the power signal line vdd to the intermediate node a of the second transistor M2, it passes through the data signal line vdata, so that a parasitic capacitance is formed between the metal trace 101 and the data signal line vdata, thereby increasing the parasitic capacitance on the data signal line vdata. Illustratively, the parasitic capacitance formed between the metal trace 101 and the data signal line vdata accounts for 30% of the total capacitance on the data signal line vdata. When the pixel driving circuit writes data voltage in through the data signal line vdata, the parasitic capacitance on the data signal line vdata is large, so that the data voltage writing process has large delay, long time is required for realizing data writing, and the high refreshing frequency of the display panel is not facilitated.
In view of the above technical problems, an embodiment of the present invention provides an array substrate. Fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 4, the array substrate includes a substrate 110 and a driving line layer on the substrate 110, the driving line layer is provided with pixel driving circuits 120 therein, and each pixel driving circuit 120 includes a threshold compensation transistor T1; the threshold compensation transistor T1 includes a first channel region 121, a second channel region 122, and an intermediate active region 123, the intermediate active region 123 being disposed between the first channel region 121 and the second channel region 122; the driving circuit layer is provided with a first voltage line V1 and a data signal line VDATA; the first voltage line V1 at least partially overlaps the vertical projection of the intermediate active region on the substrate 110, and the data signal line VDATA does not overlap the vertical projection of the first voltage line V1 on the substrate 110.
Specifically, as shown in fig. 4, the array substrate includes an active layer 130 and a first metal layer 140, the active layer 130 is patterned to form an active region of the threshold compensation transistor T1, the active region includes a first channel region 121, a second channel region 122, and an intermediate active region 123. The first metal layer is patterned to form the gate of the threshold compensation transistor T1. The threshold compensation transistor T1 is a double gate transistor for compensating the threshold voltage of the driving transistor of the pixel driving circuit 120 during the data writing phase of the pixel driving circuit 120. The first metal layer forms a first gate and a second gate of the threshold compensation transistor T1. The first channel region 121 is disposed corresponding to the first gate of the threshold compensation transistor T1, and the second channel region 122 is disposed corresponding to the second gate of the threshold compensation transistor T1. The intermediate active region 123 is disposed between the first channel region 121 and the second channel region 122, forming an intermediate node B of the threshold compensation transistor T1. The first voltage line V1 is capable of providing a first voltage signal and at least partially overlaps a vertical projection of the intermediate active region 123 onto the substrate 110 such that the first voltage line V1 forms a parasitic capacitance with the intermediate active region 123, the first voltage line V1 acting as a first plate of the parasitic capacitance and the intermediate active region 123 acting as a second plate of the parasitic capacitance. In addition, parasitic capacitance exists between the gate and the source and drain of the threshold compensation transistor T1. In the operation of the pixel driving circuit 120, when the gate potential of the threshold compensation transistor T1 jumps, the first voltage supplied by the first voltage line V1 makes the parasitic capacitance formed by the middle active region 123 and the first voltage line V1 fix the potential of the middle node B of the threshold compensation transistor T1, so as to prevent the threshold compensation transistor T1 from generating leakage. When the data writing stage of the pixel driving circuit 120 is finished, the gate potential change of the driving transistor caused by the gate potential jump of the threshold compensation transistor T1 can be avoided, so that the driving current of the pixel driving circuit 120 is ensured to correspond to the data voltage, and the display uniformity of the array substrate after the display panel is formed is ensured. Moreover, the first voltage lines V1 do not overlap with the vertical projection of the data signal line VDATA on the substrate 110, i.e., the first voltage lines V1 do not form parasitic capacitance with the data signal line VDATA, so that the parasitic capacitance on the data signal line VDATA can be reduced. When the pixel driving circuit 120 operates in the data writing stage, the delay generated when the data signal on the data signal line VDATA is written can be reduced, which is favorable for reducing the time requirement for data writing, and thus is favorable for the display panel to realize a high refresh frequency.
With continued reference to fig. 4, each pixel drive circuit 120 also includes a storage capacitor; the first electrode plate 151 of the storage capacitor is disposed in the same layer as the first voltage line V1.
Specifically, the array substrate further includes a second metal layer 150, the second metal layer 150 may form a first electrode plate 151 of a storage capacitor by patterning, and the second electrode plate of the storage capacitor may multiplex the gate electrode 141 of the driving transistor formed by the first metal layer 140. In the pixel driving circuit 120, the storage capacitor is used to store the data voltage written to the gate 141 of the driving transistor in the data writing phase. In addition, the array substrate further includes an interlayer insulating layer disposed between the first metal layer 140 and the second metal layer 150 for preventing the first metal layer 140 and the second metal layer 150 from being shorted. By arranging the first voltage line V1 to be disposed on the same layer as the first electrode plate 151 of the storage capacitor, that is, the second metal layer 150 is patterned to further form the first voltage line V1, so that the first voltage line V1 and the first electrode plate 151 of the storage capacitor are formed in the same process, the manufacturing process of the array substrate can be reduced, and the additional metal layer can be avoided. Also, the capacitance value of the parasitic capacitance is inversely proportional to the distance between the two electrode plates. When the second metal layer 150 forms the first voltage line V1, the first voltage line V1, the middle active region 123 and the interlayer insulating layer directly form a parasitic capacitance, and the distance between the two electrode plates of the parasitic capacitance is only the thickness of the interlayer insulating layer, so that the maximum capacitance value of the parasitic capacitance formed when the overlapping area of the first voltage line V1 and the vertical projection of the middle active region 123 on the substrate 110 is constant can be ensured.
Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 5, the first voltage line V1 is disposed in the same layer as the source and drain of the threshold compensation transistor T1.
Specifically, the array substrate further includes a third metal layer 160, and the third metal layer 160 may form a source drain of the threshold compensation transistor T1, the data signal line VDATA, and the first power signal line VDD by patterning. In other embodiments, the first voltage line V1 may also be disposed at the same layer as the source and drain of the threshold compensation transistor T1, that is, the third metal layer 160 is patterned to form the first voltage line V1, and at this time, the first voltage line V1 may form a parasitic capacitor as the middle active region 123, so as to stabilize the potential of the middle node B of the threshold compensation transistor T1, and further avoid the threshold compensation transistor T1 from forming a leakage.
In addition to the above-described embodiments, the first voltage lines V1 are formed by patterning the second metal layer 160, for example. With continued reference to fig. 4, each pixel driving circuit 120 further includes a reference voltage signal line VREF; the first voltage line V1 is electrically connected to the reference voltage line VREF.
Specifically, the reference voltage line VREF is used to provide a reference voltage for the pixel driving circuit 120, and initialization of the pixel driving circuit 120 may be achieved. The reference voltage provided by the reference voltage line VREF is a fixed potential signal, and the first voltage line V1 is electrically connected to the reference voltage line VREF, so that the first voltage line V1 can directly obtain the fixed potential signal provided by the reference voltage line VREF, and a signal line additionally provided as a stable voltage provided by the first voltage line V1 on the array substrate is avoided.
With continued reference to fig. 4, each pixel drive circuit 120 further includes a drive transistor T2; a first pole of the threshold compensation transistor T1 is electrically connected to the gate 141 of the driving transistor T2, and a second pole of the threshold compensation transistor is electrically connected to the second pole of the driving transistor T2; the reference voltage signal line VREF is disposed at a side of the threshold compensation transistor T1 away from the driving transistor T2, and the data signal line VDATA is disposed at a side of the driving transistor T2 away from the threshold compensation transistor T1.
Specifically, the driving transistor T2 may be fabricated simultaneously with the threshold compensation transistor T1. The reference voltage signal line VREF is disposed on a side of the threshold compensation transistor T1 away from the driving transistor T2, and the data signal line VDATA is disposed on a side of the driving transistor T2 away from the threshold compensation transistor T1, such that in the same row of pixel driving circuits 120, along a direction in which the data signal line VDATA extends, the reference voltage signal line VREF and the data signal line VDATA are disposed on two sides of the pixel driving circuits 120, respectively. When the reference voltage signal line VREF is electrically connected to the first voltage line V1, and the first voltage line V1 extends to the threshold compensation transistor T1, the vertical projection overlap of the first voltage line V1 and the data signal line VDATA on the substrate 110 can be avoided, so that the parasitic capacitance on the data signal line VDATA can be reduced, further, the delay generated when the data signal on the data signal line VDATA is written can be reduced, which is beneficial to reducing the time requirement for data writing, and is beneficial to realizing a high refresh frequency of the display panel. Illustratively, when the first voltage line V1 does not overlap with the vertical projection of the data signal line VDATA on the substrate 110, the total capacitance on the data signal line VDATA can be decreased from 39.24pF to 34.88pF, i.e., the capacitance on the data signal line VDATA can be decreased by 11%, thereby decreasing the delay generated when the data signal on the data signal line VDATA is written.
With continued reference to fig. 4, the reference voltage line VREF is disposed on a side of the source-drain layer of the threshold compensation transistor T1 away from the substrate 110; the reference voltage line VREF extends in a direction in which the data signal line VDATA extends.
Specifically, the array substrate may further include a fourth metal layer 170, and the fourth metal layer 170 may form a reference voltage line VREF through patterning. The reference voltage line VREF is disposed in the fourth metal layer 170, which is beneficial to simplifying the routing configuration in the third metal layer 160 and reducing the difficulty in manufacturing the array substrate. In addition, the reference voltage line VREF extends along the extending direction of the data signal line VDATA, so that the overlap between the reference voltage line VREF and the vertical projection of the data signal line VDATA on the substrate 110 can be avoided, thereby being beneficial to further reducing the parasitic capacitance generated between the reference voltage line VREF and the data signal line VDATA, and further being beneficial to reducing the delay generated when the data signal on the data signal line VDATA is written.
In addition, the first voltage line V1 and the reference voltage line VREF are traces of different layers, so that the first voltage line V1 and the reference voltage line VREF can be electrically connected through a via. Illustratively, when the first voltage line V1 is located in the second metal layer 150, a via may be formed between the second metal layer 150 and the third metal layer 160, and then a via may be formed between the third metal layer 160 and the fourth metal layer 170, with the two vias forming a large via that extends through the second metal layer 150 and the fourth metal layer 170, thereby electrically connecting the first voltage line V1 to the reference voltage line VREF.
It should be noted that, when the first voltage line V1 is disposed in the third metal layer 160, as shown in fig. 5, a via hole may be formed between the third metal layer 160 and the fourth metal layer 170 to electrically connect the first voltage line V1 and the reference voltage line VREF.
With continued reference to fig. 4, each pixel driving circuit 120 further includes a first scan signal line S1 and a first initialization transistor T3; the gate of the first initialization transistor T3 is electrically connected to the first scan signal line S1, the first pole of the first initialization transistor T3 is electrically connected to the reference voltage line VREF, and the second pole of the first initialization transistor T3 is electrically connected to the gate 141 of the driving transistor T2.
Specifically, the first scan signal line S1 may be patterned by the first metal layer 140, and the first initialization transistor T3 may be fabricated simultaneously with the threshold compensation transistor T1. The first scan signal line S1 is electrically connected to the gate of the first initialization transistor T3, and provides a first scan signal to control the first initialization transistor T3 to be turned on or off. When the first initialization transistor T3 is controlled to be turned on by the first scan signal supplied from the first scan signal line S1, the reference voltage signal supplied from the reference voltage line VREF, which is input to the first pole of the first initialization transistor T3, is transmitted to the gate 141 of the driving transistor T2 through the first initialization transistor T3, thereby enabling initialization of the gate 141 of the driving transistor T2.
With continued reference to fig. 4, each pixel driving circuit 120 further includes a second scanning signal line S2 and a data writing transistor T4; the gate of the data writing transistor T4 is electrically connected to the second scanning signal line S2, the first pole of the data writing transistor T4 is electrically connected to the data signal line VDATA, and the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T2.
Specifically, the second scan signal line S2 may be patterned by the first metal layer 140. The data write transistor T4 may be fabricated at the same time as the threshold compensation transistor T1. The second scan signal line S2 is electrically connected to the gate of the data write transistor T4, and provides a second scan signal line to control the turn-on or turn-off of the data write transistor T4. When the data writing transistor T4 is controlled to be turned on by the second scan signal supplied from the second scan signal line S2, the data voltage signal supplied from the data signal line VDATA inputted to the first electrode of the data writing transistor T4 is transmitted to the gate electrode 141 of the driving transistor T2 through the data writing transistor T4, thereby implementing the writing of the data signal.
With continued reference to fig. 4, each pixel driving circuit 120 further includes a third scanning signal line S3, a light emitting device (not shown in the drawing), and a second initialization transistor T5; the gate of the second initialization transistor T5 is electrically connected to the third scan signal line S3, the first pole of the second initialization transistor T5 is electrically connected to the reference voltage line VREF, and the second pole of the second initialization transistor T5 is electrically connected to the anode of the light emitting device.
Specifically, the third scan signal line S3 may be patterned by the first metal layer 140. The second initialization transistor T5 may be fabricated simultaneously with the threshold compensation transistor T1. The third scan signal line S3 is electrically connected to the gate of the second initialization transistor T5, and provides a third scan signal to control the second initialization transistor T5 to be turned on or off. When the second initializing transistor T5 is controlled to be turned on by the third scan signal supplied from the third scan signal line S3, the reference voltage signal supplied from the reference voltage line VREF is transmitted to the anode of the light emitting device through the second shipment transistor T5, thereby initializing the anode of the light emitting device.
It should be noted that the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 may be formed from the first metal layer 140 in the same process. In addition, the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 may correspond to the scanning signal lines corresponding to the pixel driving circuits 120 in different rows on the array substrate, respectively. Illustratively, when the pixel driving circuit 120 is a pixel driving circuit of the ith row on the array substrate, the first scanning signal line S1 is a scanning signal line corresponding to the pixel driving circuit 120 of the ith-1 row, the second scanning signal line S2 is a scanning signal line corresponding to the pixel driving circuit 120 of the ith row, and the third scanning signal line S3 is a scanning signal line corresponding to the pixel driving circuit 120 of the ith +1 row. The scan signals supplied from the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are sequentially output.
With continued reference to fig. 4, each of the pixel driving circuits 120 further includes a light emission control signal line EM, a first light emission control transistor T6, and a second light emission control transistor T7. The light emission control signal line EM may be patterned by the first metal layer 140, and the first and second light emission control transistors T6 and T7 may be fabricated simultaneously with the threshold compensation transistor T1. The threshold compensation transistor T1, the driving transistor T2, the first initialization transistor T3, the data writing transistor T4, the second initialization transistor T5, the first light emission control transistor T6, and the second light emission control transistor T7 form all the transistors in the pixel driving circuit 120 of 7T 1C. The emission control signal line EM is electrically connected to the gates of the first and second emission control transistors T6 and T7, and supplies an emission control signal to control the first and second emission control transistors T6 and T7 to be turned on or off. The first light emitting control transistor T6 has a first pole electrically connected to the first power signal line VDD and a second pole electrically connected to the first pole of the driving transistor T2. A first pole of the second light emission controlling transistor T7 is electrically connected to a second pole of the driving transistor T2, and the second pole is electrically connected to an anode of the light emitting device. When the light emission control signal supplied from the light emission control signal line EM controls the first and second light emission control transistors T6 and T7 to be turned on, the first power signal supplied from the first power signal line VDD is transmitted to the first electrode of the driving transistor T2 through the first light emission control transistor T6, so that the driving transistor T2 is turned on and forms a driving current, which is transmitted to the anode of the light emitting device through the second light emission control transistor T7 to control the light emitting device to emit light.
The embodiment of the invention also provides a display panel. Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 6, the display panel 10 includes an array substrate 11 according to any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a substrate and a driving circuit layer positioned on the substrate, wherein pixel driving circuits are arranged in the driving circuit layer, and each pixel driving circuit comprises a threshold compensation transistor; the threshold compensation transistor includes a first channel region, a second channel region, and an intermediate active region disposed between the first channel region and the second channel region;
a first voltage line and a data signal line are arranged in the driving circuit layer; the first voltage line at least partially overlaps a vertical projection of the intermediate active region on the substrate, and the data signal line does not overlap the vertical projection of the first voltage line on the substrate.
2. The array substrate of claim 1, wherein each of the pixel driving circuits further comprises a storage capacitor; the first electrode plate of the storage capacitor and the first voltage line are arranged on the same layer.
3. The array substrate of claim 1, wherein the first voltage line is disposed in the same layer as a source drain of the threshold compensation transistor.
4. The array substrate of any one of claims 1-3, wherein each of the pixel driving circuits further comprises a reference voltage signal line; the first voltage line is electrically connected to the reference voltage line.
5. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a driving transistor; a first pole of the threshold compensation transistor is electrically connected with the grid electrode of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected with the second pole of the driving transistor;
the reference voltage signal line is arranged on one side of the threshold compensation transistor, which is far away from the driving transistor, and the data signal line is arranged on one side of the driving transistor, which is far away from the threshold compensation transistor.
6. The array substrate of claim 4, wherein the reference voltage line is disposed on a side of the source drain layer of the threshold compensation transistor away from the substrate; the reference voltage line extends along a direction in which the data signal line extends.
7. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a first scan signal line and a first initialization transistor;
the gate of the first initialization transistor is electrically connected to the first scan signal line, the first pole of the first initialization transistor is electrically connected to the reference voltage line, and the second pole of the first initialization transistor is electrically connected to the gate of the driving transistor.
8. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a second scanning signal line and a data writing transistor;
the gate of the data writing transistor is electrically connected to the second scanning signal line, the first pole of the data writing transistor is electrically connected to the data signal line, and the second pole of the data writing transistor is electrically connected to the first pole of the driving transistor.
9. The array substrate of claim 4, wherein each of the pixel driving circuits further comprises a third scanning signal line, a light emitting device, and a second initialization transistor;
the gate of the second initialization transistor is electrically connected to the third scanning signal line, the first electrode of the second initialization transistor is electrically connected to the reference voltage line, and the second electrode of the second initialization transistor is electrically connected to the anode of the light emitting device.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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