CN107037650A - A kind of array base palte, display panel and display device - Google Patents
A kind of array base palte, display panel and display device Download PDFInfo
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- CN107037650A CN107037650A CN201710260996.3A CN201710260996A CN107037650A CN 107037650 A CN107037650 A CN 107037650A CN 201710260996 A CN201710260996 A CN 201710260996A CN 107037650 A CN107037650 A CN 107037650A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention discloses a kind of array base palte, display panel and display device, the data lead-out wire not overlapped with scan signal line is set, avoid and parasitic capacitance formed between scan signal line and data lead-out wire, so avoid to data lead-out wire transmit data voltage interfere；And, data lead-out wire is connected with data wire, using by data lead-out wire as data line transfer data voltage, when data wire transmits data voltage to pixel cell corresponding with the scan signal line of Current Scan, greatly reduce the quantity of the parasitic capacitance of interference data voltage, improve the situation that parasitic capacitance is interfered to data voltage, improve the display effect of display device.
Description
Technical field
The present invention relates to display technology field, more specifically, it is related to a kind of array base palte, display panel and display dress
Put.
Background technology
Array base palte is as one of important composition part of display device, and the quality of its performance directly affects display device
Display effect.Complicated, its multi-strip scanning signal wire for generally including to intersect and insulating and a plurality of of array base palte
Data wire.Wherein, one end of scan signal line is connected with scan drive circuit, input and the data-driven structure phase of data wire
Even, when carrying out display scanning, scan drive circuit is scanned to scan signal line, and simultaneously in data input, data
Driving structure provides data voltage for data wire.Because scan signal line and data wire intersect setting, thus in scanning letter
The overlapping region of number line and data wire can produce parasitic capacitance, and in display device shows scanning process, parasitic capacitance is to data
The data voltage of line transmission is interfered so that data voltage changes when transmitting to pixel cell, reduction display device
Display effect.
The content of the invention
In view of this, the invention provides a kind of array base palte, display panel and display device, set and scan signal line
Not overlapping data lead-out wire, it is to avoid form parasitic capacitance between scan signal line and data lead-out wire, and then avoid pair
The data voltage of data lead-out wire transmission is interfered；And, data lead-out wire is connected with data wire, to pass through data lead-out wire
For data line transfer data voltage, data voltage is transmitted to pixel corresponding with the scan signal line of Current Scan in data wire
During unit, the only connection end of data wire and data lead-out wire, the parasitism in region between the scan signal line of Current Scan
Electric capacity is interfered to data voltage, is greatly reduced the quantity of the parasitic capacitance of interference data voltage, is improved parasitic capacitance pair
The situation that data voltage is interfered, improves the display effect of display device.
To achieve the above object, the technical scheme that the present invention is provided is as follows：
A kind of array base palte, includes a plurality of data lines and multi-strip scanning signal wire of intersecting and insulation, the multi-strip scanning
Signal wire includes the first scan signal line to N scan signal lines, and N is the integer not less than 2, in addition to：
Many data lead-out wires, first end and the data wire of the data lead-out wire connect one to one, the number
According to lead-out wire and the data wire connection end be located at adjacent two scan signal lines between, and the data lead-out wire with
The scan signal line is not overlapped；
And, driving structure, the driving structure is connected with the second end of the data lead-out wire, for passing through the number
It is the data line transfer data voltage according to lead-out wire.
The invention provides a kind of array base palte, display panel and display device, including intersecting and insulation many datas
Line and multi-strip scanning signal wire, the multi-strip scanning signal wire include the first scan signal line to N scan signal lines, and N is not
Integer less than 2, in addition to：Many data lead-out wires, first end and the data wire of the data lead-out wire are corresponded
Connection, the connection end of the data lead-out wire and the data wire is located between adjacent two scan signal lines, and described
Data lead-out wire is not overlapped with the scan signal line；And, driving structure, the driving structure and the data lead-out wire
Second end is connected, for being the data line transfer data voltage by the data lead-out wire.
As shown in the above, the technical scheme that the present invention is provided, sets the data not overlapped with scan signal line to draw
Line, it is to avoid parasitic capacitance is formed between scan signal line and data lead-out wire, and then avoids what is transmitted to data lead-out wires
Data voltage is interfered；And, data lead-out wire is connected with data wire, using by data lead-out wire as data line transfer data
Voltage, when data wire transmits data voltage to pixel cell corresponding with the scan signal line of Current Scan, greatly reduces
The quantity of the parasitic capacitance of interference data voltage, improves the situation that parasitic capacitance is interfered to data voltage, improves aobvious
The display effect of showing device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
A kind of structural representation for array base palte that Fig. 1 provides for the embodiment of the present application；
Fig. 2 a transmit schematic diagram for a kind of data voltage that the embodiment of the present application is provided；
Fig. 2 b are a kind of existing data voltage transmission schematic diagram；
The structural representation for another array base palte that Fig. 3 a provide for the embodiment of the present application；
The structural representation for another array base palte that Fig. 3 b provide for the embodiment of the present application；
The structural representation for another array base palte that Fig. 3 c provide for the embodiment of the present application；
Fig. 3 d are a kind of existing structural representation of array base palte；
The structural representation for another array base palte that Fig. 4 provides for the embodiment of the present application；
A kind of structural representation for display panel that Fig. 5 provides for the embodiment of the present application；
The structural representation for another display panel that Fig. 6 provides for the embodiment of the present application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As described in background, array base palte is complicated, and it is a plurality of that it generally includes to intersect and insulated
Scan signal line and a plurality of data lines.Wherein, one end of scan signal line is connected with scan drive circuit, the input of data wire
It is connected with data-driven structure, when carrying out display scanning, scan drive circuit is scanned to scan signal line, and is existed simultaneously
During data input, data-driven structure provides data voltage for data wire.Set because scan signal line and data wire intersect
Put, thus parasitic capacitance can be produced in the overlapping region of scan signal line and data wire, in display device shows scanning process,
Parasitic capacitance is interfered to the data voltage of data line transfer so that data voltage changes when transmitting to pixel cell,
Reduce the display effect of display device.
Based on this, the embodiment of the present application provides a kind of array base palte, display panel and display device, sets and believes with scanning
Data lead-out wire that number line is not overlapped, it is to avoid parasitic capacitance is formed between scan signal line and data lead-out wire, and then avoid
The data voltage that data lead-out wires is transmitted is interfered；And, the connection end that data lead-out wire is connected with data wire, distance
The length at data wire both ends is respectively less than the overall length of data wire, reduces connection end to the pressure drop between data wire both ends
Difference, in the corresponding pixel cell of the scan signal line for scanning diverse location, improves and inputs each picture by data wire
The larger situation of the data voltage difference of plain unit so that display device different zones display brightness is more uniform, improves display
The display effect of device.To achieve the above object, the technical scheme that the embodiment of the present application is provided is as follows, specific to combine Fig. 1 to Fig. 6
It is shown, the technical scheme that the embodiment of the present application is provided is described in detail.
With reference to shown in Fig. 1, a kind of structural representation of the array base palte provided for the embodiment of the present application, wherein, array base
Plate includes：
The a plurality of data lines 100 and multi-strip scanning signal wire 200 of intersecting and insulation, the multi-strip scanning signal wire 200 are wrapped
The first scan signal line is included to N scan signal lines, N is the integer not less than 2, in addition to：
Many data lead-out wires 300, the first end of the data lead-out wire 300 is corresponded with the data wire 100 to be connected
Connect, the connection end of the data lead-out wire 300 and the data wire 100 is located between adjacent two scan signal lines 200,
And the data lead-out wire 300 is not overlapped with the scan signal line 200, the present invention described in " not overlapping ", i.e., perpendicular to
On the direction of array base palte, the projection of data lead-out wire 300 and the projection of scan signal line 200 are misaligned；
And, driving structure 400, the driving structure 400 is connected with the second end of the data lead-out wire 300, is used for
It is that the data wire 100 transmits data voltage by the data lead-out wire 300.
As shown in the above, the technical scheme that the embodiment of the present application is provided, sets the number not overlapped with scan signal line
According to lead-out wire, it is to avoid form parasitic capacitance between scan signal line and data lead-out wire, and then avoid to data lead-out wire
The data voltage of transmission is interfered；And, data lead-out wire is connected with data wire, to be passed by data lead-out wire as data wire
Transmission of data voltage, when data wire transmits data voltage to pixel cell corresponding with the scan signal line of Current Scan, greatly
The quantity of the big parasitic capacitance for reducing interference data voltage, improves the situation that parasitic capacitance is interfered to data voltage, carries
The high display effect of display device.
Interference for parasitic capacitance to data voltage, its impedance for being mainly reflected in parasitic capacitance generation can be to data wire
On impedance impact, and then influence the data voltage that transmits on data wire.That is, voltage input end extremely ends from data wire
Between end, parasitic capacitance is formed between data wire and multi-strip scanning signal wire, wherein, the impedance meeting pair produced due to parasitic capacitance
Impedance on data wire is impacted, with data wire voltage input end to the direction for ending end, impedance on data wire with
And can gradually increase with overlapping the increasing for quantity of scan signal line, and then the pressure drop of data voltage transmitted on data wire can be caused
Increase therewith, the data voltage otherness finally transmitted to pixel cell is larger so that the Luminance Distribution of display device is uneven.
The embodiment of the present application improves parasitic capacitance and data voltage is caused by reducing the quantity of the parasitic capacitance to data voltage disturbance
The situation of interference, improves the uneven situation of the Luminance Distribution of display device, improves the display effect of display device.
The situation that data voltage is interfered is described in detail to improving parasitic capacitance below in conjunction with the accompanying drawings, wherein counting
The connection end being connected according to voltage by data lead-out wire with data wire is transmitted to data wire, is not passed in data voltage from connection end
Parasitic capacitance on the path for the scan signal line for transporting to Current Scan will not increase the pressure drop of data voltage, so, below thing
The connection end being connected in example with data lead-out wire with data wire, the parasitism electricity in region between the scan signal line of Current Scan
Hold and the disturbed condition of data voltage is illustrated.
With specific reference to shown in Fig. 2 a, schematic diagram is transmitted for a kind of data voltage that the embodiment of the present application is provided, wherein, array
Substrate includes：Data wire 101, scan signal line 201 are to scan signal line 207 and data lead-out wire 301；Wherein, data wire
101 intersect and insulate to scan signal line 207 with scan signal line 201 respectively.With reference to shown in Fig. 2 a, in data lead-out wire
301 connection ends being connected with data wire 101, to data wire 101 between the end of the side of scan signal line 201, are formed with altogether
Four parasitic capacitances, as data wire 101 are respectively with scan signal line 201, scan signal line 202, scan signal line 203 and sweeping
Retouch the parasitic capacitance of overlapping region formation between signal wire 204；And, the company being connected in data lead-out wire 301 with data wire 101
End is connect, three parasitic capacitances, as data wire are formed between the end of the side of scan signal line 207, altogether to data wire 101
The 101 parasitism electricity that overlapping region is formed between scan signal line 205, scan signal line 206 and scan signal line 207 respectively
Hold.Wherein, data wire 101 respectively with scan signal line 201, scan signal line 202, scan signal line 203 and scan signal line
Interference of the parasitic capacitance to data voltage of overlapping region formation between 204, with data wire 101 respectively with scan signal line 205,
The parasitic capacitance of overlapping region formation is to phase between the interference of data voltage between scan signal line 206 and scan signal line 207
Mutually without influence.
It is scanned to scan signal line 202, while being that data wire 101 transmits data electricity by data lead-out wire 301
During pressure, data voltage needs to transmit to scan signal line 202 and data wire 101 along data lead-out wire 301, data wire 101 to intersect
In the corresponding pixel cell in place.Wherein, believe because the connection end that data lead-out wire 301 is connected with data wire 101 is located at scanning
Region number between line 204 and scan signal line 205, thus, data voltage (direction as the dotted line arrows) will be along data
Lead-out wire 301 is transmitted to the connection end with data wire 101, then enters data wire 101 from connection end, and data voltage along
Data wire 101 is transmitted to the pixel cell corresponding to scan signal line 202 and the infall of data wire 101, is only swept
Retouch the parasitic capacitance of signal wire 204 and scan signal line 203 respectively with the formation of data wire 101 to interfere data voltage, subtract
The quantity of the parasitic capacitance of interference data voltage is lacked, has improved the situation that parasitic capacitance is interfered to data voltage, improve
The display effect of display device.
And in the prior art, with specific reference to shown in Fig. 2 b, being that a kind of existing data voltage transmits schematic diagram, wherein,
Array base palte includes：Data wire 101 ', scan signal line 201 ' are to scan signal line 207 '.Show and sweep in existing display device
When retouching, and the scan signal line of Current Scan, when being scan signal line 202 ', data voltage is needed from data wire 101 ' close to sweeping
The input for retouching signal wire 207 ' starts transmission, in this regard, being transmitted in data voltage along data wire 101 ' to scan signal line
202 ' with during the pixel cell corresponding to the infall of data wire 101 ', have five parasitic capacitances and data voltage are done
Disturb, as scan signal line 207 ', scan signal line 206 ', scan signal line 205 ', scan signal line 204 ' and scanning signal
The parasitic capacitance of line 203 ' respectively with the formation of data wire 101 '.The technical scheme carried compared to the above embodiments of the present application, it is existing
The parasitic capacitance quantity interfered in technology to data voltage is more, influences the display effect of display device.
In the embodiment of the application one, two institutes are included up between adjacent two scan signal line 200 that the application is provided
State data lead-out wire 300.That is, the embodiment of the present application is preferred, space region between adjacent two scan signal lines 200 are ensured
In the case that domain and pixel aperture ratio are not affected, many data lead-out wires can be included between adjacent two scan signal line 200
300, that is to say, that the connection end including multiple data lead-out wires 300 and data wire 100.
Further, with reference to shown in Fig. 3 a, the structural representation of another array base palte provided for the embodiment of the present application,
Wherein, all data lead-out wires 300 are located at 1+a scan signal lines 20 (1+a) and N-b scan signal lines 20 (N-b)
Between region, wherein, 1+a and N-b are positive integer, and 1+a is less than N-b.The array base palte that the embodiment of the present application is provided, owns
Data lead-out wire 300 is preferably centrally located at the middle body of all compositing areas of scan signal line 200, i.e. data lead-out wire
300 from the centre of all compositing areas of scan signal line 200 to both sides radiation profiles, to ensure that all data lead-out wires 300 are passed
Defeated data voltage, can be interfered, it is ensured that display device when showing scanning by the parasitic capacitance of negligible amounts to it
Display effect it is optimal.The embodiment of the present application is preferred, and a is identical with b numerical value.
Below in conjunction with the accompanying drawings 3b, Fig. 3 c, Fig. 3 d, shown in Tables 1 and 2, the technical scheme that the embodiment of the present application is provided is entered
The detailed description of row, wherein, Fig. 3 b to Fig. 3 c are illustrated by taking seven scan signal lines and two data wires as an example.
Wherein, the structural representation for another array base palte that Fig. 3 b provide for the embodiment of the present application, Fig. 3 b are specifically illustrated
Array base palte includes two data lead-out wires for data lead-out wire 301 and data lead-out wire 302；And, Fig. 3 b are using N as 7, a
Be to illustrate exemplified by 2 with b, then 1+a=1+2=3, N-b=7-2=5；Wherein, data lead-out wire 301 and data lead-out wire
302 are located at the middle body of scan signal line compositing area, i.e. data lead-out wire 301 is located at the 3rd scan signal line 203 and the
Between four scan signal lines 204, data lead-out wire 302 be located at the 4th scan signal line 204 and the 5th scan signal line 205 it
Between.
As a comparison, the structural representation for another array base palte that Fig. 3 c provide for the embodiment of the present application, wherein, Fig. 3 c
Show that data lead-out wire is located at the situation of scan signal line compositing area end, i.e. data lead-out wire 301 ' and is located at scan signal line
Between 205 and scan signal line 206, data lead-out wire 302 ' is located between scan signal line 206 and scan signal line 207.
And, as a comparison, Fig. 3 d are a kind of existing structural representation of array base palte, wherein, Fig. 3 d show array
Substrate includes scan signal line 201 ' to scan signal line 207 ' and two data lines 100 ', and two data lines 100 ' are respectively
Pass through input 301 " and the input data voltage of input 302 ".
For two kinds of situations shown in Fig. 3 b and Fig. 3 c, (that is, data lead-out wire is located in scan signal line compositing area
The situation and data lead-out wire of part are entreated positioned at the situation of the end of scan signal line compositing area), in whole scanning process
In (that is, to scan signal line 201 to the scanning process of scan signal line 207), the parasitic capacitance interfered to data voltage
Quantity situation is as shown in table 1：
Table 1
And, when Fig. 3 d show prior art, in whole scanning process, data voltage is interfered
The quantity situation of parasitic capacitance is as shown in table 2：
Table 2
Shown in reference table 1, in whole scanning process, the data electricity that data lead-out wire 301 and data lead-out wire 302 are transmitted
The quantity for the interference that the suffered parasitic capacitance of pressure is produced is 5+3+1+0+1+3+5=18；And data lead-out wire 301 ' and data are drawn
The quantity for the interference that the parasitic capacitance suffered by data voltage that outlet 302 ' is transmitted is produced is 9+7+5+3+1+0+1=26.Knot
Two kinds of situations and the data of table 1 shown in Fig. 3 b and Fig. 3 c are closed, is located at compared to data lead-out wire 301 ' and data lead-out wire 302 ' and sweeps
The situation of the end (i.e. between scan signal line 205 and scan signal line 207) of signal wire compositing area is retouched, the application is real
The data lead-out wire 301 and data lead-out wire 302 for applying example offer are located at the middle body of all scan signal line compositing areas (i.e.
Between scan signal line 203 and scan signal line 205) situation, data voltage is interfered during display
The negligible amounts of parasitic capacitance, improve the display effect of display device.
In addition, compared to the situation of the existing scanning process shown by Fig. 3 d and table 2, what data voltage was interfered posts
Raw electric capacity quantity is 12+10+8+6+4+2+0=42.I.e. no matter Fig. 3 b or Fig. 3 c that the application is provided any one is corresponding real
Example is applied, it is compared to prior art, and the quantity of the parasitic capacitance interfered during display to data voltage is less, improves
The display effect of display device.
It should be noted that Fig. 3 a, Fig. 3 b and Fig. 3 c illustrated embodiments are one kind in all wire structures of the application,
In the application other embodiment, wire structures can also be other modes, this application is not particularly limited, it is necessary to according to
Practical application carries out specific design.And, the length of the preferred all data wires of the embodiment of the present application is identical, it is ensured that data wire
Storage capacitance is consistent.
With reference to shown in Fig. 4, the structural representation of another array base palte provided for the embodiment of the present application, wherein, this Shen
Please embodiment provide the driving structure 400 include：
Multiplexer circuit 410, the multiplexer circuit 410 is connected with the second end of the data lead-out wire 300.Its
In, the output end of multiplexer circuit 410 is connected with data lead-out wire 300, and the input of multiplexer circuit 410 is with showing
The driving chip of showing device is connected, and driving chip is that multiplexer circuit 410 transmits data voltage, then, multi-path choice electricity
Road 410 selects corresponding data voltage and transmitted by data lead-out wire 300 to corresponding data line 100.
In the embodiment of the application one, the multiplexer circuit 410 is located at the bearing of trend of the scan signal line 200
Upper first side.
And, the array base palte that the embodiment of the present application is provided includes：Scan drive circuit 500, the turntable driving
Circuit 500 is connected with first scan signal line to the N scan signal lines, for being passed for the scan signal line 200
Defeated scanning signal；
Wherein, the scan drive circuit 500 is located at the second side on the bearing of trend of the scan signal line 200.
As shown in the above, in the embodiment of the present application, by scan drive circuit 500 and the phase of multiplexer circuit 410
Two sides to being arranged at scan signal line 200, reasonable line arrangement, the wire bond of optimization array substrate are carried out with array substrate
Structure.
In the above-mentioned any one embodiment of the application, the data lead-out wire is located at same conduction with the scan signal line
Layer.Wherein, data lead-out wire and scan signal line are arranged at same conductive layer, and then avoid increasing conduction newly in manufacturing process
The situation of layer, has reached the purpose economized on resources.And, data lead-out wire and data wire can be connected by via.
It should be noted that in the application other embodiment, data lead-out wire and scan signal line may be located on not
Same conductive layer, is not particularly limited to this application, it is necessary to carry out specific design according to practical application.
Accordingly, the embodiment of the present application additionally provides a kind of display panel, and the display panel includes above-mentioned any one reality
The array base palte of example offer is provided.
It should be noted that the display panel that the embodiment of the present application is provided, it can be liquid crystal display panel, can also be
Organic electroluminescent display panel, or electronic paper display panel etc., this application is not particularly limited, it is necessary to be answered according to actual
With specifically being chosen.
With reference to shown in Fig. 5, a kind of structural representation of the display panel provided for the embodiment of the present application, the embodiment of the present application
The display panel 10 provided can be circular display panel, and display panel is made as to the display of the display devices such as dial plate
Panel.
Display panel 10 includes viewing area AA, and viewing area AA is provided with the array that above-mentioned any one embodiment is provided
The structures such as scan signal line, gate line and the data lead-out wire of substrate.And, display panel 10 frame region and along sweeping
The both sides direction of signal wire is retouched, data scanning region 101 and gated sweep region 102 is provided with.
Wherein, data scanning region 101 can be provided with the multichannel choosing for the array base palte that above-mentioned any one embodiment is provided
Circuit is selected, multiplexer circuit is connected with driving chip, and, gated sweep region 102 is provided with above-mentioned any one implementation
The scan drive circuit for the array base palte that example is provided.
Further, data scanning region 101 is also provided with the structures such as static release circuit, and this application is not made
Concrete restriction.
With reference to shown in Fig. 6, the structural representation of another display panel provided for the embodiment of the present application, wherein, with Fig. 5
Unlike corresponding embodiment, the display panel shown in the application Fig. 6, its data scanning region 101 and gated sweep region
102 can also be reversed with position shown in Fig. 5.
Accordingly, the embodiment of the present application additionally provides a kind of display device, and the display device includes above-mentioned any one reality
The display panel of example offer is provided.
It should be noted that the display device that the embodiment of the present application is provided, it can be liquid crystal display device, can also be
Organic electroluminescent display device, or display device of electronic paper etc., this application is not particularly limited, it is necessary to be answered according to actual
With specifically being chosen.
The embodiment of the present application provides a kind of array base palte, display panel and display device, including intersecting and insulation many
Data line and multi-strip scanning signal wire, the multi-strip scanning signal wire include the first scan signal line to N scan signal lines,
N is the integer not less than 2, in addition to：Many data lead-out wires, the first end and the data wire of the data lead-out wire are one by one
Correspondence connection, the connection end of the data lead-out wire and the data wire is located between adjacent two scan signal lines, and
The data lead-out wire is not overlapped with the scan signal line；And, driving structure, the driving structure is drawn with the data
Second end of line is connected, for being the data line transfer data voltage by the data lead-out wire.
As shown in the above, the technical scheme that the embodiment of the present application is provided, sets the number not overlapped with scan signal line
According to lead-out wire, it is to avoid form parasitic capacitance between scan signal line and data lead-out wire, and then avoid to data lead-out wire
The data voltage of transmission is interfered；And, data lead-out wire is connected with data wire, to be passed by data lead-out wire as data wire
Transmission of data voltage, when data wire transmits data voltage to pixel cell corresponding with the scan signal line of Current Scan, greatly
The quantity of the big parasitic capacitance for reducing interference data voltage, improves the situation that parasitic capacitance is interfered to data voltage, carries
The high display effect of display device.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (11)
1. a kind of array base palte, includes a plurality of data lines and multi-strip scanning signal wire of intersecting and insulation, the multi-strip scanning letter
Number line includes the first scan signal line to N scan signal lines, and N is the integer not less than 2, it is characterised in that also included：
Many data lead-out wires, first end and the data wire of the data lead-out wire are connected one to one, and the data are drawn
The connection end of outlet and the data wire be located at adjacent two scan signal lines between, and the data lead-out wire with it is described
Scan signal line is not overlapped；
And, driving structure, the driving structure is connected with the second end of the data lead-out wire, for being drawn by the data
Outlet is the data line transfer data voltage.
2. array base palte according to claim 1, it is characterised in that include up to two between adjacent two scan signal line
The data lead-out wire.
3. array base palte according to claim 2, it is characterised in that all data lead-out wires are scanned positioned at 1+a
Region between signal wire and N-b scan signal lines, wherein, 1+a and N-b are positive integer, and 1+a is less than N-b.
4. array base palte according to claim 3, it is characterised in that a is identical with b numerical value.
5. array base palte according to claim 1, it is characterised in that the driving structure includes：
Multiplexer circuit, the multiplexer circuit is connected with the second end of the data lead-out wire.
6. array base palte according to claim 5, it is characterised in that the multiplexer circuit is located at the scanning signal
First side on the bearing of trend of line.
7. array base palte according to claim 6, it is characterised in that the array base palte includes：Scan drive circuit, institute
State scan drive circuit with first scan signal line to the N scan signal lines to be connected, for for the scanning signal
Line transmits scanning signal；
Wherein, the scan drive circuit is located at the second side on the bearing of trend of the scan signal line.
8. array base palte according to claim 1, it is characterised in that the data lead-out wire and scan signal line position
In same conductive layer.
9. a kind of display panel, it is characterised in that the display panel includes the array described in claim 1~8 any one
Substrate.
10. display panel according to claim 9, it is characterised in that the display panel is circular display panel.
11. a kind of display device, it is characterised in that the display device includes the display panel described in claim 9 or 10.
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| CN107037650B (en) | 2019-12-27 |
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Effective date of registration: 20210929 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |