CN109212799B - Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board - Google Patents
Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board Download PDFInfo
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- CN109212799B CN109212799B CN201811258712.8A CN201811258712A CN109212799B CN 109212799 B CN109212799 B CN 109212799B CN 201811258712 A CN201811258712 A CN 201811258712A CN 109212799 B CN109212799 B CN 109212799B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
Abstract
The invention discloses a peripheral circuit structure of a liquid crystal panel, which is arranged in a panel unit, wherein the panel unit comprises a first liquid crystal panel and a second liquid crystal panel which have different sizes, and the peripheral circuit structure comprises: the first group of signal wires are electrically connected with the signal input terminals of the first liquid crystal panel, the second group of signal wires are electrically connected with the signal input terminals of the second liquid crystal panel, the first group of HVA alignment pads and the first group of array test pads are respectively electrically connected with the first group of signal wires, and the second group of HVA alignment pads and the second group of array test pads are respectively electrically connected with the second group of signal wires; wherein the first group of signal lines extends from the first edge area to the third edge area of the panel unit via the second edge area, and the second group of signal lines extends from the first edge area to the third edge area of the panel unit via the fourth edge area. The invention also discloses a liquid crystal display motherboard which comprises the peripheral circuit structure.
Description
Technical Field
The invention relates to the technical field of displays, in particular to a peripheral circuit structure of a liquid crystal panel and a liquid crystal display mother board.
Background
With the improvement of living standard of people, large-size liquid crystal televisions are more and more popular with consumers, and the liquid crystal televisions are turned from small to large, so that the production of large-size liquid crystal display panels has good market and development situation. However, due to the limitation of generation line, the simple production of large-sized liquid crystal display panels with single size will result in low utilization rate of large panels and higher production cost, and thus limit the market development.
At present, the MMG (multi-model Glass) cutting technology is adopted to overcome the defect, namely, two liquid crystal panels with different sizes are designed on the same Glass substrate in a mixed mode, so that the utilization rate of the Glass substrate is greatly improved. For example, G8.5 generation line, the cutting utilization rate of pure cutting 43 inches is only 75 percent; and the cutting utilization rate of the glass substrate reaches 97 percent when the glass substrate is cut by mixing 43 inches and 22 inches.
The MMG cut-in liquid crystal display mother panel usually employs an HVA (High Vertical Alignment) Alignment technology (HVA current), which mainly utilizes polymerization of macromolecules in the liquid crystal under the combined action of ultraviolet light and voltage, and realizes automatic Alignment of the liquid crystal. The HVA Curing process is as follows: firstly, a certain proportion of high-purity reactive liquid crystal (phototaxis monomer, the liquid crystal has a liquid crystal core of common liquid crystal molecules and has one or more reactive light energy groups such as acrylic groups at the tail end) is doped into VA liquid crystal; then, a voltage is applied between the upper substrate and the lower substrate to enable the liquid crystal molecules to generate a pre-tilt angle; after UV light in a specific wavelength range is irradiated from the TFT substrate side, the reactive liquid crystal is polymerized into a polymer network to attract the liquid crystal molecules of the surface layer to form a fixed pretilt angle. Therefore, it is necessary to apply a certain voltage to the liquid crystal panel from a peripheral circuit while the liquid crystal panel is irradiated with ultraviolet light.
In the liquid crystal display mother board of the existing MMG product, peripheral circuits of a liquid crystal panel all adopt a structure of single-side wiring. As shown in fig. 1, one panel unit 1 of the liquid crystal display mother panel includes a liquid crystal panel a and a liquid crystal panel B having different sizes, a first group of signal lines 2a and a second group of signal lines 2B are disposed in an edge area of the panel unit 1, the first group of signal lines 2a and the second group of signal lines 2B are arranged in parallel on the same side of the panel unit 1, the first group of signal lines 2a are electrically connected to signal input terminals (including a source side terminal 3a and a gate side terminal 3B) of the liquid crystal panel a, and the second group of signal lines 2B are electrically connected to signal input terminals (including a source side terminal 4a and a gate side terminal 4B) of the liquid crystal panel B. The first group of signal lines 2a is used for an alignment circuit for HVA alignment of the liquid crystal panel a and also used for a detection circuit for an Array Test (Array Test) of the liquid crystal panel a, and thus, as shown in fig. 1, the first group of signal lines 2a is also electrically connected to an alignment Pad (Pad)5a for HVA alignment of the liquid crystal panel a and a Test Pad 6a for the Array Test. Similarly, the second group of signal lines 2B is used for an alignment circuit for HVA alignment of the liquid crystal panel B and also for a detection circuit for Array Test (Array Test) of the liquid crystal panel B, and therefore, as shown in fig. 1, the second group of signal lines 2B is also electrically connected to an alignment pad 5B for HVA alignment of the liquid crystal panel B and a Test pad 6B for Array Test.
As the peripheral circuit structure of the liquid crystal panel shown in fig. 1, since the first group of signal lines 2a and the second group of signal lines 2B employ one-sided wiring, the connection lines 7a between the array test pads 6a and the first group of signal lines 2a and the second group of signal lines 2B form cross wiring regions 8a, and the connection lines 7B between the second group of signal lines 2B and the signal input terminals of the liquid crystal panel B and the first group of signal lines 2a form cross wiring regions 8B. Since the first group of signal lines 2a and the second group of signal lines 2b usually include a plurality of signal lines with small pitches, the number of the cross wiring regions 8a and the number of the cross wiring regions 8b are large, and there are usually hundreds or thousands of the cross wiring regions, and ESD (Electro-Static discharge) is very likely to occur in the cross wiring regions 8a and 8b, which may cause cracking or even damage of the circuit structure, further cause poor HVA alignment process or inaccurate array test, increase the defect rate of the final product, and increase the production cost.
Accordingly, there is a need for improvements and developments in the art.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a peripheral circuit structure of a liquid crystal panel to improve the problem of increased defect rate caused by the presence of crossed wiring areas in peripheral signal lines in the peripheral circuit structure of the liquid crystal panel of MMG products.
In order to achieve the purpose, the invention adopts the following technical scheme:
a peripheral circuit structure of a liquid crystal panel provided in a panel unit including a first liquid crystal panel and a second liquid crystal panel which are different in size from each other, wherein the peripheral circuit structure comprises: a first group of signal lines electrically connected to the signal input terminals of the first liquid crystal panel, a second group of signal lines electrically connected to the signal input terminals of the second liquid crystal panel, a first group of HVA alignment pads and a first group of array test pads electrically connected to the first group of signal lines, respectively, and a second group of HVA alignment pads and a second group of array test pads electrically connected to the second group of signal lines, respectively;
wherein the panel unit includes a first edge area, a second edge area, a third edge area, and a fourth edge area, the first group of signal lines extends from the first edge area to the third edge area via the second edge area, and the second group of signal lines extends from the first edge area to the third edge area via the fourth edge area.
Specifically, the first group of HVA alignment pads and the second group of HVA alignment pads are disposed on the first edge region, the first group of array test pads is disposed on the second edge region, and the second group of array test pads is disposed on the fourth edge region.
Specifically, the first liquid crystal panel and the second liquid crystal panel are both non-GOA type liquid crystal panels; the signal input terminals of the first liquid crystal panel include a first source-side terminal and a first gate-side terminal, the first source-side terminal being disposed at a side of the first liquid crystal panel facing the first edge region, the first gate-side terminal being disposed at a side of the first liquid crystal panel facing the second edge region, the first group of signal lines being electrically connected to the first source-side terminal and the first gate-side terminal at the first edge region and the second edge region, respectively; the signal input terminals of the second liquid crystal panel include a second source-side terminal and a second gate-side terminal, the second source-side terminal being disposed at a side of the second liquid crystal panel facing the fourth edge region, the second gate-side terminal being disposed at a side of the second liquid crystal panel facing the third edge region, the second group of signal lines being electrically connected to the second source-side terminal and the second gate-side terminal at the fourth edge region and the third edge region, respectively.
Further, if the first liquid crystal panel has a higher signal accuracy requirement than the second liquid crystal panel in the HVA alignment process, the first set of HVA alignment pads and the second set of HVA alignment pads are disposed at an end of the first edge region adjacent to the second edge region to reduce the routing resistance from the first set of HVA alignment pads to the signal input terminals of the first liquid crystal panel; if the second liquid crystal panel has higher precision requirement on signals in the HVA alignment process than the first liquid crystal panel, the first group of HVA alignment pads and the second group of HVA alignment pads are arranged at one end of the first edge region close to the fourth edge region, so as to reduce the routing resistance from the second group of HVA alignment pads to the signal input terminals of the second liquid crystal panel.
Further, the size of the first liquid crystal panel is smaller than that of the second liquid crystal panel, the second and fourth edge regions have portions having a larger width at both sides corresponding to the first liquid crystal panel, the first group of array test pads is disposed at the portion having a larger width in the second edge region, and the second group of array test pads is disposed at the portion having a larger width in the fourth edge region.
Further, the peripheral circuit structure further includes a third set of HVA alignment pads and a fourth set of HVA alignment pads disposed at the third edge region, the third set of HVA alignment pads is electrically connected to the first set of signal lines, and the fourth set of HVA alignment pads is electrically connected to the second set of signal lines.
Specifically, the first liquid crystal panel and the second liquid crystal panel are both GOA type liquid crystal panels; the signal input terminals of the first liquid crystal panel include a first source-side terminal disposed on a side of the first liquid crystal panel facing the first edge region, the first group of signal lines being electrically connected to the first source-side terminal at the first edge region; the signal input terminal of the second liquid crystal panel includes a second source-side terminal disposed at a side of the second liquid crystal panel facing the fourth edge region, and the second group of signal lines is electrically connected to the second source-side terminal at the fourth edge region.
Further, the size of the first liquid crystal panel is smaller than that of the second liquid crystal panel, the second and fourth edge regions have portions having a larger width at both sides corresponding to the first liquid crystal panel, the first group of array test pads is disposed at the portion having a larger width in the second edge region, and the second group of array test pads is disposed at the portion having a larger width in the fourth edge region.
Further, the peripheral circuit structure further includes a third set of HVA alignment pads and a fourth set of HVA alignment pads disposed at the third edge region, the third set of HVA alignment pads is electrically connected to the first set of signal lines, and the fourth set of HVA alignment pads is electrically connected to the second set of signal lines.
The invention also provides a liquid crystal display mother board, which comprises at least one panel unit, wherein the panel unit comprises a first liquid crystal panel and a second liquid crystal panel which have different sizes, and the panel unit is internally provided with the peripheral circuit structure of the liquid crystal panel.
In the peripheral circuit structure of the liquid crystal panel provided by the embodiment of the invention, in the panel unit comprising two liquid crystal panels with different sizes, for two groups of different signal lines (which are respectively multiplexed into an HVA (high voltage alternating current) alignment line and an array test line), a structure of wiring at two sides is adopted, so that a crossed wiring area in the peripheral circuit structure is reduced or even avoided, the risk of an ESD (electro-static discharge) phenomenon in the peripheral circuit is reduced, the product yield is improved, and the production cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of a peripheral circuit of a conventional liquid crystal panel;
fig. 2 is a schematic structural diagram of a mother panel for a liquid crystal display provided in embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a peripheral circuit of a liquid crystal panel provided in embodiment 1 of the present invention;
fig. 4 is a schematic configuration diagram of a peripheral circuit of another preferred embodiment in embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a peripheral circuit of a liquid crystal panel provided in embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are exemplary only, and the invention is not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
Example 1
The present embodiment provides a liquid crystal display mother board, as shown in fig. 2, the liquid crystal display mother board 100 is a MMG type product, the liquid crystal display mother board 100 includes at least one panel unit 10 (two panel units 10 are exemplarily shown in the figure), the panel unit 10 includes a first liquid crystal panel a and a second liquid crystal panel B which are different in size from each other, the first liquid crystal panel a and the second liquid crystal panel B may be the same type of liquid crystal panel, such as a liquid crystal panel both of a GOA (Gate Driver on Array, Array substrate line drive) type, or a liquid crystal panel both of a non-GOA type, and the first liquid crystal panel a and the second liquid crystal panel B may also be different types of liquid crystal panels, such as a liquid crystal panel of one of the GOA types and a liquid crystal panel of the other of the non-GOA type. Two liquid crystal panels with different sizes are designed on the same glass substrate in a mixed mode, so that the utilization rate of the glass substrate is greatly improved.
The present embodiment also provides a peripheral circuit structure of a liquid crystal panel, which is disposed in the panel unit 10 of the liquid crystal display mother panel 100. Referring to fig. 3, the peripheral circuit structure includes: a first set of signal lines 21, a second set of signal lines 22, a first set of HVA alignment pads 31, a second set of HVA alignment pads 32, a first set of array test pads 41, and a second set of array test pads 42.
As shown in fig. 3, the panel unit 10 includes a first edge area 10a, a second edge area 10b, a third edge area 10c, and a fourth edge area 10d, the first edge area 10a and the third edge area 10c are located at opposite sides, and the second edge area 10b and the fourth edge area 10d are located at opposite other sides. The first group of signal lines 21 extends from the first edge region 10a to the third edge region 10c via the second edge region 10b, and the second group of signal lines 22 extends from the first edge region 10a to the third edge region 10c via the fourth edge region 10 d.
The first set of HVA alignment pads 31 and the first set of array test pads 41 are electrically connected to the first set of signal lines 21, respectively, and the second set of HVA alignment pads 32 and the second set of array test pads 42 are electrically connected to the second set of signal lines 22, respectively. In this embodiment, the first set of HVA alignment pads 31 and the second set of HVA alignment pads 32 are disposed on the first edge region 10a, the first set of array test pads 41 is disposed on the second edge region 10b, and the second set of array test pads 42 is disposed on the fourth edge region 10 d.
The first group of signal lines 21 is electrically connected to the signal input terminals of the first liquid crystal panel a, and the second group of signal lines 22 is electrically connected to the signal input terminals of the second liquid crystal panel B.
In this embodiment, as shown in fig. 3, the first liquid crystal panel a and the second liquid crystal panel B are both non-GOA type liquid crystal panels. The signal input terminals of the first liquid crystal panel a include a first source-side terminal 51 and a first gate-side terminal 52, the first source-side terminal 51 is disposed at a side of the first liquid crystal panel a facing the first edge region 10a, the first gate-side terminal 52 is disposed at a side of the first liquid crystal panel a facing the second edge region 10b, the first group of signal lines 21 is electrically connected to the first source-side terminal 51 at the first edge region 10a, and the first group of signal lines 21 is electrically connected to the first gate-side terminal 52 at the second edge region 10 b. The signal input terminals of the second liquid crystal panel B include a second source-side terminal 61 and a second gate-side terminal 62, the second source-side terminal 61 is disposed at a side of the second liquid crystal panel B facing the fourth edge region 10d, the second gate-side terminal 62 is disposed at a side of the second liquid crystal panel B facing the third edge region 10c, the second group signal line 22 is electrically connected to the second source-side terminal 61 at the fourth edge region 10d, and the second group signal line 22 is electrically connected to the second gate-side terminal 62 at the third edge region 10 c.
The peripheral circuit structure of the liquid crystal panel as described above:
when the alignment process is performed on the first liquid crystal panel a, an external signal is input from the first group HVA alignment pads 31, connected to the first source-side terminal 51 and the first gate-side terminal 52 of the first liquid crystal panel a through the first group signal lines 21, whereby the external signal is input into the first liquid crystal panel a for alignment.
When the alignment process is performed on the second liquid crystal panel B, an external signal is input from the second group HVA alignment pad 32, connected to the second source-side terminal 61 and the second gate-side terminal 62 of the second liquid crystal panel B through the second group signal line 22, and thus input into the second liquid crystal panel B for alignment.
When the array test is performed on the first liquid crystal panel a, an external signal is input from the first group of array test pads 41, connected to the first source-side terminal 51 and the first gate-side terminal 52 of the first liquid crystal panel a through the first group of signal lines 21, and thus input into the first liquid crystal panel a for the array test.
When the array test is performed on the second liquid crystal panel B, an external signal is input from the second group array test pad 42, connected to the second source-side terminal 61 and the second gate-side terminal 62 of the second liquid crystal panel B through the second group signal line 22, and thus input into the second liquid crystal panel B for the array test.
In the peripheral circuit structure of the liquid crystal panel, referring to fig. 3, the signal lines 21 and 22 corresponding to the first liquid crystal panel a and the second liquid crystal panel B respectively adopt a structure of wiring on two sides in the panel unit 10, which reduces or even avoids the existence of crossed wiring areas in the peripheral circuit structure, reduces the risk of ESD in the peripheral circuit, improves the product yield, and saves the production cost, compared with the prior art.
Further, in the prior art, a single-sided wiring structure is adopted, and the first liquid crystal panel a and the second liquid crystal panel B are located at the edge of the panel unit 10 that is biased to one side (for example, wiring is carried out at the fourth edge region 10d, and then the panels are biased to the second edge region 10B) rather than at the center of the panel unit 10, which may cause the risk of the liquid crystal panel having poor edge mura. As the peripheral circuit structure in the above embodiment adopts a structure of wiring on both sides, the positions of the first liquid crystal panel a and the second liquid crystal panel B can be made to approach the center of the panel unit 10, and the risk of occurrence of edge mura defects in the liquid crystal panel can be reduced; and the symmetrical structure of both sides wiring, the room that the wiring space can be adjusted is great, reduces the technology degree of difficulty in the production process.
Further, in this embodiment, the accuracy requirement of the first liquid crystal panel a on the signal in the HVA alignment process is higher than that of the second liquid crystal panel B, therefore, as shown in fig. 3, the first set of HVA alignment pads 31 and the second set of HVA alignment pads 32 are disposed at one end of the first edge region 10a close to the second edge region 10B, so as to reduce the routing resistance from the first set of HVA alignment pads 31 to the signal input terminals of the first liquid crystal panel a.
In some other embodiments, if the signal accuracy requirement of the second liquid crystal panel B in the HVA alignment process is higher than that of the first liquid crystal panel a, at this time, as shown in fig. 4, the first set of HVA alignment pads 31 and the second set of HVA alignment pads 32 are disposed at an end of the first edge region 10a close to the fourth edge region 10d, so as to reduce the routing resistance between the second set of HVA alignment pads 32 and the signal input terminals of the second liquid crystal panel B.
Further, in the present embodiment, as shown in fig. 3, the size of the first liquid crystal panel a is smaller than that of the second liquid crystal panel B, the width of the second liquid crystal panel B is larger than that of the first liquid crystal panel a in a direction from the second edge region 10B to the fourth edge region 10d, and the second edge region 10B and the fourth edge region 10d have portions having larger widths (with respect to the widths at both sides of the second liquid crystal panel B) at both sides corresponding to the first liquid crystal panel a. The first group of array test pads 41 is disposed on the portion of the second edge region 10b with the larger width, and the second group of array test pads 42 is disposed on the portion of the fourth edge region 10d with the larger width, so as to minimize the area of the panel unit 10 occupied by the peripheral circuit structure.
Further, in the embodiment, as shown in fig. 3, the peripheral circuit structure further includes a third group of HVA alignment pads 31a and a fourth group of HVA alignment pads 32a, the third group of HVA alignment pads 31a and the fourth group of HVA alignment pads 32a are disposed in the third edge region 10c, the third group of HVA alignment pads 32a is electrically connected to the first group of signal lines 21, and the fourth group of HVA alignment pads 32a is electrically connected to the second group of signal lines 22. The third group of HVA alignment pads 31a and the first group of HVA alignment pads 31 have the same structure, and they can be replaced with each other; similarly, the fourth set of HVA alignment pads 32a and the second set of HVA alignment pads 32 are the same in structure, and they may be replaced with each other. When a plurality of panel units 10 are arranged in an array in the lcd mother panel 100, the first group of HVA alignment pads 31 and the second group of HVA alignment pads 32 in the first edge region 10a of some of the panel units 10 are more convenient to receive external signals, and at this time, the first group of HVA alignment pads 31 and the second group of HVA alignment pads 32 are used to receive externally input alignment signals; while the third and fourth sets of HVA alignment pads 31a and 32a in the third edge region 10c in some other panel units 10 are more convenient for receiving external signals, the third and fourth sets of HVA alignment pads 31a and 32a are used for receiving externally input alignment signals.
Example 2
This embodiment provides a peripheral circuit structure of a liquid crystal panel, and is different from embodiment 1 in that, as shown in fig. 5, both the first liquid crystal panel a and the second liquid crystal panel B in the panel unit 10 are GOA type liquid crystal panels.
The signal input terminal of the first liquid crystal panel a includes a first source-side terminal 51a, the first source-side terminal 51a is disposed at a side of the first liquid crystal panel a facing the first edge region 10a, and the first group signal line 21 is electrically connected to the first source-side terminal 51a at the first edge region 10 a. The signal input terminal of the second liquid crystal panel B includes a second source-side terminal 61a, the second source-side terminal 61a is disposed on a side of the second liquid crystal panel B facing the fourth edge region 10d, and the second group signal line 22 is electrically connected to the second source-side terminal 61a in the fourth edge region 10 d. The wiring method of the peripheral circuit structure of the present embodiment is the same as that of embodiment 1, and the technical effects obtained by the two are also similar.
It should be noted that, since the panel types of the first liquid crystal panel a and the second liquid crystal panel B in the present embodiment are different from those in embodiment 1, the number of signal lines included in each group of the signal lines 21/22 and the number of external signals to be received by the HVA alignment pads 31/32 and the array test pads 41/42 are different, and such a difference is easily understood by those skilled in the art.
In summary, the peripheral circuit structure of the liquid crystal panel and the corresponding liquid crystal display mother panel provided by the above embodiments adopt a double-sided wiring structure, thereby improving the problem of increased defect rate caused by the presence of the crossed wiring area in the peripheral signal lines in the peripheral circuit structure of the MMG liquid crystal product.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing is directed to embodiments of the present application and it is noted that numerous modifications and adaptations may be made by those skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.
Claims (3)
1. A peripheral circuit structure of a liquid crystal panel provided in a panel unit including a first liquid crystal panel and a second liquid crystal panel which are different in size from each other, characterized by comprising: a first group of signal lines electrically connected to the signal input terminals of the first liquid crystal panel, a second group of signal lines electrically connected to the signal input terminals of the second liquid crystal panel, a first group of HVA alignment pads and a first group of array test pads electrically connected to the first group of signal lines, respectively, and a second group of HVA alignment pads and a second group of array test pads electrically connected to the second group of signal lines, respectively;
wherein the panel unit includes a first edge area, a second edge area, a third edge area, and a fourth edge area, the first group of signal lines extending from the first edge area to the third edge area via the second edge area, the second group of signal lines extending from the first edge area to the third edge area via the fourth edge area;
the first liquid crystal panel and the second liquid crystal panel are non-GOA type liquid crystal panels; the signal input terminals of the first liquid crystal panel include a first source-side terminal and a first gate-side terminal, the first source-side terminal being disposed at a side of the first liquid crystal panel facing the first edge region, the first gate-side terminal being disposed at a side of the first liquid crystal panel facing the second edge region, the first group of signal lines being electrically connected to the first source-side terminal and the first gate-side terminal at the first edge region and the second edge region, respectively; the signal input terminals of the second liquid crystal panel include a second source-side terminal and a second gate-side terminal, the second source-side terminal being disposed at a side of the second liquid crystal panel facing the fourth edge region, the second gate-side terminal being disposed at a side of the second liquid crystal panel facing the third edge region, the second group of signal lines being electrically connected to the second source-side terminal and the second gate-side terminal at the fourth edge region and the third edge region, respectively;
wherein, if the first liquid crystal panel has a higher precision requirement on signals than the second liquid crystal panel in the HVA alignment process, the first group of HVA alignment pads and the second group of HVA alignment pads are disposed at one end of the first edge region adjacent to the second edge region to reduce the routing resistance from the first group of HVA alignment pads to the signal input terminals of the first liquid crystal panel; if the precision requirement of the second liquid crystal panel on signals in the HVA alignment process is higher than that of the first liquid crystal panel, the first group of HVA alignment pads and the second group of HVA alignment pads are arranged at one end, close to the fourth edge area, of the first edge area, so that the routing resistance from the second group of HVA alignment pads to the signal input terminals of the second liquid crystal panel is reduced;
wherein the first liquid crystal panel has a size smaller than that of the second liquid crystal panel, the second and fourth edge regions have portions having a larger width at both sides corresponding to the first liquid crystal panel, the first group of array test pads is disposed at the portion having the larger width in the second edge region, and the second group of array test pads is disposed at the portion having the larger width in the fourth edge region.
2. A peripheral circuit structure of a liquid crystal panel according to claim 1, further comprising a third group of HVA alignment pads and a fourth group of HVA alignment pads, the third group of HVA alignment pads and the fourth group of HVA alignment pads being disposed at the third edge region, the third group of HVA alignment pads being electrically connected to the first group of signal lines, the fourth group of HVA alignment pads being electrically connected to the second group of signal lines.
3. A liquid crystal display mother panel comprising at least one panel unit including a first liquid crystal panel and a second liquid crystal panel which are different in size from each other, wherein a peripheral circuit structure of the liquid crystal panel according to any one of claims 1 to 2 is provided in the panel unit.
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| CN201811258712.8A CN109212799B (en) | 2018-10-26 | 2018-10-26 | Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board |
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| CN201811258712.8A CN109212799B (en) | 2018-10-26 | 2018-10-26 | Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board |
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| CN111323952B (en) * | 2020-03-16 | 2022-11-25 | Tcl华星光电技术有限公司 | LCD mother board |
| CN111679511B (en) * | 2020-06-04 | 2023-06-27 | Tcl华星光电技术有限公司 | Liquid crystal panel and photo-alignment method thereof |
| CN114185202A (en) * | 2021-12-13 | 2022-03-15 | 苏州华星光电技术有限公司 | Alignment circuit and liquid crystal display substrate |
| CN114815335B (en) * | 2022-04-07 | 2023-08-22 | 苏州华星光电技术有限公司 | Liquid crystal display mother board |
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