CN202472178U - Test circuit - Google Patents
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- CN202472178U CN202472178U CN2012201029183U CN201220102918U CN202472178U CN 202472178 U CN202472178 U CN 202472178U CN 2012201029183 U CN2012201029183 U CN 2012201029183U CN 201220102918 U CN201220102918 U CN 201220102918U CN 202472178 U CN202472178 U CN 202472178U
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Abstract
The utility model relates to the technical field of array substrate manufacture, in particular to a test circuit which is used for relieving the phenomenon of short circuit in the test circuit. The test circuit is characterized in that detection ports are arranged at a first outer side in the sequence of the first group of ports and then the second group of ports; detection ports are arranged at a second outer side in the sequence of the second group of ports and then the first group of ports; the first group of ports positioned at the first outer side are connected with data signal input ports of a first display panel through a first group of leading wires which are not crossed; the second group of ports are connected with signal input ports of a data signal input side of a second display panel through a second group of leading wires which are not crossed; and the detection ports positioned at the first outer side and the detection ports positioned at the second outer side are respectively connected through third-area leading wires which are not crossed; and the first group of leading wires and the second group of leading wires do not intersect mutually. The structure can relieve the phenomenon of short circuit.
Description
Technical field
The utility model relates to array base palte manufacturing technology field, relates in particular to a kind of test circuit.
Background technology
Whether the display panel that the peripheral test circuit on the array base palte is used for detecting this array base palte exists bad point to wait the bad phenomenon that influences vision.In order to improve testing efficiency, the peripheral test circuit can be respectively from the left side or the right side simultaneously the polylith display panel is detected.Introduce this for ease and sentence and comprise in the block array substrate that two display panels and the peripheral test circuit that these two display panels are tested are example, the structure of this array base palte is as shown in Figure 1:
Comprising first display panel 110 and second display panel 111; First grid detection port 101, second grid detection port 102; The detection port that second display panel 111 is tested: the first power supply utmost point constant voltage port one 03, the first even data input port one 04, the first odd data input port one 05; The detection port that first display panel 110 is tested: the second power supply utmost point constant voltage port one 06, the second even data input port one 07, the second odd data input port one 08; Because; This peripheral test circuit can be respectively from the left side or the right side these two display panels are detected; Therefore, also be provided with and the corresponding port of above-mentioned detection port on the right side of second display panel 111, the corresponding detection port in the left and right sides connects through circuit; The principle of work of this peripheral test circuit is following:
The first power supply utmost point constant voltage port one 03 and the second power supply utmost point constant voltage port one 06 are used to provide constant voltage; First grid detection port 101 is used for control TFT (Thin Film Transistor with second grid detection port 102; Opening or closing TFT); When TFT is in open mode; The source electrode of thin film transistor (TFT) and drain electrode conducting, the first even data input port one 04 and the first odd data input port one 05 input to the display voltage signal on the pixel electrode of second display panel 111 through drain electrode, and the public electrode on pixel electrode and the color membrane substrates forms vertical electric field; Whether drives liquid crystal molecules deflects, detect display panel with this and exist bad point to wait the bad phenomenon that influences vision.
But the inventor finds that as shown in Figure 1, there is circuit overlapping place, many places 112 in the circuit cabling in the existing peripheral test circuit; Because the restriction of working condition is easy on peripheral test circuit, produce static, when generation of static electricity during at circuit overlapping place 112, two circuits that can cause overlapping puncture, and cause short circuit phenomenon, damage the entire periphery test circuit in process of production.
The utility model content
The utility model embodiment provides a kind of test circuit, is used for improving the peripheral test circuit because the short circuit phenomenon that static causes.
A kind of test circuit is used for the display panel of detection arrays substrate, and said test circuit comprises:
In first arranged outside tactic detection port according to first group of port, second group of port is arranged;
Have according to said second group of port, said first group of tactic detection port of port in second arranged outside;
First group of port, second group of port in said first group of port in said first outside, second group of port and said second outside connect one to one through mutual Uncrossed lead-in wire;
Said first group of port links to each other with the data-signal input port of said first display panel through first group of lead-in wire of non-cross arrangement; Said second group of port links to each other with the data-signal input port of said second display panel through second group of lead-in wire of non-cross arrangement;
Said first group of lead-in wire mutually disjoints with said second group of lead-in wire.
A kind of test circuit is used for the display panel of detection arrays substrate, and this test circuit comprises:
In first arranged outside tactic detection port according to first group of port, second group of port is arranged; Said first outside is positioned at the outside of first display panel and not adjacent with second display panel;
In second arranged outside said second group of port arranged; Said second outside is positioned at the outside of second display panel and not adjacent with first display panel;
Be provided with said first group of port in the inboard; Said panel inboard is between said first display panel and said second display panel;
The signal input port of the port that the first group lead-in wire of first group of port in said first outside through non-cross arrangement and said panel are inboard and the data-signal input end of said second display panel links to each other; The signal input port of the port in second group of port, second group of lead-in wire through non-cross arrangement and said second outside and the data-signal input end of said first display panel links to each other;
Said second group of lead-in wire mutually disjoints with said first group of lead-in wire.
It is thus clear that, the test circuit that adopts the utility model embodiment to provide, therefore the overlapping phenomenon between can avoiding as much as possible going between can improve the overlapping phenomenon of lead-in wire, can improve the short circuit phenomenon that is overlapped and caused by lead-in wire, thereby guarantee the yield of product.
Description of drawings
Fig. 1 is the structural representation of peripheral test circuit in the prior art;
The structural representation of the test circuit that Fig. 2 provides for the utility model embodiment one;
The structural representation of the test circuit that Fig. 3 provides for the utility model embodiment two;
The structural representation of the test circuit that Fig. 4 provides for the utility model embodiment five;
Embodiment
The test circuit that adopts the utility model embodiment to provide, therefore the overlapping phenomenon between can avoiding as much as possible going between can improve the overlapping phenomenon of lead-in wire, can improve the short circuit phenomenon that is overlapped and caused by lead-in wire.Below with the practical implementation case introduction:
Embodiment one:
As shown in Figure 2; Embodiment one provides a kind of test circuit; Overlapping phenomenon between this test circuit can be avoided going between is fully introduced for ease and is comprised two display panels on this array base palte, is respectively first display panel 110; Second display panel 111 specifically also comprises: previously selected a plurality of ports;
A plurality of ports are respectively the detection port that second display panel 111 is tested: the first power supply utmost point constant voltage port one 03, the first even data input port one 04, the first odd data input port one 05; The detection port that first display panel is tested: the second power supply utmost point constant voltage port one 06, the second even data input port one 07, the second odd data input port one 08;
Wherein, first group of port comprises: the first power supply utmost point constant voltage port one 03, the first even data input port one 04, the first odd data input port one 05; Second group of port comprises: the second power supply utmost point constant voltage port one 06, the second even data input port one 07, the second odd data input port one 08; First group of port links to each other through lead-in wire with the data-signal input end 25 of its corresponding display panel respectively with second group of port;
As shown in Figure 2, first outside is positioned at the outside of first display panel 110 and not adjacent with second display panel 111; Comprise first group of port and second group of port in first outside 21.First group of port and the detection port in second group of port are as shown in Figure 2 can be according to the identical arrangement that puts in order, also inverted arrangements order as required;
As shown in Figure 2, second outside 22 is positioned at the outside of second display panel and not adjacent with first display panel; Detection port in the vertical direction in second outside 22; From top to down according to the arrangement that puts in order of second group of port, first group of port, promptly the second power supply utmost point constant voltage port one 06, the second even data input port one 07, the second odd data input port one 08, the first power supply utmost point constant voltage port one 03, the first even data input port one 04, the first odd data input port one 05 are arranged in order.
As shown in Figure 2, first group of port in said first outside 21 is connected with first group of lead-in wire of first group of port in said second outside 22 through non-cross arrangement, and arrangement mode and cabling guarantee that the institute in first group of lead-in wire is leaded non-intersect; Second group of port in said first outside 21 is connected with second group of lead-in wire of second group of port in said second outside 22 through non-cross arrangement, and arrangement mode and cabling guarantee second group of leaded mutually disjointing in the lead-in wire; First group of the detection port in said first outside 21 lead-in wire and second group of lead-in wire go between corresponding the connection with first group of lead-in wire of the detection port in said second outside 22 and second group respectively; Be same two detection port that type is identical that lead-in wire connects; And first group of lead-in wire passes through Uncrossed the 3rd group of lead-in wire 23 corresponding connections mutually with second group of lead-in wire, and concrete connected mode is following:
The first power supply utmost point constant voltage port one 03 in first outside 21 links to each other with the first power supply utmost point constant voltage port one 03 in second outside 22;
The first even data input port one 04 in first outside 21 links to each other with the first even data input port one 04 in second outside 22;
The first odd data input port one 05 in first outside 21 links to each other with the first odd data input port one 05 in second outside 22;
The second power supply utmost point constant voltage port one 06 in first outside 21 links to each other with the second power supply utmost point constant voltage port one 06 in second outside 22;
The second even data input port one 07 in first outside 21 links to each other with the second even data input port one 07 in second outside 22;
The second odd data input port one 08 in first outside 21 links to each other with the second odd data input port one 08 in second outside 22;
Preferable, overlapping mutually for fear of follow-up lead-in wire, first group of lead-in wire can be through the 3rd zone 23, and concrete wire laying mode includes but not limited to shown in Figure 2; Any lead-in wire in said the 3rd zone 23 does not intersect with any lead-in wire in this test circuit mutually, can not produce the overlapping place; Said the 3rd zone 23 is positioned at an opposite side of grid detection signal input end 24; The first grid detection port 101, the second grid detection port 102 that are used to control the TFT switch link to each other through lead-in wire respectively with its corresponding display panel signal input end 24.
Said second group of port comprises:
The first power supply utmost point constant voltage port one 03, the first even data input port one 04, the first odd data input port one 05;
Said first group of port comprises:
The second power supply utmost point constant voltage port one 06, the second even data input port one 07 and the second odd data input port one 08.
The data-signal input end 25 of first group of port and said first display panel 110 links to each other through first group of lead-in wire of non-cross arrangement; The data-signal input end 25 of second group of port and said second display panel 111 links to each other through second group of lead-in wire of non-cross arrangement; Second group the lead-in wire in lead-in wire mutually disjoint.
Preferable, for fear of the overlapping phenomenon, said first group of lead-in wire goes between through the 3rd regional 23 o'clock leaded mutually disjointing with said second group; The bar number of said first group of lead-in wire equates promptly 3 with the number of said first group of port; The bar number of said second group of lead-in wire equates promptly 3 with the number of said second group of port;
In the present embodiment, in any case wiring all should guarantee first group of lead-in wire and second group of lead-in wire leaded mutually disjointing in first outside 21, second outside 22 and the 3rd regional 23; Detection port in first group of port and the second group of port is vertically arranged point-blank, and this straight line is guaranteeing can to become arbitrarily angled with surface level under the leaded disjoint prerequisite of institute; Detection port symmetrical distribution and per two symmetrical detection port in said first outside and second outside are identical.
Further; The first group of port in first outside 21 and second outside 22 and the detection port of second group of port can be arranged arbitrarily as required; As long as guarantee in first outside 21 first group of port and second group of port in detection port put in order with second outside 22 in first group of port and second group of port can be corresponding one by one; For example: the detection port of first group of port in first outside 21 puts in order and is: the second even data input port one 07, the second power supply utmost point constant voltage port one 06, the second odd data input port one 08, and the detection port of first group of port puts in order and is: the second even data input port one 07, the second power supply utmost point constant voltage port one 06, the second odd data input port one 08 in the second corresponding with it outside 22.
Further; In order to reduce the test circuit area occupied; Also can be with any in a longitudinal direction arrangement of port in first outside 21 and second outside 22; As long as guarantee not intersect each other between first group of lead-in wire and second group of lead-in wire, can well avoid the line short problem that causes the puncture at overlapping place to cause because of electrostatic accumulation like this, improve the product yield.
Embodiment two:
As shown in Figure 3, present embodiment two also provides a kind of test circuit, the overlapping phenomenon between can avoiding fully going between, and the connected mode of the port of this test circuit can be referring to embodiment one; Present embodiment two is with the difference of embodiment one; The arrangement that is in line in a lateral direction of all detection port in first group of port in first outside 21 and second outside 22 and the second group of port, and the port in the port in first outside 21 and second outside 22 is corresponding one by one connects through mutual Uncrossed lead-in wire.
Further; Detection port in first outside 21 can be arranged arbitrarily smoothly; Can be for example as long as guarantee can not intersect corresponding one by one and mutually with the port in second outside: put in order one: it be the second power supply utmost point constant voltage port that first group of port in first outside 21 puts in order, the second even data input port and the second odd data input port; Put in order two: also can be from left to right: the second odd data input port, the second even data detection port and the second power supply utmost point constant voltage detection port; As long as guarantee that detection port order in first outside 21 is corresponding one by one with the detection port order in second outside 22 and mutually disjoint, it is unrestricted to put in order.
Further; All detection port in first outside 21 can not arranged on same straight line in a lateral direction yet; The arrangement that can misplace is arbitrarily in a lateral direction mutually disjointed between all detection port and lead-in wire corresponding one by one with the detection port in second outside 22 as long as guarantee in first outside 21.
Corresponding one by one and mutually disjoint through all detection port in first outside 21 and second outside 22 like this, like this institute leaded between overlapping place not, then avoid because of between going between because of electrostatic accumulation causes the generation of short circuit problem, thereby guarantee the product yield.
Embodiment three:
As shown in Figure 4, present embodiment five also provides a kind of test circuit, can improve the overlapping phenomenon between lead-in wire, and this test circuit comprises: first display panel 110, second display panel 111 and first group of port and second group of port;
Comprise in said second group of port:
The first power supply utmost point constant voltage port one 03, the first even data input port one 04 and the first odd data input port one 05;
Said first group of port comprises:
The second power supply utmost point constant voltage port one 06, the second even data input port one 07 and the second odd data input port one 08.
As shown in Figure 4, be arranged with first group of port and second group of port in first outside 21 according to the order of sequence; An other side of the data-signal input end 25 of first outside 21 and said second display panel 111; Be that said first outside is positioned at the outside of second display panel and not adjacent with first display panel 110.
As shown in Figure 4, be to be provided with first group of port in the panel inboard 41 between first display panel 110 and second display panel 111; First group of port in first group of port in said first outside 21 and the panel inboard 41 is connected through first group of lead-in wire of non-cross arrangement; First group of port in said first outside 21 connects one to one with port in inboard 41.
The concrete structure of the corresponding connection of port in first group of port in said first outside 21 and inboard 41 comprises:
In first outside 21 second power supply utmost point constant voltage port one 06 is connected with power supply utmost point constant voltage port in the inboard 41;
The second even data input port one 07 in first outside 21 is connected with even data input port in inboard 41;
The second odd data input port one 08 in first outside 21 is connected with odd data input port in inboard 41.
Lead-in wire in said first group of lead-in wire links to each other with the signal input port of the data-signal input end 25 of second display panel 111 respectively;
As shown in Figure 4, be provided with port in second outside 22; Port in second group of port in said first outside 21 and said second outside 22 is connected through second group of lead-in wire of non-cross arrangement; The corresponding connection of port in second group of port in said first outside 21 and second outside 22; Said second outside 22 links to each other with the signal input port of the data-signal input end 25 of said first display panel 110; Be that said second outside is positioned at the outside of second display panel 111 and not adjacent with first display panel 110;
The concrete structure of the corresponding connection of port in second group of port in said first outside 21 and second outside 22 comprises:
In first outside 21 first power supply utmost point constant voltage port one 03 is connected with power supply utmost point constant voltage port in second outside 22;
The first even data input port one 07 in first outside 21 is connected with the even data input port in second outside 22;
The first odd data input port one 08 in first outside 21 is connected with the odd data input port in second outside 22.
Lead-in wire in said second group of lead-in wire links to each other with the signal input port of the data-signal input end 25 of second display panel 110 respectively;
Preferable, said second group of lead-in wire mutually disjoints with said first group of lead-in wire.
First group of detection port and second group of detection port arrangement that is in line in vertical direction in first outside 21, and first group of detection port is corresponding one by one with the detection port of panel inboard 41; Second group of detection port in first outside 21 is corresponding one by one with the detection port in second outside 22.
Further, first group of detection port and second group of detection port in first outside 21 also can be transversely arranged in the horizontal direction, preferable, can be the arrangements that is in line in the horizontal direction in order to reduce the area that detection port takies array base palte.
Above-mentioned all embodiment also comprise first grid detection port of the prior art 101, second grid detection port 102, and the lead-in wire between these two ports; These two ports are connected through lead-in wire with the signal input port of the signal input end 24 of first display panel 110 corresponding with it or second display panel 111.
Detection port can also be placed in the optional position by random order among above-mentioned all embodiment, as long as guarantee on the basis of accomplishing test, institute is leaded all non-intersect, and the quantity that perhaps overlaps is less than overlapping quantity of the prior art and gets final product.
In sum, beneficial effect:
The test circuit that adopts the utility model embodiment to provide, therefore the overlapping phenomenon between can avoiding as much as possible going between can improve the overlapping phenomenon of lead-in wire, can improve the short circuit phenomenon that is overlapped and caused by lead-in wire.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from the spirit and the scope of the utility model.Like this, belong within the scope of the utility model claim and equivalent technologies thereof if these of the utility model are revised with modification, then the utility model also is intended to comprise these changes and modification interior.
Claims (10)
1. test circuit is used for the display panel of detection arrays substrate, it is characterized in that said test circuit comprises:
In first arranged outside tactic detection port according to first group of port, second group of port is arranged;
Have according to said second group of port, said first group of tactic detection port of port in second arranged outside;
First group of port, second group of port in said first group of port in said first outside, second group of port and said second outside connect one to one through mutual Uncrossed lead-in wire;
Said first group of port links to each other with the data-signal input port of said first display panel through first group of lead-in wire of non-cross arrangement; Said second group of port links to each other with the data-signal input port of said second display panel through second group of lead-in wire of non-cross arrangement;
Said first group of lead-in wire mutually disjoints with said second group of lead-in wire.
2. test circuit as claimed in claim 1 is characterized in that, all detection port in said first group of port and the second group of port are arranged point-blank.
3. test circuit as claimed in claim 1 is characterized in that, detection port symmetrical distribution and per two symmetrical detection port in said first outside and second outside are corresponding one by one.
4. test circuit as claimed in claim 1 is characterized in that, said first group of port comprises:
The second power supply utmost point constant voltage port, the second even data input port and the second odd data input port;
Said second group of port comprises:
The first power supply utmost point constant voltage port, the first even data input port, the first odd data input port.
5. test circuit as claimed in claim 4 is characterized in that, is positioned at the detection port and the detection port that is positioned at said second outside in said first outside, and the corresponding concrete syndeton that connects of the 3rd zone lead-in wire through non-cross arrangement comprises respectively:
The first power supply utmost point constant voltage port in first outside links to each other with the first power supply utmost point constant voltage port in second outside;
The first even data input port in first outside links to each other with the first even data input port in second outside;
The first odd data input port in first outside links to each other with the first odd data input port in second outside;
The second power supply utmost point constant voltage port in first outside links to each other with the second power supply utmost point constant voltage port in second outside;
The second even data input port in first outside links to each other with the second even data input port in second outside;
The second odd data input port in first outside links to each other with the second odd data input port in second outside.
6. test circuit is used for the display panel of detection arrays substrate, it is characterized in that said test circuit comprises:
In first arranged outside tactic detection port according to first group of port, second group of port is arranged; Said first outside is positioned at the outside of first display panel and not adjacent with second display panel;
In second arranged outside said second group of port arranged; Said second outside is positioned at the outside of second display panel and not adjacent with first display panel;
Be provided with said first group of port in the inboard; Said panel inboard is between said first display panel and said second display panel;
The signal input port of the port that the first group lead-in wire of first group of port in said first outside through non-cross arrangement and said panel are inboard and the data-signal input end of said second display panel links to each other; The signal input port of the port in second group of port, second group of lead-in wire through non-cross arrangement and said second outside and the data-signal input end of said first display panel links to each other;
Said second group of lead-in wire mutually disjoints with said first group of lead-in wire.
7. test circuit as claimed in claim 6 is characterized in that, said first group of port comprises:
The second power supply utmost point constant voltage port, the second even data input port and the second odd data input port;
Comprise in said second group of port:
The first power supply utmost point constant voltage port, the first even data input port and the first odd data input port.
8. test circuit as claimed in claim 7 is characterized in that, first group of port in said first outside comprises with the concrete structure that the inboard port of said panel is connected through first group of lead-in wire of non-cross arrangement:
In first outside second power supply utmost point constant voltage port is connected with power supply utmost point constant voltage port in the inboard;
The second even data input port in first outside is connected with the even data input port in the inboard;
The second odd data input port in first outside is connected with the odd data input port in the inboard.
9. test circuit as claimed in claim 7 is characterized in that, second group of port in said first outside comprises with the concrete structure that the port in second outside is connected:
In first outside first power supply utmost point constant voltage port is connected with power supply utmost point constant voltage port in second outside;
The first even data input port in first outside is connected with the even data input port in second outside;
The first odd data input port in first outside is connected with the odd data input port in second outside.
10. test circuit as claimed in claim 6 is characterized in that, the detection port in said first group of port is arranged point-blank;
Detection port in said second group of port is arranged point-blank.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201029183U CN202472178U (en) | 2012-03-16 | 2012-03-16 | Test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201029183U CN202472178U (en) | 2012-03-16 | 2012-03-16 | Test circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202472178U true CN202472178U (en) | 2012-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012201029183U Expired - Lifetime CN202472178U (en) | 2012-03-16 | 2012-03-16 | Test circuit |
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| Country | Link |
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| CN (1) | CN202472178U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407456A (en) * | 2014-12-18 | 2015-03-11 | 深圳市华星光电技术有限公司 | Array substrate and display device |
| CN109212799A (en) * | 2018-10-26 | 2019-01-15 | 深圳市华星光电技术有限公司 | The peripheral circuit structure and motherboard of liquid crystal display of liquid crystal display panel |
-
2012
- 2012-03-16 CN CN2012201029183U patent/CN202472178U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407456A (en) * | 2014-12-18 | 2015-03-11 | 深圳市华星光电技术有限公司 | Array substrate and display device |
| CN109212799A (en) * | 2018-10-26 | 2019-01-15 | 深圳市华星光电技术有限公司 | The peripheral circuit structure and motherboard of liquid crystal display of liquid crystal display panel |
| CN109212799B (en) * | 2018-10-26 | 2021-10-29 | Tcl华星光电技术有限公司 | Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board |
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Legal Events
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150623 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150623 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150623 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121003 |